Cache information updating method and apparatus, device, and medium

Abstract

The present disclosure provides a cached information updating method and device, a chip, an equipment and a medium, relates to the technical field of computers, and particularly relates to the chip technology and the cache technology field. The implementation scheme is: receiving a first read request for first data; in response to determining that the target read data of a plurality of cache lines is not the first data, marking the target read data of the first cache line as the first data; storing the first read request to a request set; updating the request identifier of the first cache line to indicate that there is a read request for the first data in the request set; receiving a second read request for the first data; in response to determining that there is the first cache line with the target read data being the first data, storing the request to the request set; when the first data is stored to the first cache line, reading the first data, returning the first and second read requests and removing them from the request set; and updating the request identifier of the first cache line to indicate that there is no read request for the first data in the request set.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of chip technology and cache technology, specifically to a cache information update method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of artificial intelligence technology, more and more applications are achieving results far exceeding those of traditional algorithms. Deep learning is a data-intensive and computationally intensive algorithm; to improve the execution efficiency of deep learning algorithms, it is necessary to improve the utilization rate of system cache.

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] This disclosure provides a method, apparatus, electronic device, computer-readable storage medium, and computer program product for updating cached information.

[0005] According to one aspect of this disclosure, a method for updating cached information is provided, comprising: receiving a first read request for first data; in response to determining that the target read data of a plurality of cache lines is not the first data, marking the target read data of a first cache line among the plurality of cache lines as the first data; storing the first read request to a request set; updating the request identifier of the first cache line to indicate that there is a read request for the first data in the request set; receiving a second read request for the first data; in response to determining that there is a first cache line with the target read data being the first data, and in response to determining that the first cache line does not contain the first data, storing the second read request to the request set; in response to determining that the first data is stored in the first cache line, reading the first data from the first cache line and returning the first read request and the second read request; removing the first read request and the second read request from the request set; and updating the request identifier of the first cache line to indicate that there is no read request for the first data in the request set.

[0006] According to another aspect of this disclosure, a cache information update apparatus is provided, comprising: a receiving unit configured to receive a first read request for first data; a marking unit configured to mark the target read data of a first cache line among the plurality of cache lines as the first data in response to determining that the target read data of all of the plurality of cache lines is not the first data; a storage unit configured to store the first read request to a request set; and an updating unit configured to update the request identifier of the first cache line to indicate that a read request for the first data exists in the request set; the receiving unit is further configured to receive a second read request for the first data; the storage unit... It is also configured to, in response to determining that a first cache line exists with the target read data being the first data, and in response to determining that the first cache line does not contain the first data, store the second read request to the request set; a read unit is configured to, in response to determining that the first data is stored in the first cache line, read the first data from the first cache line and return the first read request and the second read request; and a remove unit is configured to remove the first read request and the second read request from the request set; the update unit is further configured to update the request identifier of the first cache line to indicate that there is no read request for the first data in the request set.

[0007] According to another aspect of this disclosure, a chip is provided that includes the aforementioned cached information update device.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the aforementioned cached information update method.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform the aforementioned cached information update method.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, is capable of implementing the above-described cached information update method.

[0011] According to one or more embodiments of this disclosure, information updates can be cached.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0014] Figure 1 A schematic diagram of an exemplary system in which various methods described herein may be implemented, according to exemplary embodiments of the present disclosure;

[0015] Figure 2 A flowchart of a method for updating cached information according to an exemplary embodiment of the present disclosure is shown;

[0016] Figure 3 A schematic diagram of a cache data structure according to an exemplary embodiment of the present disclosure is shown;

[0017] Figure 4 A structural block diagram of a cached information updating apparatus according to an exemplary embodiment of the present disclosure is shown;

[0018] Figure 5 A schematic diagram of the structure of a data reading apparatus according to an exemplary embodiment of the present disclosure is shown;

[0019] Figure 6 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0020] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to define the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0022] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0023] Typically, the data processing unit executing deep learning algorithms needs to send data read requests to the main memory to obtain the data to be processed. During convolution operations, the same data in the main memory is often accessed repeatedly within a short period. Therefore, a cache can be set up between the data processing unit and the main memory to store accessed data. When a read request is received from the data processing unit for data included in the cache, it can be read directly from the cache.

[0024] In this scenario, when a read request is received from the data processing unit for data not included in the cache, a read request needs to be sent to the main memory. In related technologies, a corresponding cache line is typically allocated for the aforementioned pending read request, and the read request is stored in a specific register to await the main memory returning the corresponding data. However, in this implementation, when multiple pending read requests exist for the same data, read requests will be repeatedly sent to the main memory, repeatedly occupying cache lines, thereby reducing cache utilization.

[0025] Based on this, this disclosure provides a method for updating cache information, which stores a data read request count value corresponding to each cache line in the cache to indicate the number of multiple pending read requests associated with each cache line, so that multiple pending read requests pointing to the same data can reuse the data to be read in a cache line, thereby improving cache utilization.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of an exemplary system 100 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 1 The system 100 includes one or more client devices 101, 102, 103, 104, 105 and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105 and 106 can be configured to execute one or more applications.

[0028] In embodiments of this disclosure, server 120 may run one or more services or software applications that enable the execution of cached information update methods.

[0029] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 101, 102, 103, 104, 105, and / or 106 under a Software as a Service (SaaS) model.

[0030] exist Figure 1 In the configuration shown, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can sequentially interact with server 120 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 100. Therefore, Figure 1 This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0031] Users can use client devices 101, 102, 103, 104, 105, and / or 106 to send data read requests. The client devices can provide an interface that allows users to interact with the client devices. The client devices can also output information to the user through this interface. Although... Figure 1 Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0032] Client devices 101, 102, 103, 104, 105, and / or 106 may include various categories of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various categories and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices can run a variety of different applications, such as various Internet-related applications, communication applications (e.g., email applications), short message service (SMS) applications, and can use various communication protocols.

[0033] Network 110 can be any type of network well known to those skilled in the art, and can use any of a variety of available protocols (including but not limited to TCP / IP, SNA, IPX, etc.) to support data communication. By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0034] Server 120 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0035] The computing unit in server 120 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 120 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0036] In some implementations, server 120 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0037] In some implementations, server 120 can be a server for a distributed system or a server integrated with blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0038] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. Databases 130 may reside in various locations. For example, a database used by server 120 may be local to server 120, or it may be located away from server 120 and may communicate with server 120 via a network-based or dedicated connection. Databases 130 may be of different categories. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve data from and from the databases in response to commands.

[0039] In some embodiments, one or more of the databases 130 may also be used by an application to store application data. The databases used by the application may be different categories of databases, such as key-value stores, object stores, or regular stores supported by a file system.

[0040] Figure 1The system 100 can be configured and operated in various ways to enable the application of the various methods and apparatus described in this disclosure.

[0041] Figure 2 A flowchart of a cache information update method 200 according to an exemplary embodiment of the present disclosure is shown, wherein the cache includes multiple cache lines. Figure 2 As shown, method 200 includes:

[0042] Step S201: Receive the first read request for the first data;

[0043] Step S202: In response to determining that the target read data of the plurality of cache lines is not the first data, mark the target read data of the first cache line among the plurality of cache lines as the first data;

[0044] Step S203: Store the first read request to the request set, and update the request identifier of the first cache line to indicate that there is a read request for the first data in the request set;

[0045] Step S204: Receive a second read request for the first data;

[0046] Step S205: In response to determining that there is a first cache line containing the first data as the target read data, and in response to determining that the first cache line does not contain the first data, the second read request is stored in the request set;

[0047] Step S206: In response to determining that the first data is stored in the first cache line, read the first data from the first cache line and return the first read request and the second read request; and

[0048] Step S207: Remove the first read request and the second read request from the request set, and update the request identifier of the first cache line to indicate that there is no read request for the first data in the request set.

[0049] Therefore, by utilizing the request identifier of the first cache line, it is possible to indicate whether there are any pending read requests associated with the first cache line in the request set. When the first data has not yet been returned to the first cache line, for a received second read request pointing to the same first data, only the second read request needs to be stored in the request set. This allows the first and second read requests to reuse the data in the cache line after the first data is stored there, thereby improving cache utilization. Furthermore, in this scenario, the first cache line only needs to issue one read request for the first data to the main memory, reducing the consumption of main memory access resources.

[0050] According to some embodiments, the request identifier is a request count value. The request count value of the first cache line can indicate the number of read requests for the first data in the request set. Specifically, after storing the first read request into the request set, the count value of the first cache line is incremented by one; after storing the second read request into the request set, the count value of the first cache line is also incremented by one. Therefore, the request count value can be used to simply and efficiently indicate the number of read requests for the first data in the request set.

[0051] In some examples, step S202 may involve randomly selecting a first cache line from the plurality of cache lines and marking its target read data as the first data, or it may involve determining the first cache line from the plurality of cache lines based on a preset strategy, and there is no limitation on this.

[0052] According to some embodiments, in step S202, the target read data of the first cache line among the plurality of cache lines with a request count value of zero is marked as the first data. When the request count value of a cache line is not zero, it indicates that the request set also includes pending read requests waiting for the target read data corresponding to that cache line. By selecting the first cache line with a request count value of zero, it is possible to avoid the cache line associated with pending requests being occupied by new requests.

[0053] The applicant noted that in practical application scenarios, for multiple ordered data read requests received, it is necessary to return the corresponding data to the requester in an orderly manner to ensure the timing of data processing.

[0054] Based on this, according to some embodiments, the data structure of the request set is a first-in-first-out (FIFO) queue. Step S206, reading the first data from the first cache line and returning the first read request and the second read request, includes: in response to determining that the first read request is located at the dequeue position of the queue, reading the first data from the first cache line and returning the first read request; and in response to determining that the second read request is located at the dequeue position of the queue, reading the first data from the first cache line and returning the second read request. Thus, the FIFO queue data structure can be used to achieve the orderly return of multiple data read requests, that is, returning them to the request sender according to the receiving order of the multiple data read requests, thereby ensuring the timing of data processing.

[0055] Furthermore, according to some embodiments, when the request is identified as a request count value, in step S207, in response to determining that the first data has been returned to the first read request, the first read request is removed from the request set, and the request count value of the first cache line is decremented by one; in response to determining that the first data has been returned to the second read request, the second read request is removed from the request set, and the request count value of the first cache line is decremented by one. By updating the request count value of the cache line based on the read request removal operation in the request set, the request count value can be used to accurately indicate the number of read requests in the request set targeting the cache line for reading data.

[0056] In this case, method 200 may further include: in response to determining that a first cache line exists containing the first data as the target read data, and in response to determining that the queue is not empty, storing the second read request into the request set, and incrementing the request count value of the first cache line. Thus, the second data read request can be temporarily stored in the request set when the queue is not empty, ensuring the ordered nature of the returned data.

[0057] In some examples, the cache can be shared by multiple data processing units, allowing it to receive data read requests from different units. In this case, each data read request issued in an orderly manner by a processing unit needs to be returned in an orderly fashion.

[0058] Based on this, according to some embodiments, the request set includes a first sub-queue and a second sub-queue. In step S201, the first read request is received from the first processing unit; in step S204, a second read request is received from a second processing unit different from the first processing unit; and in step S203, the first read request is stored in the first sub-queue, and in step S205, the second read request is stored in the second sub-queue. Thus, the first and second sub-queues can be used to store data read requests sent by different processing units respectively, efficiently processing data read requests from different processing units in parallel, improving data reading efficiency, while ensuring ordered data return for each processing unit.

[0059] According to some embodiments, each of the plurality of cache lines includes a cache data identifier for indicating the target read data of that cache line, and wherein step S202, marking the target read data of the first cache line among the plurality of cache lines as the first data, includes: updating the cache data identifier of the first cache line to a first data identifier corresponding to the first data, and wherein, in response to determining that the cache data identifier of the first cache line is the first data identifier, and in response to determining that the first cache line does not contain the first data, the second read request for the first data is stored in the request set. Thus, the cache data identifier can be used to indicate the target read data of a cache line, and when a new read request is received, by comparing the identifier of the data pointed to by the new read request with the cache data identifier, it is possible to easily and efficiently determine whether there is a matched cache line among the plurality of cache lines.

[0060] According to some embodiments, the first data identifier is the storage address of the first data in main memory. Therefore, the storage address can be used to easily and efficiently instruct the target to read data.

[0061] In some examples, the first data identifier can also be of other types. For example, when the data in the main memory is stored in the form of an index table, the index corresponding to the first data can be used as the first data identifier.

[0062] According to some embodiments, method 200 further includes: marking the first cache line as invalid after marking the target read data in the plurality of cache lines as the first data; and marking the first cache line as valid in response to determining that the first data is stored in the first cache line, and in step S206, reading the first data from the first cache line in response to determining that the first cache line is valid. Thus, the valid or invalid status of a cache line can be used to easily and accurately indicate whether the cache line includes data corresponding to its cached data identifier.

[0063] In some examples, a binary valid status flag can be used to indicate whether the data in the cache line is valid or invalid. For example, a valid status flag of 1 can be assigned to indicate that the data in the cache line is valid, and a valid status flag of 0 can be assigned to indicate that the data in the cache line is invalid.

[0064] Figure 3 A schematic diagram of the data structure of cache 300 according to an exemplary embodiment of the present disclosure is shown. Figure 3As shown, cache 300 includes multiple cache lines, each containing a valid status identifier, a request count, a cache data identifier, and cache data. In one example, when the cache is shared by multiple data processing units, each data processing unit can read or update the above information in cache 300 to improve the utilization of cache lines and increase data reading efficiency.

[0065] In one example, the first processing unit and the second processing unit share the same cache 300 to initiate read requests. A read request with data identifier 'a' corresponds to data A, and a read request with data identifier 'b' corresponds to data B. By executing the above method 200, this example may include, for example, the following process:

[0066] S1. Receive a read request with data identifier a sent by the first processing unit;

[0067] S2. In response to the determination that the cache data identifier of any cache line in the cache is not a, update the cache data identifier of cache line A with a request count value of 0 to a, update the request count value to 1, mark cache line A as invalid data, and send a read request with data identifier a to the main memory.

[0068] S3. Store the read request with data identifier 'a' into the first queue;

[0069] S4. Receive a read request with data identifier b sent by the second processing unit;

[0070] S5. In response to the determination that the cache data identifier of any cache line in the cache is not b, update the cache data identifier of cache line B with a request count value of 0 to b, update the request count value to 1, mark cache line B as invalid data, and send a read request with data identifier b to the main memory.

[0071] S6. Store the read request with data identifier b into the second queue;

[0072] S7. Receive a read request with data identifier b sent by the first processing unit;

[0073] S8. Update the request count value of cache line B to 2;

[0074] S9. Store the read request with data identifier b into the first queue;

[0075] S10. Receive a read request with data identifier a sent by the second processing unit;

[0076] S11. Update the request count value of cache line A to 2;

[0077] S12. Store the read request with data identifier 'a' into the second queue;

[0078] S13. In response to determining that data A has been stored in cache line A, mark cache line A as valid data;

[0079] S14. In response to determining that the read request with data identifier a is located at the dequeue position of the first queue, return data A to the first processing unit, remove the read request with data identifier a from the first queue, and update the request count value of cache line A to 1.

[0080] S15. In response to determining that data B has been stored in cache line B, mark cache line B as valid data.

[0081] S16. In response to determining that the read request with data identifier b is located at the dequeue position of the second queue, return data B to the second processing unit, remove the read request with data identifier b from the second queue, and update the request count value of cache line B to 1.

[0082] S17. In response to determining that the read request with data identifier a is located at the dequeue position of the second queue, return data A to the second processing unit, remove the read request with data identifier a from the second queue, and update the request count value of cache line A to 0.

[0083] S18. In response to determining that the read request with data identifier b is located at the dequeue position of the first queue, return data B to the first processing unit, remove the read request with data identifier b from the first queue, and update the request count value of cache line B to 0.

[0084] It can be seen that the first and second processing units issued a total of 4 read requests. By utilizing the method 200 described in this disclosure, the two read requests with data identifier 'a' can share cache line A, and the two read requests with data identifier 'b' can share cache line B. Furthermore, the cache only issued 2 read requests to the main memory. For the second processing unit, although the data A corresponding to its second read request is stored in the cache first, before the data B corresponding to the first read request is returned, because the second read request is not in the dequeue position of the second queue, the data A corresponding to the second read request is not returned to the second processing unit. At this time, the request count value of cache line A is 1, ensuring that the data A in cache line A is not replaced until it is returned to the second processing unit. Thus, multiple data are returned according to the receiving order of their corresponding multiple data read requests, ensuring the data processing sequence.

[0085] According to another aspect of this disclosure, a cached information updating device is also provided. Figure 4 A structural block diagram of a cache information update apparatus 400 according to an exemplary embodiment of the present disclosure is shown, the cache including multiple cache lines. Figure 4 As shown, the device 400 includes:

[0086] The receiving unit 401 is configured to receive a first read request for the first data;

[0087] The marking unit 402 is configured to mark the target read data of the first cache line among the plurality of cache lines as the first data in response to determining that the target read data of the plurality of cache lines is not the first data.

[0088] Storage unit 403 is configured to store the first read request into the request set;

[0089] The update unit 404 is configured to update the request identifier of the first cache line to indicate that there is a read request for the first data in the request set;

[0090] The receiving unit 401 is also configured to receive a second read request for the first data;

[0091] Storage unit 403 is also configured to store the second read request into the request set in response to determining that there is a first cache line containing the first data as the target read data, and in response to determining that the first cache line does not contain the first data;

[0092] Read unit 405 is configured to, in response to determining that the first data is stored in the first cache line, read the first data from the first cache line and return the first read request and the second read request; and

[0093] Removal unit 406 is configured to remove the first read request and the second read request from the request set;

[0094] The update unit 404 is also configured to update the request identifier of the first cache line to indicate that there is no read request for the first data in the request set.

[0095] According to some embodiments, the request identifier is a request count value, the request count value of the first cache line can indicate the number of read requests for the first data in the request set, and wherein the update unit 404 is configured to perform an increment update on the count value of the first cache line after the first read request is stored in the request set, and is also configured to perform an increment update on the count value of the first cache line after the second read request is stored in the request set.

[0096] According to some embodiments, the marking unit 402 is configured to mark the target read data of the first cache line among the plurality of cache lines with a request count value of zero as the first data.

[0097] According to some embodiments, the data structure of the request set is a first-in-first-out queue, and the reading unit 405 is configured to: in response to determining that the first read request is located at the dequeue position of the queue, read the first data from the first cache line and return the first read request; in response to determining that the second read request is located at the dequeue position of the queue, read the first data from the first cache line and return the second read request.

[0098] According to some embodiments, when the request is identified as a request count value, the removal unit 406 is configured to: remove the first read request from the request set in response to determining that the first data has been returned to the first read request, and the update unit 404 is configured to perform a decrement update on the request count value of the first cache line; and remove the second read request from the request set in response to determining that the first data has been returned to the second read request, and the update unit 404 is configured to perform a decrement update on the request count value of the first cache line.

[0099] According to some embodiments, the receiving unit 401 is configured to receive the first read request from the first processing unit and the second read request from the second processing unit, which is different from the first processing unit, and the request set includes a first sub-queue and a second sub-queue, and the storage unit 403 is configured to store the first read request in the first sub-queue and the second read request in the second sub-queue.

[0100] According to some embodiments, each of the plurality of cache lines includes a cache data identifier for indicating the target read data of the cache line, and wherein the marking unit 402 is configured to update the cache data identifier of the first cache line to a first data identifier corresponding to the first data, and wherein the storage unit 403 is configured to store the second read request for the first data to the request set in response to determining that the cache data identifier of the first cache line is the first data identifier and in response to determining that the first cache line does not contain the first data.

[0101] According to some embodiments, the first data identifier is the storage address of the first data in the main memory.

[0102] According to some embodiments, the marking unit 402 is further configured to: mark the first cache line as invalid after marking the target read data of the first cache line among the plurality of cache lines as the first data; and mark the first cache line as valid in response to determining that the first data is stored in the first cache line, and wherein the reading unit 405 is configured to read the first data from the first cache line in response to determining that the first cache line is valid.

[0103] The operation of units 401-406 of the cached information update device 400 is similar to the operation of steps S201-S207 described above, and will not be repeated here.

[0104] Figure 5 A schematic diagram of the structure of a data reading apparatus 500 according to an exemplary embodiment of the present disclosure is shown. Figure 5 As shown, the data reading device 500 may include: a main memory 510, an arbitration unit 520, a cache 300, and multiple cache information updating devices 400. The multiple devices 400 are respectively used to process data read requests from different processing units, and store the received data read requests into their respective first sub-queues 531, second sub-queues 532, and third sub-queues 533. The solid arrows in the figure indicate the flow of data read requests, and the dashed arrows indicate the flow of information in the cache 300.

[0105] For example, the operation of the data reading device includes the following steps:

[0106] S21. The device 400 corresponding to the first sub-queue 531 receives a third data read request;

[0107] S22. In response to the determination that the first sub-queue 531 is not full, execute the following sub-steps S3-S4:

[0108] S23. In response to determining that the third data identifier included in the third data read request is the same as the cache data identifier of the third cache line, the request count value of the third cache line is incremented by one, and the third data read request information is stored in the first sub-queue 531.

[0109] S24. In response to determining that the third data identifier included in the third data read request is different from the cache data identifier of any cache line, and in response to determining that there is a third cache line with a request count value of zero, update the cache data identifier of the third cache line to the third data identifier, increment the request count value of the third cache line, send a data read request for the third data to the arbitration unit 520, mark the third cache line as invalid data, and store the third data read request information in the first sub-queue 531.

[0110] S25. Arbitration unit 520, in response to receiving multiple data read requests, sorts them according to a preset strategy and sends them sequentially to main memory 510. The preset strategy may be, for example, a polling strategy, or sorting based on the priority information of each processing unit configured manually, and is not limited thereto.

[0111] S26, the main memory 510 writes the third data into the third cache line and marks the third cache line as valid;

[0112] S27. In response to determining that the third data read request is in the dequeue position of the first subqueue 531, the device 400 corresponding to the first subqueue 531 reads the third data from the third cache line and returns the third data read request, removes the third data read request from the first subqueue 531, and performs a decrement update on the request count value of the third cache line.

[0113] According to another aspect of this disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the cached information update method described above.

[0114] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause the computer to perform the above-described cached information update method.

[0115] According to another aspect of this disclosure, a computer program product is also provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the above-described method for updating cached information.

[0116] refer to Figure 6 The present invention describes a structural block diagram of an electronic device 600 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0117] like Figure 6As shown, device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 602 or a computer program loaded from storage unit 608 into random access memory (RAM) 603. RAM 603 may also store various programs and data required for the operation of device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0118] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, output unit 607, storage unit 608, and communication unit 609. Input unit 606 can be any type of device capable of inputting information to device 600. Input unit 606 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 607 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 608 may include, but is not limited to, a hard disk and an optical disk. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0119] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the cached information update method. For example, in some embodiments, the cached information update method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the cached information update method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the cached information update method by any other suitable means (e.g., by means of firmware).

[0120] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0121] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0122] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0123] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0124] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, and blockchain networks.

[0125] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0126] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0127] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A method of updating cached information, the cache comprising a plurality of cache lines, the method comprising: receiving a first read request for first data; in response to determining that none of the plurality of cache lines has target read data that is the first data, marking target read data of a first cache line of the plurality of cache lines as the first data; storing the first read request to a request set; updating a request identification of the first cache line to indicate that there is a read request for the first data in the request set; receiving a second read request for the first data; in response to determining that there is a first cache line having target read data that is the first data, and in response to determining that the first data is not included in the first cache line, storing the second read request to the request set; in response to determining that the first data is stored in the first cache line, reading the first data from the first cache line and returning the first read request and the second read request; removing the first read request and second read request from the request set; and updating the request identification of the first cache line to indicate that there is no read request for the first data in the request set. the request identification is a request count value, the request count value of the first cache line is capable of indicating a number of read requests for the first data in the request set, 2. The method of claim 1, wherein, and wherein the count value of the first cache line is incremented by one after storing the first read request to the request set, and wherein the count value of the first cache line is incremented by one after storing the second read request to the request set. marking target read data of a first cache line of the plurality of cache lines having a request count value of zero as the first data.

3. The method of claim 2, wherein, the data structure of the request set is a first-in-first-out queue, the reading the first data from the first cache line and returning the first read request and the second read request comprises:

4. The method of any one of claims 1-3, wherein, in response to determining that the first read request is at a dequeue position of the queue, reading the first data from the first cache line and returning the first read request; in response to determining that the second read request is at the dequeue position of the queue, reading the first data from the first cache line and returning the second read request.

5. The method of claim 4, when the request identification is a request count value, the removing the first read request and second read request from the request set, and updating the request identification of the first cache line comprises: in response to determining that the first data has been returned to the first read request, removing the first read request from the request set and decrementing the request count value of the first cache line by one; in response to determining that the first data has been returned to the second read request, removing the second read request from the request set and decrementing the request count value of the first cache line by one.

6. The method of claim 4 or 5, wherein: the first read request is received from a first processing unit, the second read request is received from a second processing unit different from the first processing unit, ​ And wherein the request set includes a first sub-queue and a second sub-queue, the first read request is stored to the first sub-queue, and the second read request is stored to the second sub-queue.

7. The method of any one of claims 1-6, wherein, Each cache line of the plurality of cache lines includes a cache data tag to indicate target read data of the cache line, and wherein the marking the target read data of the first cache line of the plurality of cache lines as the first data includes: updating the cache data tag of the first cache line to a first data tag corresponding to the first data, And wherein, in response to determining that the cache data tag of the first cache line is the first data tag, and in response to determining that the first data is not included in the first cache line, the second read request for the first data is stored to the request set.

8. The method of claim 7, wherein, The first data tag is a storage address of the first data in a main memory.

9. The method of any of claims 1-8, further comprising: after marking the target read data of the first cache line of the plurality of cache lines as the first data, marking the first cache line as a data invalid state; And in response to determining that the first data is stored in the first cache line, marking the first cache line as a data valid state, And wherein, in response to determining that the first cache line is in the data valid state, reading the first data from the first cache line.

10. An apparatus for updating information of a cache, the cache including a plurality of cache lines, the apparatus comprising: a receiving unit configured to receive a first read request for first data; a marking unit configured to, in response to determining that target read data of the plurality of cache lines is not the first data, mark target read data of a first cache line of the plurality of cache lines as the first data; a storing unit configured to store the first read request to a request set; an updating unit configured to update a request tag of the first cache line to indicate that there is a read request for the first data in the request set; the receiving unit is further configured to receive a second read request for the first data; the storing unit is further configured to, in response to determining that there is a first cache line having target read data as the first data, and in response to determining that the first data is not included in the first cache line, store the second read request to the request set; a reading unit configured to, in response to determining that the first data is stored in the first cache line, read the first data from the first cache line and return the first read request and the second read request; And a removing unit configured to remove the first read request and the second read request from the request set; the updating unit is further configured to update the request tag of the first cache line to indicate that there is no read request for the first data in the request set.

11. The apparatus of claim 10, wherein, The request tag is a request count value, and the request count value of the first cache line is able to indicate a number of read requests for the first data in the request set, and wherein the updating unit is configured to perform a plus one update on the count value of the first cache line after the first read request is stored to the request set, and is further configured to perform a plus one update on the count value of the first cache line after the second read request is stored to the request set.

12. The apparatus of claim 11, wherein, The marking unit is configured to mark target read data of a first cache line of the plurality of cache lines whose request count value is zero as the first data.

13. The apparatus of any of claims 10-12, wherein, The data structure of the request set is a first-in-first-out queue, and the reading unit is configured to: read the first data from the first cache line and return the first read request in response to determining that the first read request is located at a dequeue position of the queue; read the first data from the first cache line and return the second read request in response to determining that the second read request is located at the dequeue position of the queue.

14. The apparatus of claim 13, when the request is identified as a request count value, the removing unit is configured to: remove the first read request from the request set in response to determining that the first data has been returned to the first read request, and the updating unit is configured to perform a minus one update on the request count value of the first cache line; remove the second read request from the request set in response to determining that the first data has been returned to the second read request, and the updating unit is configured to perform a minus one update on the request count value of the first cache line.

15. The apparatus of claim 13 or 14, wherein: the receiving unit is configured to receive the first read request from a first processing unit, and receive a second read request from a second processing unit different from the first processing unit, and the request set comprises a first sub-queue and a second sub-queue, and the storing unit is configured to store the first read request to the first sub-queue, and store the second read request to the second sub-queue.

16. The apparatus of any one of claims 10-15, wherein, Each cache line of the plurality of cache lines comprises a cache data identifier for indicating target read data of the cache line, and wherein the marking unit is configured to: update the cache data identifier of the first cache line to a first data identifier corresponding to the first data, and wherein the storing unit is configured to store the second read request for the first data to the request set in response to determining that the cache data identifier of the first cache line is the first data identifier, and in response to determining that the first data is not included in the first cache line.

17. The apparatus of claim 16, wherein, The first data identifier is a storage address of the first data in a main memory.

18. The apparatus of any one of claims 10-17, the marking unit is further configured to: after marking target read data of a first cache line of the plurality of cache lines as the first data, mark the first cache line as a data invalid state; and in response to determining that the first data is stored to the first cache line, mark the first cache line as a data valid state, And wherein, The read unit is configured to read the first data from the first cache line in response to determining that the first cache behavior data valid state.

19. A chip comprising the apparatus of any of claims 10-18.

20. An electronic device, comprising: at least one processor; and memory connected with the at least one processor in communication; wherein the memory has stored instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any of claims 1-9.

21. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing a computer to perform the method of any of claims 1-9.

22. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any of claims 1-9. The computer program, when executed by a processor, implements the method of any of claims 1-9.

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