An agent model-based simulation vector automatic generation method for assertion coverage
By using a proxy model-based approach, combined with lightweight analog vector generation and Surrogate technology, analog vectors that simultaneously activate multiple assertions are generated. This solves the problems of insufficient assertion coverage and state space explosion in existing technologies, improves the efficiency and accuracy of analog vector generation, and helps to discover defects in hardware design.
Patent Information
- Application Number
- CN202211219750.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-30
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2042-09-30
AI Technical Summary
In existing technologies, analog vector generation methods suffer from problems such as incomplete assertion coverage, state space explosion, and high solution complexity. They are difficult to efficiently activate assertions containing intermediate signals and have high time overhead.
A surrogate-based approach is adopted, combining lightweight analog vector generation and Surrogate technology to generate analog vectors that simultaneously activate multiple assertions. Machine learning tools are used to generate the mapping relationship between input signals and intermediate signals, and coverage analysis guides the generation of analog vectors.
It improves the efficiency and accuracy of analog vector generation, reduces the coverage of corners, enables rapid generation of analog vectors, and helps identify defects in hardware design.
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Figure CN115544924B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application mainly relates to the field of verification technology of ultra large scale integrated circuits, in particular to a simulation vector automatic generation method based on agent model and oriented to assertion coverage. BACKGROUND
[0002] In modern electronic design automation flow, the increase of complexity and the shortening of time to market make functional verification the main bottleneck in hardware design flow. Among them, simulation (simulation) plays an irreplaceable role in functional verification. Functional verification based on simulation is a key and time-consuming step. In this step, a large number of simulation vectors are generally used to simulate the design, and the signals are monitored to determine whether the coverage target or functional requirements are met.
[0003] And random simulation vector generation, constraint solving simulation vector generation based on random sampling and directed simulation vector generation are the three most widely used methods of test generation in simulation verification.
[0004] Using constraint solving based on random sampling for simulation vector generation is one of the mainstream methods in today's hardware verification flow. It requires randomly generated simulation vectors to meet a set of specified input constraints, and then applies these input constraints to verify the given design characteristics through simulation. The efficiency of the whole process depends largely on: (1) the performance of the constraint solver; (2) the distribution of the generated solution. And this work has been relatively mature, such as the hybrid solver based on Markov chain Monte Carlo method, random simulation vector generation based on entropy and XOR constraint.
[0005] On the contrary, the goal of directed simulation vector generation is to use fewer simulation vectors to activate specific coverage targets (functional requirements), which is also one of the mainstream methods of simulation vector generation. Directed test generation mainly generates simulation vectors for specified design characteristics, and there is also a lot of work in this area, such as the bounded model checking (BMC) method based on Boolean satisfiability (SAT), the combination of random simulation based on symbolic execution and RTL model.
[0006] The above existing traditional methods still have certain deficiencies:
[0007] 1. When using constraint solving simulation vector generation based on random sampling, there will always be assertions that are not covered.
[0008] 2. When using formal method based directed test generation, state space explosion causes the solution complexity to increase dramatically.
[0009] 3. When combining formal method based directed simulation vector generation and constraint solving simulation vector generation based on random sampling, a lot of solution accuracy is lost.
[0010] The above problems are the main problems existing in the field of hardware simulation vector generation. When generating simulation vectors, since intermediate signals embody circuit information, simulation vector generation based on random sampling is difficult to activate assertions containing intermediate signals; and in order to activate these assertions containing intermediate signals, the directed simulation based on formalized methods is used to automatically generate, which introduces the problems of state space explosion and time consumption explosion caused by analyzing the circuit. SUMMARY
[0011] The technical problem to be solved by the present application is that, in view of the technical problems existing in the prior art, the present application provides a simulation vector automatic generation method based on a proxy model and oriented to assertion coverage, which is simple in principle, easy to operate and can improve efficiency.
[0012] To solve the above technical problems, the present application adopts the following technical solutions:
[0013] A simulation vector automatic generation method based on a proxy model and oriented to assertion coverage, comprising:
[0014] Lightweight simulation vector automatic generation, which is directed to assertion statements in which the precondition only involves module inputs in a System Verilog file;
[0015] Proxy model generation, which is directed to the generation of a proxy model for assertions with complex preconditions in a System Verilog file;
[0016] Multi-assertion simulation vector automatic generation, which generates simulation vectors that activate multiple assertions at the same time.
[0017] As a further improvement of the present application, the assertions involved in the System Verilog file include:
[0018] (a) assertions in which the precondition only contains module input signals;
[0019] (b) assertions in which the precondition contains intermediate signals and output signals in addition to module input signals.
[0020] As a further improvement of the present application, the process of lightweight simulation vector automatic generation is accompanied by a process of analysis and guidance for assertion coverage.
[0021] As a further improvement of the present application, the analysis and guidance for assertion coverage means that after each round of simulation vector generation, the coverage of assertions is obtained according to the simulation results, and the next round of simulation vector generation is guided.
[0022] As a further improvement of the present application, the assertion statements in which the precondition only involves module input signals are generated by a random sampling tool.
[0023] As a further improvement of the application: the random sampling tool uses the constraint file written in the constraint description standard in the process, to generate the value of the variable satisfying the constraint mentioned in the constraint file, that is, the simulation vector.
[0024] As a further improvement of the application: the generation of the agent model includes converting the assertion involving the intermediate signal into the assertion involving only the input signal on the basis of incomplete expansion circuit analysis.
[0025] As a further improvement of the application: the generation of the agent model is completed by a machine learning tool, including: given a Verilog file, automatically and quickly generating an assertion, that is, an approximate mapping relationship between the input signal and the intermediate signal.
[0026] As a further improvement of the application: the machine learning tool generates a Surrogate model, converts the assertion involving the intermediate signal into the assertion involving only the input signal by using the mapping relationship between the input signal and the intermediate signal obtained by the machine learning tool, and leaves it to the lightweight simulation vector generation.
[0027] As a further improvement of the application: the process of automatic generation of the multi-assertion simulation vector includes: analyzing the precondition of the assertion, building the precondition of the assertion into a tree structure, and finding the inclusion relationship between the trees.
[0028] Compared with the prior art, the application has the advantages that:
[0029] 1. The simulation vector automatic generation method based on the agent model and oriented to the assertion coverage ratio has the advantages of fast speed, multiple generated simulation vectors, and reduced coverage corners, by combining the simulation vector generation technology based on random sampling and the directional simulation vector automatic generation technology based on the Surrogate technology.
[0030] 2. The simulation vector automatic generation method based on the agent model and oriented to the assertion coverage ratio integrates the coverage rate analysis tool and the simulation vector automatic generation tool, takes the coverage rate analysis result as the guiding input of the simulation vector generation, and improves the simulation vector generation accuracy.
[0031] 3. The simulation vector automatic generation method based on the agent model and oriented to the assertion coverage ratio improves the directional simulation vector automatic generation based on the formal method, improves the simulation vector generation efficiency, and realizes the system prototype. Further, the application can be the integration of the simulation vector automatic generation tool and the simulation vulnerability mining tool, takes the simulation vector generation result as the input of the simulation, and is used for discovering the defects in the hardware design. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 is a flowchart of the method of the present application.
[0033] Figure 2 is a functional flowchart of the present application for obtaining the mapping relationship between the intermediate signal and the input signal in a specific application example.
[0034] Figure 3 is a schematic diagram of the present application for effect evaluation according to the simulation output in a specific application example.
[0035] Figure 4 is a schematic diagram of the present application for processing multiple assertions in a specific application example. DETAILED DESCRIPTION
[0036] The present application will be further described in detail below in conjunction with the accompanying drawings and specific examples.
[0037] As shown in Figures 1-3 , a simulation vector automatic generation method based on agent model for assertion coverage of the present application includes:
[0038] Lightweight simulation vector automatic generation, which is for the assertion statement in the System Verilog file in which the precondition only involves the module input;
[0039] Surrogate model generation, which is for the assertion in the System Verilog file in which the precondition is complex, to generate a surrogate model for easy processing;
[0040] Multiple assertion simulation vector automatic generation, which generates a simulation vector that activates multiple assertions at the same time.
[0041] In a specific application example, the assertions involved in the System Verilog are mainly divided into two categories:
[0042] (a) The assertion whose precondition only contains the module input signal;
[0043] (b) The assertion whose precondition contains the intermediate signal and the output signal in addition to the module input signal.
[0044] In a specific application example, the lightweight simulation vector automatic generation process is accompanied by the process of analysis and guidance for assertion coverage.
[0045] As a preferred embodiment, the analysis and guidance for assertion coverage in this example refers to: after each round of simulation vector generation, the coverage of the assertion is obtained according to the simulation results, thereby guiding the next round of simulation vector generation.
[0046] As a preferred embodiment, the preconditions in this example only involve the assertion of module input signals, and the lightweight simulation vector automatic generation mainly uses the existing random sampling tool.
[0047] In a specific application example, the existing random sampling tool processes a constraint file written using a constraint description standard (such as smtlib2) to generate values of variables satisfying the constraints mentioned in the constraint file, that is, the simulation vector.
[0048] In a specific application example, the generation of the surrogate model aims to transform the assertion involving intermediate signals into an assertion involving only input signals without completely expanding the circuit analysis, and mainly uses a machine learning tool.
[0049] In a specific application example, the machine learning tool mainly functions to automatically and quickly generate an assertion, that is, an approximate mapping relationship between input signals and intermediate signals, given a Verilog file.
[0050] In a specific application example, the generation of the surrogate model using the machine learning tool means that the mapping relationship between input signals and intermediate signals obtained by the machine learning tool is used to transform the assertion involving intermediate signals into an assertion involving only input signals, which is left for lightweight simulation vector generation.
[0051] In a specific application example, the multi-assertion simulation vector automatic generation aims to cover multiple assertions using as few simulation vectors as possible.
[0052] In a specific application example, the multi-assertion simulation vector automatic generation has the following process: analyzing the preconditions of the assertions, building the preconditions of the assertions into a tree structure, and finding the inclusion relationship between the trees.
[0053] As can be seen from the above, for a large circuit design, the present application uses a constraint solving technique based on random sampling to generate simulation vectors to cover most of the assertions. This preliminary plan is based on a random sampling method; it includes:
[0054] First, for the assertions involving only original inputs in the assertions, the preconditions of the assertions are directly sent to the sampler as constraints to sample, and simulation vectors that can activate the assertions are obtained.
[0055] Second, the basic information of the circuit, such as signal bit number, is sent to the sampler as constraints to sample, and basic random simulation vectors are obtained.
[0056] Finally, the simulation vectors are sent to the simulator for simulation, and the coverage of the assertions is observed.
[0057] In the specific use process, the coverage of the assertions referred to by the present application is divided into the following categories:
[0058] Overall coverage of each assertion: the ratio of the single-shot simulation vector activated assertion to all the activated assertions. Considering that the system of the present application is a coverage-guided regression system, investigating the coverage of each assertion can better guide the generation of the simulation vector of the next iteration of the constraint solving technique, and can determine whether the simulation vector generation can be terminated by observing the trend of the change of the assertion coverage.
[0059] Uniform coverage of single assertion: when an assertion is activated n times, the number of different combinations of signals involved in the assertion m / n. The present application considers generating as many simulation vectors as possible that can activate the assertion, and detecting whether the result of the assertion is true in the case of multiple activations of the single assertion, so as to more fully verify the functional model of the circuit.
[0060] Coverage of single assertion in a period of time: according to the generated simulation vector, the number of shots in which the assertion is activated m / n in n shots. In the present application, the mapping relationship between the intermediate signal and the input signal is obtained using the proxy model, and this relationship is an approximate relationship. Investigating the coverage of the single assertion in a period of time can evaluate the accuracy of this proxy model.
[0061] In specific applications, the present application obtains the mapping relationship between the intermediate signal and the input signal by means of machine learning technology. This mapping relationship may involve multiple cycles, or may only involve part of the information of the intermediate signal or the input signal.
[0062] In specific applications, the present application analyzes the description of the circuit by means of program slicing to find the input signal I (I1, I2,..., I n ) related to the intermediate signal Y (Y1, Y2,..., Y m ) involved in the assertion.
[0063] When using machine learning tools, the antecedent condition is limited in Y, and the consequent condition is limited in I. The antecedent condition is set to be a class conjunctive normal form (CNF, i.e. an expression connected by a conjunctive operator such as a∧b), which is mainly divided into single-shot assertions and cross-clock assertions. The cross-clock assertion needs to evaluate the accuracy of the mapping relationship through the coverage of the single assertion in a period of time defined in the previous step.
[0064] In addition, it should be noted that the processing time of the machine learning tool is also one of the evaluation criteria. For large designs, an upper limit of the processing time needs to be set to limit the processing time.
[0065] For the following example:
[0066] property p1;@posedge(clk) end property
[0067] property p2; @posedge(clk) end property
[0068] assert property(p1); assert property(p2);
[0069] The preconditions of the assertion are analyzed, the preconditions of the assertion are built into a tree structure, the containing relationship between the trees is found, and the above example is built into the tree structure as shown in Fig. 1. Figure 4 The p1 and p2 in Fig. 1 are:
[0070] For the properties as follows:
[0071] property p2'; @posedge(clk) end property
[0072] The tree diagram is built as shown in Fig. 2. Figure 4 The p2' in Fig. 2 is built, that is, the ∧ operation is built into parent-child nodes in the tree diagram, and the ∨ operation is built into sibling nodes in the tree diagram.
[0073] Then, the property tree is traversed, the containing relationship between the properties is found, and the containing relationship is used to prune the assertion to be processed.
[0074] The above is only a preferred embodiment of the present application, and the protection scope of the present application is not limited to the above embodiment. Any technical solution falling within the concept of the present application belongs to the protection scope of the present application. It should be noted that, for ordinary skilled in the art, some improvements and refinements without departing from the principle of the present application should be considered as the protection scope of the present application.
Claims
1. A method for automatically generating simulated vectors based on a surrogate model and oriented towards assertion coverage, characterized in that, include: Lightweight simulation vector automatic generation, targeting assertions in System Verilog files whose preconditions only involve module inputs; Proxy model generation: Generate proxy models for assertions with complex preconditions in System Verilog files; Multi-assertion simulation vectors are automatically generated, generating simulation vectors that simultaneously activate multiple assertions; Assertions involved in System Verilog files include: The preconditions only include assertions for the module's input signals; The preconditions include assertions for intermediate and output signals in addition to the module input signals; The generation of the proxy model involves transforming assertions involving intermediate signals into assertions involving only input signals, based on an incomplete circuit analysis. The proxy model is generated using machine learning tools, including: automatically and quickly generating assertions given a System Verilog file; that is, using the mapping relationship between the input signal and the intermediate signal obtained by the machine learning tools.
2. The method for automatically generating simulated vectors based on assertion coverage using a surrogate model according to claim 1, characterized in that, The process of automatically generating the lightweight simulation vector is accompanied by an analysis-guided process for assertion coverage.
3. The method for automatically generating simulated vectors based on assertion coverage using a surrogate model according to claim 2, characterized in that, The aforementioned analysis guidance on assertion coverage refers to obtaining the assertion coverage based on the simulation results after each round of simulated vector generation, and using this information to guide the next round of simulated vector generation.
4. The method for automatically generating simulated vectors based on assertion coverage using a surrogate model according to claim 1, characterized in that, The preconditions are generated using a random sampling tool, and the assertion statements only involve the module input signals.
5. The method for automatically generating simulated vectors based on assertion coverage using a surrogate model according to claim 4, characterized in that, The random sampling tool uses a constraint file written in the constraint description standard to generate values of variables that satisfy the constraints mentioned in the constraint file, i.e., the simulated vector.
6. The method for automatically generating analog vectors based on assertion coverage using a surrogate model according to claim 1, characterized in that, The machine learning tool generates a proxy model. By using the mapping relationship between the input signal and the intermediate signal obtained by the machine learning tool, assertions involving the intermediate signal are transformed into assertions involving only the input signal, which are then left to lightweight analog vector generation.
7. The method for automatically generating simulated vectors based on a surrogate model for assertion coverage according to any one of claims 1-5, characterized in that, The process of automatically generating multi-assertion simulation vectors includes: analyzing the preconditions of the assertions, building a tree structure from the preconditions of the assertions, and finding the inclusion relationships between the trees.