A circuit optimization method based on global information of the circuit

Abstract

The application discloses a circuit optimization method based on global information of a circuit, which comprises the following steps: utilizing equivalent saturation reasoning rewriting rules; converting a circuit intermediate format into corresponding equivalent graphs e-graphs; utilizing the equivalent saturation to apply rewriting rules to obtain all possible equivalent replacements; and searching for a target solution from all possible equivalent replacements. The application has the advantages of simple principle, simple operation, flexibility and universality.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of optimization of ultra-large-scale integrated circuits, and in particular to a circuit optimization method based on global circuit information. Background Art

[0002] As modern VLSI (Very Large Scale Integration) system designs become increasingly complex, circuit optimization becomes increasingly important. In recent years, the design of domain-specific languages ​​(DSLs) based on popular high-level programming languages ​​such as Scala and Python has become a trend. These DSLs draw heavily on compiler technology, incorporating intermediate formats similar to LLVM. However, circuit optimization based on these intermediate formats is still immature.

[0003] Existing circuit optimization methods primarily target complex computational problems, such as those encountered in digital signal processing (DSP). When performing circuit optimization, data flow calculations are first represented as Taylor expansion diagrams (TEDs). Circuit optimization is achieved through methods such as decomposition of algebraic expressions, elimination of common subexpressions, and replacement of expressions involving constant multiplication with addition and shift operations.

[0004] However, existing traditional methods still have some technical deficiencies:

[0005] 1. Traditional methods mainly focus on data flow calculations in combinational circuits and lack the means to uniformly optimize general circuits.

[0006] 2. Traditional methods perform well in local optimization of circuits, but they rarely change the architecture of a given circuit and cannot achieve global optimization results.

[0007] 3. Traditional methods cannot flexibly obtain different optimization results based on the optimization objectives (such as area, number of units, delay, etc.).

[0008] As can be seen from the above, the technical deficiencies summarized above are the shortcomings of circuit optimization. In design optimization methods based on global circuit information, optimization time directly affects the final optimization results. Similarly, optimization methods based on global circuit information inevitably incur overhead during optimization. Summary of the Invention

[0009] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides a circuit optimization method based on circuit global information that is simple in principle, easy to operate, flexible and universal.

[0010] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0011] A circuit optimization method based on circuit global information, comprising:

[0012] Rewrite rules using equivalence saturation reasoning;

[0013] Convert the intermediate format of the circuit into the corresponding equivalent graphs e-graphs;

[0014] Apply rewrite rules using equivalence saturation to obtain all possible equivalent replacements;

[0015] Search for the target solution among all possible equivalent substitutions.

[0016] As a further improvement to the method of the present invention: according to the syntax specification of the intermediate format, expressions are enumerated in the equivalence graph, rewriting rules are extracted from equivalent nodes, and the rewriting rules are simplified by using equivalent saturation.

[0017] As a further improvement of the method of the present invention: topological transformation is performed on the intermediate format of the circuit and then converted into corresponding equivalent graphs e-graphs.

[0018] As a further improvement to the method of the present invention, when applying the rewrite rule to the equivalence graph, new nodes and edges are added, but nothing is deleted.

[0019] As a further improvement to the method of the present invention: when applying rewriting rules to the equivalence graph, the reading and writing of the equivalence graph are separated, all matched replacements are saved in each iteration, and then these replacements are added to the equivalence graph and the next iteration is performed until the equivalence graph is saturated.

[0020] As a further improvement of the method of the present invention, e-nodes are created starting from the input in topological order, and connection relationships are established for subsequent e-nodes according to the properties of corresponding operators to generate the equivalent graphs e-graphs.

[0021] As a further improvement of the method of the present invention, starting from the root node of the equivalent graph to which the rewriting rules are applied to reach saturation or other constraints, a heuristic search for a target solution is performed from top to bottom.

[0022] As a further improvement of the method of the present invention, different heuristic functions can be designed for different objectives, thereby obtaining optimization results that meet the corresponding objectives.

[0023] As a further improvement to the method of the present invention: an equivalence graph is established for the topological transformation of the intermediate format of the circuit, wherein the root node of the equivalence graph is the circuit output and the leaf nodes are its predecessor nodes; rewriting rules are applied to add all possible equivalent replacements in the equivalence graph, and a data structure is created for the equivalent nodes, and these nodes are integrated into the data structure at the same time; finally, a heuristic function is used to search from top to bottom to obtain an optimization result that meets the target.

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] 1. The circuit optimization method based on global circuit information of the present invention has a simple principle, easy operation, and is flexible and universal. It can uniformly optimize the combinational logic and sequential logic, word-level signals and bit-level signals, data flow, and control flow of the circuit.

[0026] 2. The circuit optimization method based on global circuit information of the present invention utilizes the idea of ​​equivalent saturation pairs to retain information of all intermediate steps of design optimization so as to optimize the circuit based on global information, which is conducive to finding the best architecture for a given circuit.

[0027] 3. The circuit optimization method based on global circuit information of the present invention can design corresponding heuristic functions for searching according to different optimization objectives. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic flow diagram of the method of the present invention.

[0029] Figure 2 It is an exemplary schematic diagram of converting FIRRTL into e-graphs in a specific application example of the present invention.

[0030] Figure 3 It is a schematic diagram of the flow of reasoning and rewriting rules in a specific application example of the present invention.

[0031] Figure 4 This is an example schematic diagram of rewriting e-graphs using saturation equivalence in a specific application example of the present invention.

[0032] Figure 5 It is a schematic diagram of a FIRRTL example in a specific application example of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] The circuit intermediate format described in the present invention refers to an intermediate representation of a digital circuit, such as FIRRTL, which is designed as a platform for writing circuit-level conversions. Based on the intermediate format representation, the customization of RTL can be written as a function, and the customized function can be passed in as a parameter using the high-order function mechanism of the host language, and the customized action can be recursively applied to each part of the design. Since this customization is encapsulated in a function and can be used as a parameter of other functions, the customization is loosely coupled with the RTL design, which greatly improves the reusability and rapid changeability of the customization. This customization can also be replaced by design optimization, design simplification, area and power consumption estimation, mapping to FPGA or ASIC, and support for verification. FIRRTL is a very concise intermediate format, and its examples are as follows. Figure 5 shown.

[0035] The present invention utilizes the idea of ​​equivalent saturation and uses rewriting rules to add equivalent replacements to the equivalent graph corresponding to the circuit intermediate format until saturation, and then performs heuristic search according to the optimization goal.

[0036] like Figure 1 As shown, the circuit optimization method based on circuit global information of the present invention includes:

[0037] Rewrite rules using equivalence saturation reasoning;

[0038] Convert the intermediate format of the circuit into the corresponding equivalent graphs e-graphs;

[0039] Apply rewrite rules using equivalence saturation to obtain all possible equivalent replacements;

[0040] Search for the target solution from all possible equivalent replacements, and design corresponding heuristic functions for searching according to different optimization objectives.

[0041] In specific application examples, see Figure 2 ,The present invention converts the intermediate format into equivalent graphs e-graphs.

[0042] Furthermore, the present invention creates e-nodes starting from the input according to the topological order of the intermediate format, establishes connection relationships for subsequent e-nodes according to the properties of corresponding operators, and generates the equivalent graphs e-graphs.

[0043] In specific application examples, see Figure 3 , rewrite rules using equivalence saturation reasoning.

[0044] Furthermore, the present invention enumerates expressions in an equivalence graph according to the grammatical specification of the intermediate format, extracts rewriting rules from equivalent nodes, and simplifies the rewriting rules using equivalence saturation.

[0045] In specific application examples, see Figure 4, apply the rewrite rules using equivalence saturation to obtain all possible equivalent replacements.

[0046] Furthermore, when applying rewriting rules to the equivalence graph, the present invention separates the reading and writing of the equivalence graph, saves all matched replacements in each iteration, and then adds these replacements to the equivalence graph for the next iteration until the equivalence graph is saturated. The purpose is to minimize the number of times the equivalence graph is rebuilt and improve performance.

[0047] In specific application examples, corresponding heuristic functions can be designed for search based on the optimization objectives.

[0048] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A circuit optimization method based on circuit global information, characterized in that: include: Rewrite rules using equivalence saturation reasoning; Convert the intermediate format of the circuit into the corresponding equivalent graphs e-graphs; Apply rewrite rules using equivalence saturation to obtain all possible equivalent replacements; Search for the target solution among all possible equivalent substitutions.

2. The circuit optimization method based on circuit global information according to claim 1, characterized in that: According to the syntax specification of the intermediate format, expressions are enumerated in the equivalence graph, rewriting rules are extracted from equivalent nodes, and rewriting rules are simplified using equivalence saturation.

3. The circuit optimization method based on circuit global information according to claim 2, characterized in that: By performing topological transformation on the intermediate format of the circuit, it is then converted into the corresponding equivalent graphs e-graphs.

4. The circuit optimization method based on circuit global information according to claim 2, characterized in that: When applying rewrite rules to an equivalence graph, new nodes and edges are added but nothing is deleted.

5. The circuit optimization method based on circuit global information according to claim 4, characterized in that: When applying rewrite rules to the equivalence graph, the reading and writing of the equivalence graph are separated. All the matched replacements are saved in each iteration, and then these replacements are added to the equivalence graph for the next iteration until the equivalence graph is saturated.

6. The circuit optimization method based on circuit global information according to any one of claims 1 to 5, characterized in that: E-nodes are created starting from the input in topological order, and connection relationships are established for subsequent e-nodes according to the properties of corresponding operators to generate the equivalent graphs e-graphs.

7. The circuit optimization method based on circuit global information according to any one of claims 1 to 5, characterized in that: Starting from the root node of the equivalence graph where rewriting rules are applied to achieve saturation or other constraints, a heuristic search for the target solution is performed top-down.

8. The circuit optimization method based on circuit global information according to claim 6, characterized in that: Different heuristic functions can be designed for different objectives, and then optimization results that meet the corresponding objectives can be obtained.

9. The circuit optimization method based on circuit global information according to any one of claims 1 to 6, characterized in that: An equivalence graph is established for the topological transformation of the intermediate format of the circuit, wherein the root node of the equivalence graph is the circuit output and the leaf nodes are its predecessor nodes; rewriting rules are applied to add all possible equivalent replacements in the equivalence graph, and a data structure is created for the equivalent nodes, and these nodes are integrated into the data structure. Finally, a heuristic function is used to search from top to bottom to obtain an optimization result that meets the goal.

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