Method for designing a milling path on a PCB

Abstract

The application relates to the technical field of PCB production and processing, in particular to a method for designing a PCB milling path, which comprises the following steps: calculating a single-board area and a boundary area by using polygon Boolean operation and inclusion operation according to the drilling position and the plate frame position of a PCB; generating a PCB milling path; adjusting path coordinates according to the milling path and a shrinkage coefficient; reading a milling file, checking milling data, and manually fine-tuning the data; outputting the milling file and converting the file into a format that can be read by numerical control equipment. Compared with the prior art, the method for designing a PCB milling path solves the problems that, in the current PCB milling process, there is a manual cognitive bias when designing a milling path, which leads to low efficiency and quality and excessive human resources, and the method has the advantages of strong universality, the ability to quickly design a reasonable milling path and a tool changing path, the reasonable use of processing time, and the improvement of design efficiency, processing efficiency and quality.

Description

[Technical Field]

[0001] This invention relates to the field of PCB manufacturing technology, and in particular to a method based on PCB router path design. [Background Technology]

[0002] Before PCB routing, engineers need to design the routing path in the project file and address issues such as toolpath interference with the PCB board, tool processing efficiency optimization, toolpath interference with the positioning hole edges, and board expansion / contraction caused by manufacturing processes. Over extended production periods, human error is unavoidable, leading to dimensional deviations, reduced efficiency, and failure to meet delivery requirements during routing, thus impacting product quality and efficiency. To improve quality, stabilize product characteristics and functionality, and effectively control product scrap due to human error by innovating and improving PCB assembly dimensions, rationally handling toolpath interference with the PCB board, and optimizing tool selection, we need more sophisticated automated routing design software. This software allows computers to replace manual labor, rationally handle all human errors in the PCB routing process, accelerate design time, stabilize product quality, and improve efficiency. [Summary of the Invention]

[0003] To overcome the above problems, this invention proposes a method based on PCB router path design that can effectively solve the above problems.

[0004] The present invention provides a technical solution to the above-mentioned technical problems by providing a method for PCB router path design, comprising the following steps:

[0005] Step S1: Calculate the single-board area and boundary area using polygon Boolean operations and inclusion operations based on the drilling position and board frame position of the PCB board.

[0006] Step S2: PCB board router path generation;

[0007] Step S3: Adjust the path coordinates according to the gong belt path and expansion / contraction coefficient;

[0008] Step S4: Read the gong tape file, view the gong tape data, and perform manual data fine-tuning;

[0009] Step S5: Output the auger tape file and export it in a format that conforms to the reading format of CNC equipment.

[0010] Preferably, step S2 includes the following steps:

[0011] Step S21: Obtain a list of the total outline area, process edge area, stamp hole connection area, inner groove area and PCB single board area, back up the positioning holes, traverse all inner groove areas and process edge areas in the list, and merge intersecting inner groove areas and process edge areas.

[0012] Step S22: Calculate the actual cutting path to avoid overcutting and undercutting. Match the process edge regions according to the principle that the process edge regions are paired and equal in size.

[0013] Step S23: Merge the process edge region into the overall shape region, calculate the overall shape cutting path after merging the process edge region and the overall shape region, and perform supplementary cutting at the acute angle where the process edge region and the overall shape region intersect.

[0014] Step S24: The inner groove area is merged into the process edge area. The cutting path of the inner groove area is calculated. At the acute angle where the inner groove area and the process edge area intersect, the additional cutting is performed.

[0015] Step S25: Avoid positioning holes and calculate the routing path of the PCB board using a large, medium, and small router tool respectively.

[0016] Preferably, step S24 includes the following steps:

[0017] Step S241: Let the toolpath of the large gong tool be ToolPath1 and the toolpath of the small gong tool be ToolPath2, and calculate the toolpath RePairToolPaths of the small gong tool.

[0018] Step S242: The toolpath ToolPath1 of the large milling cutter is offset outward by a distance D1 to obtain the cutting path Path1 of the large milling cutter;

[0019] Step S243: The toolpath ToolPath2 of the small milling cutter is offset outward by a distance D2 to obtain the cutting path Path2 of the small milling cutter;

[0020] Step S244: Break Path2 into a new path Path3 with two points 0.1mm apart;

[0021] Step S245: Traverse and compare Path1 and Path3 to find the coordinate segments where Path1 and Path3 do not overlap.

[0022] Step S246: Calculate the area of ​​the polygon enclosed by the coordinate segments of Path1 and Path3 that do not overlap. If the area of ​​the polygon is greater than or equal to 0.5mm*0.5mm, then use the coordinate segments of Path3 that do not overlap with Path1 as the small-sized gong tool replacement path RePairToolPaths.

[0023] Step S247: Repeat steps S242-S246 to find all small-sized gong tool repair paths RePairToolPaths that meet the conditions, and merge them into a total repair path RePairToolPaths.

[0024] Preferably, step S1 includes the following steps:

[0025] Step S11: Perform a contact check on the border shape of the GKO file of the PCB board to ensure that the beginning and end are connected. If there are borders that do not touch at the beginning and end, perform straight line repair.

[0026] Step S12: Apply Boolean and inclusion operations to the GKO file of the PCB board whose frame shape is closed, and calculate the PCB board's outline area. If there are multiple outline areas in the calculation result, take the outline area with the largest area that includes other outline areas as the total outline area, and define the other areas as "areas to be analyzed".

[0027] Step S13: After determining the overall outline area, Boolean operations and inclusion operations are applied to the overall outline area to identify the process edge area, stamp hole connection area, inner groove area and PCB board area respectively.

[0028] Preferably, in step S11, the distance between the starting point and ending point of an element in the GKO file and the surrounding elements is calculated. If the distance is greater than the sum of the line widths or greater than 15mil, a straight line is used to repair the distance between the two points.

[0029] Preferably, in step S12, if there is a panel gap in the outline of the PCB board, the GKO file is expanded by 5mil, and Boolean operations and inclusion operations are reapplied. Step S12 is repeated to calculate the total outline area.

[0030] Preferably, in step S13, if the width or height of the area within the total outline area is less than 8mm, it is identified as a process edge area.

[0031] Preferably, in step S13, if a region within the total outline area contains more than three drill holes or the area of ​​drill holes exceeds 80% of the total area, it is identified as a PCB single-board region.

[0032] Preferably, in step S13, if any edge of the area within the total outline area passes through a series of holes, these holes are identified as stamp holes. If the area is not a PCB board area, it is identified as a stamp hole connection area.

[0033] Preferably, in step S13, the area enclosed by the overall shape region is analyzed by using elements that are in contact with the outline of the overall shape region. The area enclosed by the overall shape region is identified as the inner groove region, and the area not enclosed is the outer shape region.

[0034] Compared with existing technologies, the PCB router path design method of this invention can automatically output router files within 6 seconds (average 1 second), greatly accelerating production efficiency. The software supports file import, showing engineers the router path in the production process and assisting them in data review. After one year of field use, the automatic identification accuracy of the router area reached 95%. During the identification process, engineers can manually adjust blurred areas. In summary, compared with traditional manual router production, it can also output router paths in a shorter time. It solves the problems of low efficiency and quality caused by human cognitive bias in router path design during PCB router processing, as well as the excessive manpower required to handle single-board interference issues. It achieves strong versatility, can quickly design reasonable router paths and tool change paths, makes reasonable use of processing time, and improves design efficiency, processing efficiency, and quality. [Attached Image Description]

[0035] Figure 1 This is an overall flowchart of the method for PCB router path design based on the present invention;

[0036] Figure 2 This is a flowchart illustrating step S1 of the PCB router path design method of the present invention.

[0037] Figure 3 This is a flowchart of step S2 of the PCB router path design method of the present invention;

[0038] Figure 4 This is a flowchart of step S24 of the method for PCB router path design of the present invention;

[0039] Figure 5 This is a structural diagram showing the process edge region of the PCB single board located on the left and upper left corner relative to the PCB board in the PCB router path design method of the present invention.

[0040] Figure 6 This is a schematic diagram of the coordinate segments where Path1 and Path3 do not overlap in the PCB router path design method of the present invention.

Detailed Implementation Methods

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0042] It should be noted that in the embodiments of the present invention, all directional indications (such as up, down, left, right, front, back, etc.) are limited to relative positions on the specified view, rather than absolute positions.

[0043] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0044] Please see Figures 1 to 4 The method for PCB router path design of the present invention includes the following steps:

[0045] Step S1: Using the drilling positions and board frame positions of the PCB board, calculate the single board area and boundary area using polygon Boolean operations and inclusion operations.

[0046] In step S1, the single-board area is the area where cutting is not allowed, and the boundary area is the area where cutting is allowed.

[0047] Step S1 includes the following steps:

[0048] Step S11: Perform a contact check on the border shape of the GKO file of the PCB board to ensure that the beginning and end are connected. If there are borders that do not touch at the beginning and end, perform straight line repair to ensure that the border shape is closed.

[0049] Step S12: Apply Boolean and inclusion operations to the GKO file of the PCB board whose frame shape is closed, and calculate the PCB board's outline area. If there are multiple outline areas in the calculation result, take the outline area with the largest area that includes other outline areas as the total outline area, and define the other areas as "areas to be analyzed".

[0050] Step S13: After determining the overall outline area, Boolean operations and inclusion operations are applied to the overall outline area to identify the process edge area, stamp hole connection area, inner groove area and PCB board area respectively.

[0051] In step S11, the distance between the starting point and ending point of an element in the GKO file and the surrounding elements is calculated. If the distance is greater than the sum of the line widths or greater than 15mil, a straight line is used to repair the distance between the two points.

[0052] In step S12, if the calculated result of the PCB board's outline area does not contain a total outline area, it is assumed that there is a panel gap in the PCB board's border outline. The GKO file is then expanded by 5 mils to reduce interference. Boolean operations and inclusion operations are reapplied, and step S12 is repeated to calculate the total outline area. This process continues until the GKO file has more than 12 mils of elements and still cannot find a total outline area. If the calculation result contains multiple "areas to be analyzed," for example, "area to be analyzed" B contains "area to be analyzed" A, then "area to be analyzed" A is converted into an outline area. This process is recursively repeated until there are no errors in the outline area.

[0053] In step S13, if the width or height of the area within the total outline region is less than 8mm, it is identified as a process edge region; if the area within the total outline region contains more than 3 drill holes or the area of ​​drill holes exceeds 80% of the area, it is identified as a PCB board region; if any edge of the area within the total outline region passes through continuous holes, these holes are determined to be stamp holes, and if the area is not a PCB board region, it is identified as a stamp hole connection region; using elements that are in contact with the outline of the total outline region, the area enclosed by the total outline region is analyzed for inclusion, and the area included by the area is identified as an inner groove region, while the area not included is an outline region.

[0054] Step S2: PCB board router path generation.

[0055] Step S2 includes the following steps:

[0056] Step S21: Obtain a list of the total outline area, process edge area, stamp hole connection area, inner groove area and PCB single board area, and back up the positioning holes. Traverse all inner groove areas and process edge areas in the list, and merge any that intersect.

[0057] Step S22: Calculate the actual cutting path to avoid overcutting and undercutting. Match the process edge regions according to the principle that the process edge regions are paired and equal in size.

[0058] Step S23: Merge the process edge area into the overall shape area, calculate the overall shape cutting path after merging the process edge area and the overall shape area, and perform supplementary cutting at the acute angle where the process edge area and the overall shape area intersect to ensure that the single board cutting error is within the allowable range.

[0059] Step S24: The inner groove area is merged into the process edge area. The cutting path of the inner groove area is calculated. At the acute angle where the inner groove area and the process edge area intersect, additional cutting is performed to ensure that the single board cutting error is within the allowable range.

[0060] Step S25: Avoid positioning holes. Calculate the routing path of the PCB board using a large, medium, and small router tool, respectively. The large, medium, and small router tools can be referred to as large, medium, and small tools, respectively.

[0061] In step S23, within the process edge area, when a point of the border path or PCB path falls on the process edge path, the path can be corrected. The correction direction for cutting relative to the border path or PCB path in each direction is detailed in the table below:

[0062] The process edge area relative to the PCB board position X-cutting direction Y-cutting direction The process edge area is on the left, in the lower left corner. (-1，0) (-1，0) The process edge area is on the left, in the upper left corner. (-1，0) (1，0) The process edge area is on the right, in the lower right corner. (1，0) (-1，0) The process edge area is on the right, in the upper right corner. (1，0) (1，0) The process edge area is at the top, in the upper left corner. (-1，0) (1，0) The process edge area is at the top, in the upper right corner. (1，0) (1，0) The process edge area is at the bottom, in the lower left corner. (-1，0) (-1，0) The process edge area is at the bottom, in the lower right corner. (1，0) (-1，0)

[0063] Please see Figure 5 Taking the process edge at the top left corner as an example, the default direction is horizontal to the right as the positive X direction and vertical upward as the positive Y direction: Let the diameter of the large router be D, and the intersection of the PCB single board path and the process edge path be P1. Offset by a distance D in the opposite direction of the X cutting direction, i.e., the (1, 0) direction, to obtain P2 (i.e., |P1P2|=D). Then, offset by a distance D in the Y cutting direction, i.e., (1, 0), to obtain M1. Based on the X cutting direction (-1, 0) of M1, intersect the process edge contour at point M2, resulting in the region P1P2M1M2P3. Delete the path in this region. Point P1 connects to other paths of the process edge through points P2, M1, and M2. By traversing the process edges in each direction as described above, the process edge repair is completed.

[0064] In step S24, when encountering a very small inner groove area, or where there are areas in the inner groove area that a large-diameter milling cutter cannot pass through, it is necessary to switch to a smaller-diameter milling cutter for repair milling. Let the radius of the large-diameter milling cutter be D1 and the radius of the small-diameter milling cutter be D2. The steps for repair milling using a small-diameter milling cutter are as follows:

[0065] Step S241: Let the toolpath of the large gong tool be ToolPath1 and the toolpath of the small gong tool be ToolPath2, and calculate the toolpath RePairToolPaths of the small gong tool.

[0066] Step S242: The toolpath ToolPath1 of the large milling cutter is offset outward by a distance D1 to obtain the cutting path Path1 of the large milling cutter;

[0067] Step S243: The toolpath ToolPath2 of the small milling cutter is offset outward by a distance D2 to obtain the cutting path Path2 of the small milling cutter;

[0068] Step S244: Break Path2 into a new path Path3 with two points 0.1mm apart;

[0069] Step S245: Traverse and compare Path1 and Path3 to find the coordinate segments where Path1 and Path3 do not overlap; for example... Figure 6 As shown, the coordinates between the indices i1 and i2 of Path1 do not coincide with the coordinates between the indices j1 and j2 of Path3 (i.e., |PaPx|=0, and |PbPy|=0, and the distances between the coordinates of the rest (Pa~Pb) and the coordinates of (Px~Py) are not equal to 0), denoted as Path1[i1, i2], Path3[j1, j2];

[0070] Step S246: Calculate the area of ​​the polygon enclosed by the non-overlapping coordinate segments of Path1 and Path3, that is, calculate the area of ​​the polygon enclosed by Path1[i1, i2] and Path3[j1, j2]. If the polygon area is less than 0.5mm*0.5mm, it is ignored. If the polygon area is greater than or equal to 0.5mm*0.5mm, the non-overlapping coordinate segments of Path3 are used as the small-sized gong tool replacement path RePairToolPaths, that is, Path3[j1, j2] is used as the small-sized gong tool replacement path RePairToolPaths.

[0071] Step S247: Repeat steps S242-S246 to find all small-sized gong tool repair paths RePairToolPaths that meet the conditions, and merge them into a total repair path RePairToolPaths.

[0072] In step S25, if the small-sized milling cutter cannot cut completely, a milling tape trajectory cannot be generated (which is practically not allowed); if the large-sized milling cutter can cut completely, a milling tape trajectory is generated directly; if the large-sized milling cutter cannot cut completely, a medium-sized milling cutter is used to calculate whether it can cut completely; if the medium-sized milling cutter can cut completely, a cutting trajectory consisting of the large-sized milling cutter trajectory and the medium-sized milling cutter repair trajectory is used; if the medium-sized milling cutter cannot cut completely, a cutting trajectory consisting of the medium-sized milling cutter trajectory and the small-sized milling cutter repair trajectory is used.

[0073] Step S3: Adjust the path coordinates according to the belt path and expansion / contraction coefficient to meet production requirements.

[0074] Step S4: Read the gong tape file, view the gong tape data, and perform manual data fine-tuning.

[0075] Step S5: Output the auger tape file and export it in a format that conforms to the reading format of CNC equipment.

[0076] Compared with existing technologies, the PCB router path design method of this invention can automatically output router files within 6 seconds (average 1 second), greatly accelerating production efficiency. The software supports file import, showing engineers the router path in the production process and assisting them in data review. After one year of field use, the automatic identification accuracy of the router area reached 95%. During the identification process, engineers can manually adjust blurred areas. In summary, compared with traditional manual router production, it can also output router paths in a shorter time. It solves the problems of low efficiency and quality caused by human cognitive bias in router path design during PCB router processing, as well as the excessive manpower required to handle single-board interference issues. It achieves strong versatility, can quickly design reasonable router paths and tool change paths, makes reasonable use of processing time, and improves design efficiency, processing efficiency, and quality.

[0077] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any modifications, equivalent substitutions and improvements made within the concept of the present invention should be included within the patent protection scope of the present invention.

Claims

1. A method based on PCB router path design, characterized in that, Includes the following steps: Step S1: Calculate the single-board area and boundary area using polygon Boolean operations and inclusion operations based on the drilling position and board frame position of the PCB board. Step S2: PCB board router path generation; Step S2 includes the following steps: Step S21: Obtain a list of the total outline area, process edge area, stamp hole connection area, inner groove area and PCB single board area, back up the positioning holes, traverse all inner groove areas and process edge areas in the list, and merge intersecting inner groove areas and process edge areas. Step S22: Calculate the actual cutting path to avoid overcutting and undercutting. Match the process edge regions according to the principle that the process edge regions are paired and equal in size. Step S23: Merge the process edge region into the overall shape region, calculate the overall shape cutting path after merging the process edge region and the overall shape region, and perform supplementary cutting at the acute angle where the process edge region and the overall shape region intersect. Step S24: The inner groove area is merged into the process edge area. The cutting path of the inner groove area is calculated. At the acute angle where the inner groove area and the process edge area intersect, the additional cutting is performed. Step S25: Avoid positioning holes and calculate the routing path of the PCB board using a large, medium, and small router tool respectively. Step S3: Adjust the path coordinates according to the gong belt path and expansion / contraction coefficient; Step S4: Read the gong tape file, view the gong tape data, and perform manual data fine-tuning; Step S5: Output the auger tape file and export it in a format that conforms to the reading format of CNC equipment.

2. The method for PCB router path design as described in claim 1, characterized in that, Step S24 includes the following steps: Step S241: Let the toolpath of the large gong tool be ToolPath1 and the toolpath of the small gong tool be ToolPath2, and calculate the toolpath RePairToolPaths of the small gong tool. Step S242: The toolpath ToolPath1 of the large milling cutter is offset outward by a distance D1 to obtain the cutting path Path1 of the large milling cutter; Step S243: The toolpath ToolPath2 of the small milling cutter is offset outward by a distance D2 to obtain the cutting path Path2 of the small milling cutter; Step S244: Break Path2 into a new path Path3 with two points 0.1mm apart; Step S245: Traverse and compare Path1 and Path3 to find the coordinate segments where Path1 and Path3 do not overlap. Step S246: Calculate the area of ​​the polygon enclosed by the coordinate segments of Path1 and Path3 that do not overlap. If the area of ​​the polygon is greater than or equal to 0.5mm*0.5mm, then use the coordinate segments of Path3 that do not overlap with Path1 as the small-sized gong tool replacement path RePairToolPaths. Step S247: Repeat steps S242-S246 to find all small-sized gong tool repair paths RePairToolPaths that meet the conditions, and merge them into a total repair path RePairToolPaths.

3. The method for PCB router path design as described in claim 1, characterized in that, Step S1 includes the following steps: Step S11: Perform a contact check on the border shape of the GKO file of the PCB board to ensure that the beginning and end are connected. If there are borders that do not touch at the beginning and end, perform straight line repair. Step S12: Apply Boolean and inclusion operations to the GKO file of the PCB board whose frame shape is closed, and calculate the PCB board's outline area. If there are multiple outline areas in the calculation result, take the outline area with the largest area that includes other outline areas as the total outline area, and define the other areas as "areas to be analyzed". Step S13: After determining the overall outline area, Boolean operations and inclusion operations are applied to the overall outline area to identify the process edge area, stamp hole connection area, inner groove area and PCB board area respectively.

4. The method for PCB router path design as described in claim 3, characterized in that, In step S11, the distance between the starting point and ending point of an element in the GKO file and the surrounding elements is calculated. If the distance is greater than the sum of the line widths or greater than 15mil, a straight line is used to repair the distance between the two points.

5. The method for PCB router path design as described in claim 3, characterized in that, In step S12, since there are gaps in the outline of the PCB board, the GKO file is expanded by 5mil, and Boolean operations and inclusion operations are applied again. Step S12 is repeated to calculate the total outline area.

6. The method for PCB router path design as described in claim 3, characterized in that, In step S13, if the width or height of the area within the total outline area is less than 8mm, it is identified as a process edge area.

7. The method for PCB router path design as described in claim 3, characterized in that, In step S13, if a region within the total outline area contains more than 3 holes or the area of ​​the drill holes exceeds 80% of the total area, it is identified as a PCB board region.

8. The method for PCB router path design as described in claim 7, characterized in that, In step S13, if any edge of the area within the overall outline region passes through a series of holes, these holes are identified as stamp holes. If the area is not a PCB board area, it is identified as a stamp hole connection area.

9. The method for PCB router path design as described in claim 3, characterized in that, In step S13, the area enclosed by the overall shape region is analyzed by using elements that are in contact with the outline of the overall shape region. Areas that are enclosed by the overall shape region are identified as inner groove regions, while those that are not enclosed are outer shape regions.

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