Method for optimizing gate size process to balance semiconductor device performance

Abstract

The application discloses a process optimization method for balancing the gate size of a semiconductor device, which can realize the reduction of the gate size of a transistor and meet the adjustment requirement of the performance balance of the transistor. A plurality of semiconductor devices are distributed on a wafer, and each semiconductor device comprises a gate. The process optimization method comprises the following steps: dividing the gate into an adjustment area and a non-adjustment area, covering the non-adjustment area with a first photomask, adjusting the gate size of the adjustment area once, measuring the gate size after the first adjustment to obtain a first gate size, measuring the electrical performance parameter of the semiconductor device after the first adjustment, judging whether the value of the electrical performance parameter is within a preset threshold range, if yes, no further adjustment is needed, and if no, the step S7 is entered, the preset threshold range is determined according to the balance of at least two same or associated semiconductor devices, and the gate size of the semiconductor device that does not meet the requirement is adjusted at least once.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a method for optimizing gate size processes to balance the performance of semiconductor devices. Background Technology

[0002] As the integration level of integrated circuits increases, the device density and interconnection density in circuits continue to increase, and the feature size of semiconductor devices continues to decrease. Among the feature sizes, the gate length is one of the most critical parameters affecting the electrical performance of semiconductor devices, and its size reduction is also one of the difficulties in semiconductor manufacturing processes.

[0003] With the continuous development of semiconductor technology and the evolution of process nodes, for processes with gate lengths below 14nm, methods such as double patterning and trimming processes are required to further reduce the gate length of devices. However, these methods can only achieve trimming by partially defining the gate length, resulting in limited flexibility. Partially defining the gate length involves pre-setting the gate trimming dimensions in the layout and using a photomask with the pre-defined dimensions to perform photolithography etching on the gate length, obtaining a reduced gate length. However, during testing and production, there is often an imbalance in the electrical performance of two or more transistors. This imbalance refers to unequal conduction speeds or voltage differences between identical or related transistors in a chip or integrated circuit, affecting the overall stability of the chip or integrated circuit.

[0004] Currently, there is a lack of technology for balancing the electrical performance of transistors. Chips or integrated circuits made from transistors with poor balance have increased defect rates. Therefore, inventing a method to effectively reduce the gate size, meet the device performance adjustment requirements while reducing the gate length, and improve the performance balance of semiconductor devices in chips or integrated circuits has become an urgent problem to be solved by those in the field. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a gate size process optimization method for balancing the performance of semiconductor devices, which can reduce the gate size of transistors and meet the adjustment requirements for balancing transistor performance.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A gate size process optimization method for balancing the performance of semiconductor devices is used to adjust the gate size of semiconductor devices on a wafer, wherein a plurality of semiconductor devices are distributed on the wafer, and each semiconductor device includes a gate. The method is characterized in that the gate size optimization process steps include: S1, dividing the gate: dividing the gate into an adjustment region and a non-adjustment region;

[0008] S2. Cover the non-adjustment area with the first photomask;

[0009] S3. Adjust the gate size of the adjustment region once;

[0010] S4. Measure the gate size after the first adjustment to obtain the first gate size;

[0011] S5. Measure and obtain the electrical performance parameters of the semiconductor device after one adjustment;

[0012] S6. Determine whether the value of the electrical performance parameter is within the preset threshold range. If yes, it indicates that the electrical performance of the semiconductor device after one adjustment meets the requirements and no further adjustment is needed. If no, proceed to step S7. The preset threshold range is determined based on the balance of at least two identical or related semiconductor devices.

[0013] S7. Perform at least one selective adjustment on the gate size of the non-compliant semiconductor device until the value of the electrical performance parameter of the semiconductor device falls within the preset threshold range.

[0014] Its further feature is that,

[0015] The gate dimensions include the gate length;

[0016] Furthermore, in step S3, the first adjustment refers to a reduction in the gate length of the semiconductor device.

[0017] Furthermore, in step S5, the electrical performance includes the turn-on speed of the semiconductor device and the voltage difference of the associated semiconductor device, and the preset threshold range includes: a turn-on speed threshold range and a voltage difference threshold range.

[0018] Furthermore, in step S6, the specific steps for determining whether the electrical performance meets the preset threshold range include: S61, comparing the conduction speed with the conduction speed threshold range, and comparing the voltage difference with the voltage difference threshold range;

[0019] S62. If the conduction speed exceeds the conduction speed threshold range and / or the voltage difference exceeds the voltage difference threshold range, it indicates that the electrical performance does not meet the requirements, and proceed to step S7. Otherwise, it indicates that the electrical performance of the semiconductor device after one reduction meets the requirements and no selective adjustment is required.

[0020] Further, in step S7, the step of selectively adjusting includes: S71, selecting the gate region in the adjustment region that does not meet the electrical performance requirement as a secondary adjustment region, and the rest as a non-secondary adjustment region;

[0021] S72, covering the non-secondary adjustment region with a second mask;

[0022] S73, performing secondary reduction on the gate size of the secondary adjustment region;

[0023] Further, in step S3, the primary reduction refers to etching the gate of the adjustment region by using a photolithography process, to adjust the gate length from width a to width b, and width b is less than width a;

[0024] Further, the difference between width a and width b is less than or equal to 5nm;

[0025] Further, in step S73, the secondary reduction refers to etching the gate of the secondary adjustment region by using a photolithography process, to adjust the gate length from width b to width c, and width c is less than width b;

[0026] Further, the difference between width b and width c is less than or equal to 5nm;

[0027] Further, it further includes step S8, removing the first mask and the second mask.

[0028] A method for balancing the performance of semiconductor devices, applied in chip manufacturing or integrated circuit manufacturing, characterized in that the gate size of the semiconductor devices in the chip or integrated circuit is adjusted by using the above-mentioned gate size optimization method.

[0029] Further characterized in that,

[0030] The semiconductor devices include PMOS tubes and / or NMOS tubes.

[0031] The above-mentioned method of the present application can achieve the following beneficial effects: in the gate size process optimization method, after the gate size is adjusted once, the gate size of the semiconductor device that does not meet the requirements is selectively adjusted according to the electrical performance detection result of the semiconductor device, until the electrical performance of the semiconductor device meets the preset threshold range, and the preset threshold range is determined according to the balance of at least two same or associated semiconductor devices. Therefore, when the value of the electrical performance parameter of the semiconductor device after selective adjustment is within the preset threshold range, it indicates that the process parameter, i.e., the gate size, of the semiconductor device meets the requirement of the balance of the semiconductor device performance, thereby realizing the optimization of the gate size of the semiconductor device. The process optimization method realizes the reduction of the gate size of the transistor, and meets the adjustment requirement of the balance of the transistor performance, thereby ensuring the working stability of the entire chip or integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 The front view structural schematic diagram of the semiconductor device in the chip or integrated circuit before and after one-time reduction in the prior art;

[0033] Figure 2 The front view structural schematic diagram after the first mask coverage is realized in step S2 of the method of the present application;

[0034] Figure 3 The front view structural schematic diagram after the gate size is reduced twice in step S73 of the method of the present application;

[0035] Figure 4 The front view structural schematic diagram after the gate size is reduced twice in step S7 of the method of the present application and the second mask is removed in step S8;

[0036] Figure 5 The process flow chart of the method of the present application. DETAILED DESCRIPTION

[0037] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be noted that the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusion, for example, a process, method, device, product or equipment that includes a series of steps or units does not have to be limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0038] Figure 1The present application provides a structure diagram of a semiconductor device in a chip or integrated circuit after a first reduction of the gate length of the semiconductor device by using an existing gate size optimization method, which can only reduce the gate length according to the designed rules, and meets the requirement of reducing the gate length, but in the process of testing and actual production, the semiconductor device obtained by using the designed rules has a balance problem, the reduction of the gate length can meet the requirement of high integration of the integrated circuit, but also causes the leakage current, which causes the difference between the semiconductor devices with the same electrical performance, or the voltage difference between the associated semiconductor devices exceeds the preset threshold range, which reduces the balance of the same or associated semiconductor devices, and even affects the stability of the whole chip or integrated circuit.

[0039] In view of the problem that the reduction of the gate size in the prior art affects the balance of the electrical performance of the same or associated semiconductor devices, and reduces the stability of the whole chip or integrated circuit, the following provides a specific embodiment of a gate size process optimization method capable of balancing the performance of semiconductor devices.

[0040] A gate size process optimization method for balancing the performance of semiconductor devices, which is used for adjusting the gate size of a semiconductor device on a wafer 1, and the wafer is distributed with a plurality of semiconductor devices, and each semiconductor device comprises a gate 2. In this embodiment, the gate size mainly refers to the gate length.

[0041] The specific process steps of the gate size optimization include: S1, dividing the gate 2: dividing the gate into an adjustment area 3 and a non-adjustment area 4, wherein the adjustment area 3 refers to the area in which the gate length of the semiconductor device in the chip or integrated circuit needs to be reduced, and the non-adjustment area 4 refers to the area in which the gate length does not need to be reduced.

[0042] S2, covering the non-adjustment area 4 with a first photomask 30, as shown in Figure 1 ;

[0043] S3, adjusting the gate size of the adjustment area 3 once, that is, reducing the gate length of the semiconductor device once, specifically, etching the gate 2 of the adjustment area 3 by using a photolithography process, and adjusting the gate length from a width a to a width b, b is less than a, as shown in Figure 1 , in this embodiment, the width a minus the width b is less than or equal to 5nm;

[0044] S4, measuring the gate size after the first reduction by using an optical instrument (such as CDSEM, also known as critical dimension scanning electron microscope), to obtain a first gate size, which is the width b; and removing the first photomask after the first reduction. The critical dimension scanning electron microscope can accurately measure the gate length.

[0045] S5, electrically test the semiconductor device, measure the electrical performance parameters of the semiconductor device after the first adjustment. The electrical performance parameters include the turn-on speed and voltage of the semiconductor device. The voltage difference of the associated semiconductor device, i.e. the voltage difference value of the associated semiconductor device, is determined. The preset threshold range includes a turn-on speed threshold range and a voltage difference threshold range.

[0046] S6, determine whether the value of the electrical performance parameter falls within the preset threshold range. If yes, it indicates that the electrical performance of the semiconductor device after the first adjustment meets the requirements and no further adjustment is needed. If not, go to step S7. The preset threshold range is determined according to the balance of at least two identical or associated semiconductor devices.

[0047] The specific steps of determining whether the electrical performance meets the preset threshold range include: S61, compare the turn-on speed with the turn-on speed threshold range and compare the voltage difference with the voltage difference threshold range, i.e. determine whether the measured turn-on speed is within the turn-on speed threshold range and whether the voltage difference of the associated semiconductor device is within the voltage difference threshold range;

[0048] S62, if the turn-on speed exceeds the turn-on speed threshold range and / or the voltage difference exceeds the voltage difference threshold range, it indicates that the electrical performance does not meet the requirements and go to step S7. Otherwise, it indicates that the electrical performance of the semiconductor device after the first adjustment meets the requirements and no selective adjustment is needed.

[0049] S7, selectively adjust the gate size of the semiconductor device that does not meet the requirements at least once until the value of the electrical performance parameter of the semiconductor device falls within the preset threshold range.

[0050] In this step S7, the selective adjustment includes: S71, select the gate region in the adjustment region that does not meet the electrical performance requirements as the secondary adjustment region 5 and the rest as the non-secondary adjustment region 6.

[0051] S72, cover the non-secondary adjustment region with the second mask 50, see Figure 2 ;

[0052] S73, secondarily reduce the gate size of the secondary adjustment region 5. The secondary reduction refers to etching the gate of the secondary adjustment region by using the photolithography process to adjust the gate length from the width b to the width c. The width c is smaller than the width b, see Figure 3 In this embodiment, the width c minus the width b is less than or equal to 5 nm.

[0053] In actual manufacturing or debugging process, if the electrical performance of the semiconductor device after one selective adjustment does not meet the requirements, i.e., the gate size still does not meet the requirement of the electrical performance balance, then the steps S4, S5, S6 and S7 are cyclically executed until the value of the electrical performance parameter of the semiconductor device falls within the preset threshold range.

[0054] The cyclic steps S4, S5, S6 and S7 mean that the gate size and the electrical performance parameter of the semiconductor device after the second reduction are measured and obtained, it is judged whether the value of the electrical performance parameter meets the requirement of the preset threshold range, if not, a third adjustment is performed, and the cycle is sequentially repeated until the gate size meets the requirement of the electrical performance balance.

[0055] The process method further comprises a step S8 of removing the second mask. In the steps S4 and S8, the first mask and the second mask comprise photoresist and anti-reflection layer distributed in sequence from top to bottom, the semiconductor device after the first reduction and the semiconductor device after the second reduction are respectively placed in a photoresist removing machine to remove the photoresist, and then the anti-reflection layer is cleaned by using a wet cleaning method to obtain the semiconductor device after the second reduction of the gate length.

[0056] In actual testing and production process, the above gate size process optimization method is applied to the performance balance of the semiconductor device, the semiconductor device arranged in the chip or integrated circuit comprises PMOS tubes and NMOS tubes, after the gate size of the same or associated PMOS tubes and NMOS tubes in the same chip or integrated circuit is selectively adjusted by using the method, the value of the electrical performance parameter of the associated semiconductor device can fall within the preset threshold range, thereby realizing the balanced adjustment of the semiconductor device in the chip or integrated circuit. After the gate size of the PMOS tubes and NMOS tubes in the same wafer is balancedly adjusted by using the method, i.e., the gate size is improved according to the balance, the overall conduction speed of the PMOS tubes and NMOS tubes in the wafer can be increased by 8% to 15%, the threshold voltage of the PMOS tubes and NMOS tubes can be reduced by 10%, the fast conduction requirement of the PMOS tubes and NMOS tubes is met, and after the gate size of the PMOS tubes and NMOS tubes in the same wafer is balancedly adjusted, the working stability of the entire chip or integrated circuit is ensured.

[0057] The above is only the preferred embodiment of the present application, and the present application is not limited to the above embodiment. It can be understood that other improvements and changes directly derived or thought by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A method for optimizing gate size process to balance the performance of semiconductor devices, used to adjust the gate size of semiconductor devices on a wafer, wherein a plurality of semiconductor devices are distributed on the wafer, and each semiconductor device includes a gate, characterized in that, The process steps for optimizing the gate size include: S1, dividing the gate: dividing the gate into an adjustment region and a non-adjustment region; S2. Cover the non-adjustment area with the first photomask; S3. Adjust the gate size of the adjustment region once; the gate size includes the gate length; the adjustment once refers to reducing the gate length of the semiconductor device once; the reduction once refers to etching the gate of the adjustment region using a photolithography process to adjust the gate length from width a to width b, where width b is less than width a. S4. Measure the gate size after the first adjustment to obtain the first gate size; S5. Measure and obtain the electrical performance parameters of the semiconductor device after one adjustment; S6. Determine whether the value of the electrical performance parameter is within the preset threshold range. If yes, it indicates that the electrical performance of the semiconductor device after one adjustment meets the requirements and no further adjustment is needed. If no, proceed to step S7. The preset threshold range is determined based on the balance of at least two identical or related semiconductor devices. S7. Perform at least one selective adjustment on the gate size of the non-compliant semiconductor device until the value of the electrical performance parameter of the semiconductor device falls within the preset threshold range; In step S5, the electrical performance parameters include the conduction speed of the semiconductor device and the voltage difference of the associated semiconductor device. The preset threshold range includes: conduction speed threshold range and voltage difference threshold range. In step S6, the specific steps for determining whether the values ​​of electrical performance parameters meet the preset threshold range include: S61, comparing the conduction speed with the conduction speed threshold range, and comparing the voltage difference with the voltage difference threshold range; S62. If the conduction speed exceeds the conduction speed threshold range and / or the voltage difference exceeds the voltage difference threshold range, it indicates that the electrical performance does not meet the requirements, and proceed to step S7. Otherwise, it indicates that the electrical performance of the semiconductor device after one reduction meets the requirements and no selective adjustment is required. In step S7, the selective adjustment step includes: S71, selecting the gate region in the adjustment region that does not meet the electrical performance requirements as the secondary adjustment region, and the rest as the non-secondary adjustment region; S72. Cover the non-secondary adjustment area with a second photomask; S73. The gate size of the secondary adjustment region is reduced a second time. The secondary reduction refers to etching the gate of the secondary adjustment region using a photolithography process to adjust the gate length from width b to width c, where width c is less than width b.

2. The gate size process optimization method for balancing semiconductor device performance according to claim 1, characterized in that, The difference between width a and width b is less than or equal to 5 nm; the difference between width b and width c is less than or equal to 5 nm.

3. The gate size process optimization method for balancing semiconductor device performance according to claim 2, characterized in that, It also includes step S8, which removes the first photomask and the second photomask.

4. The gate size process optimization method for balancing semiconductor device performance according to claim 3, characterized in that, The semiconductor device includes a PMOS transistor and / or an NMOS transistor.

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