Semiconductor memory device and operating method thereof

Abstract

A semiconductor storage device and an operation method capable of inhibiting misoperation and performing safe operation are provided. A flash memory of the present invention includes a controller that controls operation based on a code read from a ROM. An operation method of the present invention includes detecting whether the code read from the ROM has an error by a CRC processing section, determining whether to shift to a safe mode when the code is detected to have an error, and detecting and correcting an error of the code by an ECC processing section after shifting to the safe mode.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor storage device, and particularly to a semiconductor storage device such as a flash memory that controls operation based on a code read from a read only memory (ROM) and an operation method thereof, and a central processing unit (CPU) or a microcontroller. BACKGROUND

[0002] In a NAND type flash memory or the like, at the time of power-on, setting information related to operation specifications is loaded from a fuse cell into a register, and operation voltages and the like for reading, programming, erasing, and the like are adjusted based on the setting information. For example, in the nonvolatile memory of U.S. Patent No. 7,433,247, a power-on operation is disclosed in which it is determined whether data read from a pre-check fuse cell is identical to pre-check data, setting information read from a main fuse cell is stored in a nonvolatile memory area, it is determined whether data read from a post-check fuse cell is identical to post-check data, and in the case where the pre-check and post-check are identical, the reading of the setting information is ended.

[0003] In general, in a NAND type flash memory, a CPU controls various operation programs by reading a code stored in a ROM. However, if a power supply voltage temporarily drops due to noise or peak current, or the ROM itself develops a defect or a failure due to stress caused by repeated reading, an error can sometimes occur in the reading of the ROM. It is assumed that if a reading error of the ROM occurs, that is, if the read code has an error, an operation failure of the chip (for example, a busy stack, that is, a busy state that does not return to a ready state) or a malfunction (data is erroneously programmed to a cell of an erroneous address of a fuse cell or the like, or data of a cell of an erroneous address of a fuse cell or the like is erased) occurs.

[0004] To solve the reading error of the ROM, a cyclic redundancy check (CRC) is proposed in the related art. The CRC takes a remainder obtained by dividing information from a transmission side by a predetermined generating polynomial as check data (Parity bit), and outputs the information from the transmission side with the check data as a code word. At a reception side, the code word is divided by the same generating polynomial to obtain a remainder, and by comparing and collating the remainder obtained at the reception side with the check data, it is possible to detect whether the received data has an error.

[0005] Figure 1is an operation flow of a power-on procedure of a flash memory using CRC. When power is turned on, a CPU reads a code from a ROM (S10), and detects whether or not the code has an error based on CRC (S20). If no error is detected (S30), setting information is read from a fuse cell (S40), and the read setting information is loaded into a register (S50). In the case where an error is detected, the reading of the ROM code is repeated. In this case, the number of retries of the reading of the ROM code is held (S60), and if the number of retries is equal to or less than a prescribed value N, the operation environment is waited for improvement (S70), and the reading of the ROM code is repeated (S10). In the case where the number of retries exceeds the prescribed value N, the power-on procedure ends in failure.

[0006] Such a check of CRC can detect the occurrence of a certain accidental error and notify thereof, but it is not possible to prevent various operation malfunctions or misoperations thereby. In addition, in the analysis of malfunctions of a flash memory or the like, it is difficult to accurately determine the cause of the error only by the check of CRC. SUMMARY

[0007] The present application solves such a conventional problem, and aims to provide a semiconductor storage device and an operation method capable of suppressing misoperations and the like and performing safe operations.

[0008] The operation method of the semiconductor storage device of the present application includes a controller that controls operations based on a code read from a ROM, the controller including a cyclic redundancy check (CRC) processing section and an error detection / correction (ECC) processing section, the operation method including: detecting, by the CRC processing section, whether or not a first code read from the ROM has an error using a first algorithm; determining, by the controller, whether or not to shift to a safe mode when the first code is detected to have an error; and detecting and correcting, by the ECC processing section, the error of the first code after the controller determines to shift to the safe mode.

[0009] The semiconductor storage device of the present application includes a controller that controls operations based on a code read from a ROM, the controller including: a cyclic redundancy check (CRC) processing section configured to detect whether or not a first code read from the ROM has an error using a first algorithm; a determination circuit configured to determine whether or not to shift to a safe mode when the CRC processing section detects that the first code has an error; and an error detection / correction (ECC) processing section configured to detect and correct the error of the first code after shifting to the safe mode.

[0010] According to the present application, in the case where an error of a code read from a ROM is detected and a shift to a safe mode is made, the error of the code is detected and the detected error is corrected, so that a malfunction of the code based on the ROM can be suppressed. Further, by detecting a plurality of errors using different algorithms for a plurality of operations included in an operation program, a malfunction or an operation failure can be more effectively suppressed. Furthermore, by holding and enabling output of detection information related to error detection and correction information related to error detection / correction, a site causing a malfunction or an operation failure can be easily determined or analyzed. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An operation flowchart at the time of a power-on program of a conventional flash memory is shown;

[0012] Figure 2 A block diagram of a NAND type flash memory according to an embodiment of the present application is shown;

[0013] Figure 3 A diagram showing functions included in a controller according to an embodiment of the present application is shown;

[0014] Figure 4 A flow of an operation of a controller according to a first embodiment of the present application is shown;

[0015] Figure 5 A flow of an operation of a controller according to a second embodiment of the present application is shown;

[0016] Figure 6 An operation flow of a power-on program based on the second embodiment of the present application is shown;

[0017] Figure 7 An operation flow of a program program based on the second embodiment of the present application is shown;

[0018] Figure 8 A diagram showing an example of a status register based on an embodiment of the present application is shown;

[0019] Figure 9 A flow showing an output example of a status register based on an embodiment of the present application is shown;

[0020] Figure 10 A diagram showing an example of a setting register for setting an operation mode based on a third embodiment of the present application is shown;

[0021] Figure 11 A flow showing a setting of an operation mode based on a third embodiment of the present application is shown.

[0022] [Explanation of Symbols]

[0023] 100: flash memory

[0024] 110: memory cell array

[0025] 120: input / output circuit

[0026] 130: ECC circuit

[0027] 140: address register

[0028] 150: controller

[0029] 160: word line selection circuit

[0030] 170: page buffer / readout circuit

[0031] 180: column selection circuit

[0032] 190: internal voltage generation circuit

[0033] 200: CPU

[0034] 210: ROM

[0035] 220: RAM

[0036] 230: CRC processing section

[0037] 240: ECC processing section

[0038] 250: timer

[0039] 260: status register

[0040] Ax: row address information

[0041] Ay: column address information

[0042] Vers: erase voltage

[0043] Vread: read pass voltage

[0044] Vpass: pass voltage

[0045] Vpgm: program voltage

[0046] S10-S70, S100-S230, S140A, S140B, S230A, S230B, S300-S320, S400-S420: steps DETAILED DESCRIPTION

[0047] The semiconductor storage device of the present application includes a NAND type flash memory, or a microprocessor, a microcontroller, a logic, an Application Specific Integrated Circuit (ASIC), a processor that processes an image or a sound, a processor that processes a signal such as a wireless signal, or the like, in which such a flash memory is embedded. In the following description, a NAND type flash memory is exemplified.

[0048] Figure 2 is a functional block diagram of a NAND type flash memory that represents an embodiment of the present application. The flash memory 100 includes a memory cell array 110, an input / output circuit 120, an Error Checking and Correcting (ECC) circuit 130, an address register 140, a controller 150, a word line selection circuit 160, a page buffer / read circuit 170, a column selection circuit 180, and an internal voltage generation circuit 190. The memory cell array 110 includes a plurality of memory cells arranged in a matrix shape. The input / output circuit 120 outputs read data to the outside, or receives data input from the outside. The ECC circuit 130 generates parity data of data to be programmed, and detects and corrects an error of the programmed data read from the memory cell array 110 based on the parity data. The address register 140 receives address data via the input / output circuit 120. The controller 150 controls each circuit in the flash memory 100 based on command data received via the input / output circuit 120 or a control signal applied to a terminal. The word line selection circuit 160 receives and decodes row address information Ax from the address register 140, and performs selection of a memory block or selection of a word line, or the like, based on a result of the decoding. The page buffer / read circuit 170 holds data read from a page selected by the word line selection circuit 160, or holds data programmed into the selected page. The column selection circuit 180 receives and decodes column address information Ay from the address register 140, and performs selection of a column within the page buffer / read circuit 170, or the like, based on the result of the decoding. The internal voltage generation circuit 190 generates various voltages (a program voltage Vpgm, a pass voltage Vpass, a read pass voltage Vread, an erase voltage Vers, or the like) required for performing reading, programming, and erasing of data, and the like.

[0049] The memory cell array 110 includes a plurality of memory blocks BLK(0), BLK(1),..., BLK(m-1) in the column direction, and a NAND string in which a plurality of memory cells are connected in series is formed in each memory block. The memory cell array 110 includes, in addition to a memory area provided for user use, a memory area not provided for user use (or not accessible by the user) constituted by, for example, a fuse cell. The fuse cell stores setting information (for example, setting of a program or erase voltage or setting of a user's option or the like) related to the operation of the flash memory, the setting information is read at the time of a power-on program, and the read setting information is loaded into a register.

[0050] Figure 3 The structure of the controller 150 of the present embodiment is shown. The controller 150 includes a CPU 200, a ROM 210, a random access memory (RAM) 220, a CRC processing section 230, an ECC processing section 240, a timer 250, and a status register 260.

[0051] The CPU 200 reads a code from the ROM 210 according to an address set in a program counter, decodes the read code, and controls the operation of the word line selection circuit 160, the page buffer / readout circuit 170, the column selection circuit 180, the internal voltage generation circuit 190, and the like based on the decoding result of the read code. The program counter PC is incremented in synchronization with a clock signal, and the CPU 200 reads a next code from the ROM 210 to control a next operation.

[0052] The ROM 210 stores codes for executing various operation programs. For example, codes (including instruction codes or addresses) for controlling a power-on program, a read, a program, an erase, and the like are stored. The number of bits or the number of bytes of the code read at a time by the CPU 200 from the ROM 210 is not particularly limited.

[0053] The CRC processing section 230 checks whether the code (hereinafter referred to as ROM code) read from the ROM 210 contains an error. In order to enable cyclic redundancy check of the ROM code, a CRC parity bit (check data) can be stored in the ROM 210. On the other hand, the CRC processing section 230 divides the code read from the ROM by a generator polynomial identical to that used in the ROM 210, and checks whether the resulting remainder coincides with the CRC parity bit. The generator polynomial used by the CRC processing section 230 and the generated remainder can be stored in the CRC processing section 230. In an alternative embodiment, the CRC parity bit can also be stored in hardwired logic or a nonvolatile memory, without the need for an area for storing the CRC parity bit to be additionally provided in the ROM 210.

[0054] In the present embodiment, if the CRC processing section 230 detects that the ROM code contains an error, the ECC processing section 240 can detect the error of the ROM code and correct the detected error after the operation mode of the CPU 200 is shifted to the safe mode. In order to enable error detection / correction of the ROM code, an ECC parity bit generated when the code is symbolized by ECC can be stored in the ROM 210. The ECC processing section 240 decodes the code (data and the ECC parity bit of the data) read from the ROM 210, detects an error bit of the code read from the ROM, and corrects the error bit. The number of bits that can be subjected to error detection / correction is not particularly limited. After the operation mode of the CPU 200 is shifted to the safe mode, error detection / correction based on the ECC processing section 240 is performed, and the data after error correction is held in the RAM 220. Further, in the case where the ECC circuit 130 is mounted on the flash memory 100, the ECC circuit 130 can also be shared as the ECC processing section 240. In an alternative embodiment, the ECC parity bit can also be stored in hardwired logic or a nonvolatile memory, without the need for an area for storing the ECC parity bit to be additionally provided in the ROM 210.

[0055] The timer 250 measures the elapsed time of the operation program being executed, based on the code of the ROM 210 obtained by the CPU 200. The timer 250 is constituted by hardware different from the CPU 200, and the CPU 200 can provide an instruction to count to the timer 250 when the code is read from the ROM 210. In some modes, the timer 250 outputs an interrupt signal to the CPU 200 when the measured time reaches a predetermined value, and the CPU 200 shifts to the safe mode in response to the interrupt signal.

[0056] The status register 260 holds information on whether the CRC processing section 230 has detected an error, the number of times of error detection by the CRC processing section 230, the number of error detection bits, the ROM region where the error has been detected, the elapsed time of the operation program being executed (hereinafter referred to as CRC error information) during the period in which the CPU 200 reads the code from the ROM 210. Further, the status register 260 also holds information on the number of retries of error detection / correction by the ECC processing section 240, the number of error correction bits, the error correction position, whether the ECC processing section 240 can correct the error (hereinafter referred to as ECC information). The data held by the status register 260 can be read by the user through a command.

[0057] Next, the operation of the controller 150 of the first embodiment of the present application will be described with reference to the flowchart of Fig. 2. Figure 4 Further, the operation program executed by the controller 150 is arbitrary and is not limited to a specific operation program. First, the CPU 200 reads the code from the ROM 210 in accordance with the address set in the program counter (S100). At the time point when the operation program starts, the CPU 200 starts the timer 250 (S110). The timer 250 measures the elapsed time of the operation program being executed, and outputs an interrupt signal to the CPU 200 when the measured time reaches a predetermined time Tn.

[0058] The CPU 200 supplies the code read from the ROM 210 to the CRC processing section 230, and the CRC processing section 230 detects whether the read code has an error (S120). In the case where no error has been detected (S130, Yes), the CPU 200 decodes the code read from the ROM 210 and executes the operation defined by the code (S140).

[0059] On the other hand, in the case where an error has been detected (S130, No), the CPU 200 updates the CRC error information held in the status register 260 (S150), and then determines whether to shift to the safe mode (S160). The determination condition for shifting to the safe mode is that the number of times of error detection based on CRC reaches a predetermined value Nl, or that the CPU 200 receives an interrupt signal from the timer 250 (i.e., the read time of the ROM 210 reaches the predetermined time Tn), and the CPU 200 determines to shift to the safe mode. In the embodiment, the number of times of error detection by the CRC processing section 230 is counted and updated by a counter in step S150.

[0060] In the case of shifting to the safe mode, the CPU 200 causes the ECC processing section 240 to start error detection / correction (S170). At this time, the ECC processing section 240 can store all the codes read from the ROM 210 in the RAM 220, or can store only the position information for error correction in the RAM 220. The CPU 200 also updates the ECC information held in the status register 260 (S180).

[0061] The CPU 200 determines whether the number of retries of error detection / correction by the ECC processing section 240 reaches a prescribed value N2 (S190), and if it does not reach the prescribed value N2, judges that the ROM code after error correction is reliable, decodes using the corrected code held in the RAM 220 or the error position information obtained by holding the code read from the ROM 210 in the RAM 220 and correcting it, and performs an operation in accordance with the result of the decoding (S140). On the other hand, in the case where the number of times of error detection / correction reaches the prescribed value N2, it is judged that a safe operation cannot be expected, and the operation program ends. In one embodiment, in step S190, the number of retries of error detection / correction of the ROM code by the ECC processing section 240 is counted by a second counter.

[0062] Thus, according to the present embodiment, in the case where the code read from the ROM has an error, and further in a certain condition, error detection / correction is performed by the ECC processing section 240, so that a safe operation avoiding an operation failure or a misoperation can be performed. Also, since the CRC error information and the ECC information can be held in the status register 260 and the respective information held can be output, the user can easily perform a detailed analysis of an operation failure or the like of the flash memory.

[0063] Figure 5 is a diagram showing the operation flow of the second embodiment. In the second embodiment, the checking of the CRC at a plurality of times of the operation program is performed using different algorithms.

[0064] In this figure, the steps S100 to S190 are the same as in the first embodiment, but in the second embodiment, after the operation 1 is executed (S140), the CPU 200 reads the code from the ROM 210 (step S200) in order to execute the operation 2 after the operation 1. Next, the code read from the ROM 210 is checked by the CRC processing section 230 (S210). In this embodiment, the algorithm of the check 1 of the CRC of the code for the operation 1 and the algorithm of the check 2 of the CRC of the code for the operation 2 are different. For example, the generation polynomial used in the check 1 is different from the generation polynomial used in the check 2. In this case, the code corresponding to the operation 2 and the CRC parity bit which is the remainder of the division by the generation polynomial of the check 2 are stored in the ROM 210, and the generation polynomial corresponding to the operation 2 is prepared in the CRC processing section 230 and the remainder used for comparison with the CRC parity bit of the check 2 is generated.

[0065] The CPU 200 determines whether or not an error is detected by the CRC processing section 230 (S220), and if no error is detected (S220, Yes), the code is decoded and the operation 2 is executed based on the result of the decoding (S230). On the other hand, if an error is detected in the code (S220, No), the same steps S150 to S190 as in the first embodiment are executed. It is assumed that if the shift to the safe mode is made and the number of retries of the error detection / correction is less than the prescribed value N2, the CPU 200 decodes the corrected code, executes the operation 2, and if the number of retries is the prescribed value N2, the operation program ends. In addition, in the status register 260, the CRC error information and the ECC correction information related to the operation 1 and the operation 2 are held.

[0066] Thus, according to the present embodiment, by using the plurality of CRC check operation programs which differ in the checking ability, the processing corresponding to various main causes which cause the operation failure or the misoperation can be implemented, and the analysis of such main causes can be easily performed. Further, the above-described embodiment shows the example in which the operation program includes the operation 1 and the operation 2, but this is an example, and the operation program can include the operation 1, the operation 2,..., and the operation n, in which case the CRC processing section 230 performs the check 1, the check 2,..., and the check n which differ in the checking ability or the algorithm, and determines whether or not to shift to the safe mode based on the results of the checks.

[0067] Next, a specific example of the operation program of the second embodiment will be described. Figure 6 is a flowchart showing the read operation of the ROM code at the time of execution of the power-on program. The basic operation is the same as that shown in Figure 5 the flowchart, and in the power-on program, the reading of the setting information from the fuse cell (S140A) corresponds to the operation 1, and the loading of the read setting information into the register (S230A) corresponds to the operation 2.

[0068] Figure 7 This describes the flow of ROM code reading operations during the execution of a programming program. Basic operations and... Figure 5 The process shown is the same. In the programming procedure, applying a programming voltage to the selected page (S140B) corresponds to operation 1, and reading the page to be programmed for programming verification (S230B) corresponds to operation 2. The operation procedure of the second embodiment can also be applied to other read operation procedures or erase operation procedures besides the power-on procedure or programming procedure.

[0069] Next, the status register 260 of this embodiment will be explained. For example... Figure 8 As shown, the status register 260 stores CRC error information based on the CRC processing unit 230, including, for example, whether the CRC result is pass or fail, the number of CRC retries, and the measurement time of the timer (used for subsequent determination of whether a specified time Tn has been reached). Furthermore, the status register 260 also stores whether ECC correction can be performed based on ECC information from the ECC processing unit 240, the number of ECC retries, the number of error correction bits, or their positions. The CPU 200 updates the CRC error information or ECC information in the status register 260 during ROM code read operations.

[0070] Figure 9 This is a flowchart illustrating the method of reading data from the status register. After the user inputs a read command for the status register into the flash memory 100 (S300), the controller 150 accesses the status register 260 based on the interpretation result of the command (S310), and outputs CRC error information or ECC information held in the status register 260 via the input / output circuit 120 (S320). By referring to the CRC error information or ECC information, the user can analyze under what operating conditions the ROM code error occurred, or whether the ROM, etc., has defects.

[0071] Next, a third embodiment of the present invention will be described. In the first and second embodiments, operation in safe mode is possible; however, the operation time may exceed the design specifications. Therefore, in the third embodiment, the user can configure whether the flash memory 100 can operate in safe mode.

[0072] Controller 150 uses Figure 10 The setting register shown indicates whether safe mode operation is enabled. For example, flag "1" enables safe mode, and flag "0" disables it. Assuming flag "0" is set, CPU 200... Figure 4 , Figure 5 Instead of switching to safe mode, it only checks things like... Figure 1 The CRC shown.

[0073] Figure 11 is a flowchart showing a setting method of the setting register. After a user inputs a security mode setting command to the flash memory 100 (S400), the controller 150 accesses the setting register according to a result of interpretation of the security mode setting command (S410), and sets a flag of the setting register to "1". In this case, a default state of the setting register is a flag "0". In the case of canceling the security mode, for example, a user inputs a security mode cancel command to the flash memory 100 (S420).

[0074] Thus, according to the present embodiment, by a user setting whether or not the operation of the security mode is performed, for example, the security mode can be operated only when the analysis of the flash memory 100 is performed.

[0075] In the embodiment, the NAND type flash memory is exemplified, but the present application can be applied to a semiconductor device or a semiconductor memory device in which a CPU controls an operation program based on a code read from a ROM.

[0076] Although the preferred embodiments of the present application have been described in detail, the present application is not limited to the specific embodiments, but various modifications, changes, and alterations can be made within the scope of the application as recited in the claims.

Claims

1. An operating method of a semiconductor storage device including a controller that controls an operation based on a code read from a read-only memory, the controller including a CRC processing section and an ECC processing section, the operating method comprising: detecting, by the CRC processing section, whether a first code read from the read-only memory has an error using a first algorithm; determining, by the controller, whether to shift to a safe mode when it is detected that the first code has an error; and detecting and correcting, by the ECC processing section, an error of the first code after the controller determines to shift to the safe mode. counting a number of error detections by the CRC processing section detecting whether the first code has an error using the first algorithm, 2. The operating method of claim 1, further comprising: wherein the step of determining, by the controller, whether to shift to the safe mode includes: determining whether the number of error detections reaches a first prescribed value; and determining, by the controller, to shift to the safe mode when the number of error detections reaches the first prescribed value. measuring an elapsed time of an operation program in execution, 3. The operating method of claim 1, further comprising: wherein the step of determining, by the controller, whether to shift to the safe mode includes: determining whether the measured elapsed time exceeds a certain time; and determining to shift to the safe mode when the measured elapsed time exceeds the certain time. performing a first operation based on the read first code or the corrected first code.

4. The operating method of claim 1, further comprising:

5. The operating method according to claim 4, further comprising: reading a second code corresponding to a second operation from the read-only memory after the first operation; detecting, by the CRC processing section, whether the read second code has an error using a second algorithm different from the first algorithm; determining, by the controller, whether to shift to a safe mode when it is detected that the second code has an error; and detecting and correcting, by the ECC processing section, an error of the second code after the controller determines to shift to the safe mode.

6. The operating method according to claim 1, further comprising: counting a number of retries of detecting and correcting, by the ECC processing section, an error of the first code; and ending, by the controller, the operation when the number of retries exceeds a second prescribed value.

7. The operating method according to claim 1, further comprising: maintaining and updating CRC error information in a status register related to error detection performed by the CRC processing section; and maintaining and updating ECC information in a status register related to error detection and correction performed by the ECC processing section.

8. The operating method according to claim 7, further comprising outputting the CRC error information and the ECC information.

9. The operating method according to claim 8, wherein the CRC error information includes at least one of whether an error is detected, a number of error detections, and an elapsed time of an operation program in execution, and the ECC information includes at least one of whether correction is possible, a number of retries of error detection and correction, and a number of error correction bits. setting the safe mode to be enabled or disabled, ​ ​ ​ 10. The operating method of claim 1, further comprising: ​ wherein the controller determines whether to shift to the safe mode only if the safe mode is set to be enabled.

11. The operation method according to claim 5, wherein the first operation is reading setting information from a fuse cell, and the second operation is loading the setting information read from the fuse cell into a register.

12. A semiconductor storage device including a controller that controls operations based on codes read from a read-only memory, the controller including: a CRC processing section configured to detect whether a first code read from the read-only memory has an error using a first algorithm; a determination circuit configured to determine whether to shift to a safe mode when the CRC processing section detects that the first code has an error; and an ECC processing section configured to detect and correct the first code after shifting to the safe mode.

13. The semiconductor storage device according to claim 12, further comprising: a first counter configured to count a number of times of error detection in which the CRC processing section detects whether the first code has an error using the first algorithm, wherein the determination circuit is configured to determine whether the number of times of error detection reaches a first prescribed value, and the controller determines to shift to the safe mode when the number of times of error detection reaches the first prescribed value.

14. The semiconductor storage device according to claim 12, wherein the controller further includes: a timer configured to measure an elapsed time of an operation program being executed, wherein the determination circuit determines whether the measured elapsed time exceeds a certain time, and determines to shift to the safe mode when the measured elapsed time exceeds the certain time.

15. The semiconductor storage device according to claim 12, wherein the controller is configured to execute a first operation based on the read first code or the corrected first code, and read a second code corresponding to a second operation from the read-only memory after the first operation, the CRC processing section is configured to detect whether the read second code has an error using a second algorithm different from the first algorithm, the determination circuit is configured to determine whether to shift to the safe mode when the CRC processing section detects that the second code has an error, the ECC processing section is configured to detect and correct an error of the second code after shifting to the safe mode.

16. The semiconductor storage device according to claim 12, further comprising: a second counter configured to count a number of times of retry in which the ECC processing section detects and corrects an error of the first code, wherein the controller is configured to end reading the codes from the read-only memory when the number of times of retry exceeds a second prescribed value.

17. The semiconductor memory device of claim 12, wherein the controller further comprises: a status register configured to hold CRC error information related to error detection performed by the CRC processing section, and ECC information related to error detection and correction performed by the ECC processing section.

18. The semiconductor storage device according to claim 12, wherein the controller further comprises a setting register configured to set the security mode to be enabled or disabled, and the determination circuit determines whether to shift to the security mode only in a case where the security mode is set to be enabled.

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