A multilayer ceramic capacitor and its preparation method

Abstract

This invention discloses a multilayer ceramic capacitor and its fabrication method. The multilayer ceramic capacitor includes terminal electrodes; each terminal electrode comprises a base electrode layer, an alloy layer, and a metal layer stacked sequentially; the alloy layer contains 50-80% Cu; and the thickness of the alloy layer is not less than 1 μm. The alloy layer in the terminal electrodes of the multilayer ceramic capacitor of this invention effectively improves the equivalent resistance (ESR) of the multilayer ceramic capacitor by utilizing the high resistivity of the alloy layer while ensuring the bonding strength between the layers in the terminal electrode, thus enhancing the ESR characteristics and increasing the ESR value of the multilayer ceramic capacitor. When the Cu content in the alloy layer is 50-80% and the thickness of the alloy layer is 3-20 μm, the ESR value of the multilayer ceramic capacitor is 1.5-3 mΩ.

Description

Technical Field

[0001] This invention belongs to the field of electronic materials and components, and specifically relates to a multilayer ceramic capacitor and its preparation method. Background Technology

[0002] Multilayer ceramic capacitors are among the most widely used and fastest-growing surface-mount components in the world. They are surface-mount multilayer ceramic capacitors manufactured using alternating dielectrics and electrodes. They are used in digital products such as televisions, mobile phones, computers, medical devices, and video recorders, and are extensively used in coupling, filtering, oscillation, and bypass circuits in electronic components of industrial automation control equipment. Their application is most widespread in high-frequency circuits.

[0003] In recent years, with the increasing frequency of CPU operation and the rapid increase in load current, multilayer capacitors with decoupling capacitors are required to control power supply voltage fluctuations within an acceptable range. This necessitates that multilayer capacitors with decoupling capacitors have large capacitance and high equivalent series resistance (ESR). Existing multilayer ceramic capacitors consist of multiple stacked dielectric layers, internal electrodes arranged opposite each other with dielectric layers between them, and external electrodes electrically connected to the internal electrodes. The external electrode structure consists of three metal layers—Cu, Ni, and Sn—from the inside out, with no transition layer between them. Capacitors with such an electrode structure typically have an ESR of less than 1.3 mΩ, which cannot meet the requirements for multilayer capacitors with decoupling capacitors. Summary of the Invention

[0004] In order to overcome the problems existing in the prior art, one of the objectives of the present invention is to provide a multilayer ceramic capacitor.

[0005] The second objective of this invention is to provide a method for preparing a multilayer ceramic capacitor.

[0006] The third objective of this invention is to provide an application of multilayer ceramic capacitors in electronic products.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] The first aspect of the present invention provides a multilayer ceramic capacitor, comprising a ceramic chip and terminal electrodes; a terminal electrode is provided on each side of the ceramic chip, the ceramic chip is electrically connected to the terminal electrodes, and the terminal electrodes comprise a base electrode layer, an alloy layer and a metal layer stacked sequentially; the content of Cu in the alloy layer is 50-80%; the thickness of the alloy layer is not less than 1 μm.

[0009] Preferably, the base electrode layer in the terminal electrode is located on the ceramic chip.

[0010] Preferably, the Cu content in the alloy layer is 50-70%; more preferably, the Cu content in the alloy layer is 50-60%; and even more preferably, the Cu content in the alloy layer is 50%.

[0011] Preferably, the thickness of the alloy layer is not greater than the thickness of the base electrode layer; more preferably, the thickness of the alloy layer is not greater than half the thickness of the base electrode layer; even more preferably, the thickness of the alloy layer is half the thickness of the base electrode layer.

[0012] Preferably, the alloy layer further includes at least one of Ni, Au, Ag, and Pd; more preferably, the alloy layer further includes at least one of Ni and Au; and even more preferably, the alloy layer further includes Ni.

[0013] Preferably, the material of the base electrode layer is at least one of Cu and Ni; more preferably, the material of the base electrode layer is Cu.

[0014] Preferably, the thickness of the substrate electrode layer is 10–150 μm; more preferably, the thickness of the substrate electrode layer is 10–100 μm; and even more preferably, the thickness of the substrate electrode layer is 15–40 μm.

[0015] Preferably, the metal layer is at least one of a Ni metal layer and a Sn metal layer; more preferably, the metal layer is a Ni metal layer and a Sn metal layer; the Ni metal layer is located between the Sn metal layer and the alloy layer.

[0016] Preferably, the thickness of the Ni metal layer is 0.5-5 μm; more preferably, the thickness of the Ni metal layer is 1-4 μm; and even more preferably, the thickness of the Ni metal layer is 3 μm.

[0017] Preferably, the thickness of the Sn metal layer is 2-10 μm; more preferably, the thickness of the Sn metal layer is 4-8 μm; and even more preferably, the thickness of the Sn metal layer is 5 μm.

[0018] Preferably, the ceramic chip includes an inner electrode layer and a ceramic dielectric layer; the inner electrode layer and the ceramic dielectric layer are alternately stacked; two adjacent inner electrode layers are arranged opposite each other, and the terminal electrode is electrically connected to the inner electrode layer.

[0019] Preferably, the number of inner electrode layers is not less than two, and the number of ceramic dielectric layers is not less than two.

[0020] The functions of each layer in the terminal electrodes of a multilayer ceramic capacitor are as follows:

[0021] A base electrode layer is formed on the side of the ceramic chip; the base electrode layer is preferably a Cu layer. The base electrode layer has two main functions: first, to bring out the internal electrodes inside the ceramic chip so that they can be connected to external electrical inputs to store charge; second, to protect the internal ceramic dielectric layer and the internal electrode layer, preventing the multilayer ceramic capacitor from being damaged by harmful environmental substances during its fabrication and use, which could lead to performance degradation or even failure.

[0022] Alloy Layer: The alloy layer is disposed outside the base electrode layer. The alloy layer can be a conductive metal alloy such as Cu, Ni, or Au, preferably a Cu-Ni alloy. The doping ratio of Cu to Ni in the Cu-Ni alloy is 50%-80% Cu, with Ni as the balance. The optimal doping ratio of Cu to Ni in the Cu-Ni alloy is 50% Cu and 50% Ni. When a Cu-Ni alloy is used as the alloy layer, the base electrode layer inside the alloy layer is a Cu layer, and the metal layer outside the alloy layer is a Ni layer. This selection can fully guarantee the bonding force between the base electrode layer and the Ni metal layer, while also ensuring the sintering compatibility between the alloy layer and the base electrode layer. Furthermore, Cu and Ni can form a continuous solid solution indefinitely, while the alloy layer needs to be co-fired with the base electrode layer, resulting in high sintering compatibility. If the Cu content in the alloy layer is less than 50%, the firing compatibility between the alloy layer and the base electrode layer is significantly reduced, making preparation difficult. If the Cu content is greater than 80%, the resistivity of the alloy layer decreases, resulting in a weaker effect on improving the ESR characteristics of the multilayer ceramic capacitor, and thus failing to increase the ESR value. The alloy layer improves the ESR characteristics of multilayer ceramic capacitors mainly by utilizing its high resistivity. Compared to pure metals, the resistivity of the alloy is significantly increased. The equivalent series resistance is related not only to resistivity but also directly to the effective area and thickness of the alloy layer. The effective area is constrained by the end dimensions of the multilayer ceramic capacitor, while its thickness is adjustable within a certain range; the greater the thickness, the greater the equivalent series resistance. If the alloy layer thickness is <1μm, its contribution to the equivalent series resistance is very small and has little substantial effect. If the alloy layer thickness is greater than the base electrode layer thickness, co-firing with the base electrode layer during preparation is difficult. Furthermore, the size requirements of the multilayer ceramic capacitor itself also limit the thickness of the terminal electrodes, thus limiting the thickness of the alloy layer.

[0023] Ni metal layer: The Ni metal layer is disposed on the outside of the alloy layer; the function of the Ni metal layer is to act as a heat barrier layer to prevent the multilayer ceramic capacitor body from being subjected to excessive thermal shock during welding.

[0024] Sn metal layer: The Sn metal layer is disposed outside the Ni metal layer; the Sn metal layer serves as a solderable metal layer to ensure that the multilayer ceramic capacitor has good solderability.

[0025] A second aspect of the present invention provides a method for preparing the above-mentioned multilayer ceramic capacitor, comprising the following steps:

[0026] S1: Coat a base electrode layer paste on a ceramic chip, then coat an alloy layer electrode paste on the base electrode layer paste, dry and cure to obtain a ceramic chip containing an alloy layer and a base electrode layer.

[0027] S2: A metal layer is formed on the alloy layer by electroplating deposition to obtain the multilayer ceramic capacitor.

[0028] Preferably, the method for preparing the ceramic chip includes the following steps:

[0029] S01: The raw materials of ceramic slurry are mixed and ball-milled, then cast and dried to obtain a ceramic dielectric layer;

[0030] S02: An inner electrode layer is formed on a ceramic dielectric layer by a printing process, thus obtaining a ceramic dielectric layer with an inner electrode layer printed on it.

[0031] S03: The ceramic chip is obtained by sequentially stacking, pressing, debinding and sintering the ceramic dielectric layer with the inner electrode layer printed on it.

[0032] Preferably, the raw materials for the ceramic slurry include ceramic powder, binder, and solvent.

[0033] Preferably, the substrate electrode layer slurry comprises the following components by mass percentage: 60-80% metal, 10-25% organic carrier, 2-10% glass material, 1-5% inorganic additives, and 0.5-1% dispersant.

[0034] Preferably, the metallic material is copper powder, which includes spherical copper powder and flake copper powder, with a mass ratio of spherical copper powder to flake copper powder of (2.8-3.2):1; more preferably, the metallic material is copper powder, which includes spherical copper powder and flake copper powder, with a mass ratio of spherical copper powder to flake copper powder of 3:1. Spherical copper powder has fewer contact points than flake copper powder, and their ratio affects the sintering density and rheological properties of the copper paste. Generally, a higher proportion of flake copper powder contributes to sintering density, while a higher proportion of spherical copper powder contributes to obtaining better paste rheological properties. Under the ratios specified in this invention, a copper paste with both good sintering density and good paste rheological properties will be obtained.

[0035] Preferably, the spherical copper powder is prepared by chemical vapor deposition and chemical liquid phase deposition.

[0036] Preferably, the flake copper powder is obtained by mechanically grinding spherical copper powder to extend it.

[0037] Preferably, the alloy layer slurry comprises the following components by mass percentage: 60-80% alloy powder, 10-25% organic carrier, 2-10% glass material, 1-5% inorganic additives, and 0.5-1% dispersant.

[0038] Preferably, in the substrate electrode layer slurry and / or alloy layer slurry, the organic carrier includes a thermoplastic resin and a solvent.

[0039] Preferably, the thermoplastic resin is selected from at least one of acrylic resin, cellulose resin, and alkyd resin.

[0040] Preferably, the solvent is selected from at least one of terpineol, butylcarbidol, and DBE.

[0041] Preferably, in the substrate electrode layer slurry and / or alloy layer slurry, the organic carrier is polymethacrylate resin and terpineol.

[0042] Preferably, in the substrate electrode layer paste and / or alloy layer paste, the glass material includes at least one of B2O3, BaO, Al2O3, ZnO, and SiO2.

[0043] Preferably, in the substrate electrode layer slurry and / or alloy layer slurry, the inorganic additive includes at least one of CuO, Cu2O, and TiO2.

[0044] Preferably, in the substrate electrode layer slurry and / or alloy layer slurry, the dispersant includes BYK-111 dispersant.

[0045] Preferably, the preparation methods of the substrate electrode layer slurry and the alloy layer slurry are both: the raw materials of the substrate electrode layer slurry are sequentially mixed, dispersed and stirred, ground and filtered.

[0046] Preferably, step S2 specifically involves: using a pure metal rod as the anode and a ceramic chip containing an alloy layer and a base electrode layer as the cathode, electroplating is performed in a plating solution to form a metal layer on the alloy layer, thereby obtaining the multilayer ceramic capacitor.

[0047] During the electroplating process, the metal (Ni and / or Sn) acting as the anode loses electrons and becomes metal ions that enter the plating solution. Under the action of the electric field, they diffuse and migrate toward the cathode (a ceramic chip containing an alloy layer and a base electrode layer), are adsorbed near the cathode, and gain electrons at the cathode to be reduced to metal, forming a metal crystal with a certain lattice, thereby forming a metal layer on the alloy layer.

[0048] When electroplating a Ni electrode layer, pure metallic nickel is used as the anode, and a ceramic chip containing an alloy layer and a base electrode layer is used as the cathode. Electroplating is carried out in the electroplating solution, thereby forming a Ni electrode layer on the alloy layer.

[0049] When electroplating the Sn electrode layer, pure metallic tin is used as the anode, and a ceramic chip containing a Ni electrode layer, an alloy layer, and a base electrode layer is used as the cathode. Electroplating is carried out in the electroplating solution, thereby forming the Sn electrode layer on the Ni electrode layer.

[0050] A third aspect of the present invention provides an application of the above-described multilayer ceramic capacitor in electronic products.

[0051] Preferably, the electronic product includes a television set, a mobile phone, a computer, a medical device, or a video recorder.

[0052] The beneficial effects of this invention are as follows: The terminal electrodes of the multilayer ceramic capacitor of this invention contain an alloy layer, which can effectively improve the equivalent resistance of the multilayer ceramic capacitor by utilizing the high resistivity of the alloy layer while ensuring the bonding strength of each layer in the terminal electrode, thereby improving the ESR characteristics and increasing the ESR value of the multilayer ceramic capacitor. When the Cu content in the alloy layer is 50-80% and the thickness of the alloy layer is 3-20 μm, the ESR value of the multilayer ceramic capacitor is 1.5-3 mΩ. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the structure of the multilayer ceramic capacitor in Embodiment 1 of the present invention. Detailed Implementation

[0054] The specific implementation of the present invention will be further described in detail below with reference to the accompanying drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described in detail below are those that can be implemented or understood by those skilled in the art by referring to the prior art. Reagents or instruments whose manufacturers are not specified are considered to be conventional products that can be purchased commercially.

[0055] Example 1:

[0056] Reference Figure 1 The schematic diagram shows the structure of a multilayer ceramic capacitor. In this example, the multilayer ceramic capacitor includes a ceramic chip, a first terminal electrode, and a second terminal electrode. The ceramic chip includes an inner electrode layer and a ceramic dielectric layer, which are alternately stacked. Adjacent inner electrode layers are positioned opposite each other and do not contact each other. The first terminal electrode and the second terminal electrode are respectively located on opposite sides of the ceramic chip. The first terminal electrode is electrically connected to the inner electrode layer closest to it, and the second terminal electrode is electrically connected to the inner electrode layer closest to it. The structure of the first terminal electrode is the same as that of the second terminal electrode.

[0057] The first terminal electrode includes a base electrode layer, an alloy layer, a Ni layer, and a Sn layer stacked sequentially; the base electrode layer is located on a ceramic chip.

[0058] The multilayer ceramic capacitor in this example is prepared using the following method, specifically including the following steps:

[0059] (1) The raw materials of ceramic slurry are mixed and ball-milled to obtain ceramic slurry, wherein the raw materials of ceramic slurry include ceramic powder, binder and solvent; based on the total mass of ceramic slurry, the mass percentage of ceramic powder is 30%, the mass percentage of binder is 4%, and the mass percentage of solvent is 66%; wherein the ceramic powder is barium titanate, the binder is PVB and the solvent is toluene.

[0060] (2) Cast a portion of the ceramic slurry from step (1) to form a thin film, and dry it to obtain a ceramic dielectric layer with a thickness of 1.2 μm;

[0061] (3) An inner electrode layer is formed on the surface of the ceramic dielectric layer obtained in step (2) by printing process. The thickness of the inner electrode layer is 0.9 μm. The inner electrode layer is a nickel metal layer.

[0062] (4) The ceramic dielectric layer with the inner electrode layer is stacked and pressed; then the adhesive is removed in the air at a temperature of 240°C, and then sintered at a temperature of 1200°C for 2 hours to obtain the ceramic chip, wherein the number of ceramic dielectric layers with the inner electrode layer stacked in the ceramic chip is 220.

[0063] (5) A first terminal electrode and a second terminal electrode are formed on the ceramic chip.

[0064] The process of forming the first terminal electrode and the second terminal electrode on the ceramic chip is as follows:

[0065] (a) Preparation of the base electrode layer and alloy layer: The base electrode layer and alloy layer are prepared by end-burning process, specifically: the base electrode layer electrode paste and the alloy layer electrode paste are prepared separately; then the base electrode layer electrode paste and the alloy layer electrode paste of corresponding thickness are sequentially coated on both ends of the multilayer ceramic capacitor, and then dried and cured to form the base electrode layer and the alloy layer sequentially on both ends of the ceramic chip. The base electrode layer is located between the alloy layer and the ceramic chip. The thickness of the base electrode layer is 20 μm and the thickness of the alloy layer is 10 μm.

[0066] The substrate electrode layer slurry formulation is as follows:

[0067] The raw materials for the substrate electrode layer slurry are copper, organic carrier, glass powder, inorganic additives and dispersants.

[0068] The copper in this substrate electrode layer slurry comprises spherical and flake copper powders, with the total mass percentage of spherical and flake copper powders being 74%, and the mass ratio of spherical to flake copper powders being 3:1. The organic carrier accounts for 15% of the slurry, consisting of polymethyl methacrylate resin and terpineol, with a mass ratio of polymethyl methacrylate resin to terpineol being 2:1. Glass powder accounts for 8% of the slurry. Based on the total weight of the glass powder, the mass percentages are: B2O3 25%; BaO 10%; Al2O3 30%; ZnO 5%; and SiO2 30%. The inorganic additive accounts for 2% of the slurry, consisting of TiO2; and the dispersant accounts for 1% of the slurry, consisting of BYK-111 dispersant. The substrate electrode layer slurry is prepared by mixing, dispersing, grinding, and filtering the raw materials in the above-mentioned substrate electrode layer slurry.

[0069] The formulation of the alloy layer slurry is as follows:

[0070] The raw materials for the alloy layer slurry are copper powder, nickel powder, organic carrier, glass powder, inorganic additives and dispersants.

[0071] Based on the total mass of the alloy layer slurry, the alloy powder accounts for 69% by mass, of which copper powder accounts for 50% and nickel powder accounts for 50% by mass. The organic carrier accounts for 20% by mass, consisting of polymethyl methacrylate resin and terpineol in a mass ratio of 2:1. The glass powder accounts for 8% by mass, comprising 25% B2O3, 10% BaO, 30% Al2O3, 5% ZnO, and 30% SiO2. The inorganic additive accounts for 2% by mass, consisting of CuO. The dispersant accounts for 1% by mass, consisting of BYK-111 dispersant. The alloy layer electrode slurry is prepared by mixing, dispersing, stirring, grinding, and filtering the raw materials in the alloy layer slurry.

[0072] (b) Preparation of Ni and Sn layers: Ni and Sn layers were sequentially prepared on the alloy layer by electroplating deposition. During the electroplating process, the metallic Ni and Sn, acting as the anode, lost electrons and became metal ions that entered the plating bath. Under the influence of the electric field, they diffused and migrated towards the cathode (the alloy layer of the ceramic chip) and were adsorbed near the cathode. There, they gained electrons and were reduced to metal, forming a metal crystal with a certain lattice. Thus, Ni and Sn layers were sequentially formed on the alloy layer on the ceramic chip.

[0073] The Ni layer formulation is as follows: pure metallic nickel is used as the anode, and a ceramic chip containing an alloy layer and a base electrode layer is used as the cathode. Electroplating is performed in an electrolyte to form a Ni layer on the alloy layer.

[0074] The Sn layer formulation: Pure tin is used as the anode, and a ceramic chip containing a Ni layer, an alloy layer, and a base electrode layer is used as the cathode. Electroplating is performed in an electrolyte to form a Sn layer on the Ni layer.

[0075] A 0201 specification 1μF capacitor was used as a comparison, and its ESR at its natural frequency (approximately 600MHz) was measured to verify the example. This specification has a small size, and its alloy layer thickness has an upper limit of 20μm.

[0076] The parameters of the first terminal electrode and the second terminal electrode in this example are shown in Table 1 below.

[0077] Table 1. Parameters of the first and second terminal electrodes in Example 1

[0078]

[0079] Examples 2-7

[0080] The structure and preparation method of the multilayer ceramic capacitors in Examples 2-7 are the same as those in Example 1. The difference between Examples 2-7 and Example 1 is that the Cu content in the alloy layer of Examples 2-7 is different from that in Example 1. Specifically:

[0081] In Example 2, the Cu content in the alloy layer is 55%;

[0082] In Example 3, the Cu content in the alloy layer is 60%;

[0083] In Example 4, the Cu content in the alloy layer was 65%;

[0084] In Example 5, the Cu content in the alloy layer was 70%;

[0085] In Example 6, the Cu content in the alloy layer is 75%;

[0086] In Example 7, the Cu content in the alloy layer is 80%.

[0087] Examples 8-10

[0088] The structure and preparation method of the multilayer ceramic capacitors in Examples 8-10 are the same as those in Example 1. The difference between Examples 8-10 and Example 1 is that the thickness of the alloy layer in Examples 8-10 is different from that in Example 1. Specifically:

[0089] The thickness of the alloy layer in Example 8 is 3 μm;

[0090] The thickness of the alloy layer in Example 9 is 5 μm;

[0091] The thickness of the alloy layer in Example 10 is 20 μm.

[0092] Comparative Examples 1-4

[0093] The structures and preparation methods of the multilayer ceramic capacitors in Comparative Examples 1-4 are the same as those in Example 1. The difference between Comparative Examples 1-4 and Example 1 is that the Cu content in the alloy layer of Comparative Examples 1-4 is different from that in Example 1. Specifically:

[0094] The Cu content in the alloy layer of Comparative Example 1 is 0%;

[0095] The alloy layer in Comparative Example 2 contains 90% Cu.

[0096] The Cu content in the alloy layer of Comparative Example 3 is 95%;

[0097] The alloy layer in Comparative Example 4 contains 100% Cu.

[0098] Comparative Examples 5-6

[0099] The structure and preparation method of the multilayer ceramic capacitors in Comparative Examples 5 and 6 are the same as those in Example 1. The difference between Comparative Examples 5 and 6 and Example 1 is that the thickness of the alloy layer in Comparative Examples 5 and 6 is different from that in Example 1. Specifically:

[0100] The thickness of the alloy layer in Comparative Example 5 is 0 μm, meaning that no alloy layer was set in Comparative Example 5.

[0101] The thickness of the alloy layer in Comparative Example 6 is 0.5 μm.

[0102] Performance testing:

[0103] The resistivity, ESR value, and capacitance of the alloy layer of the multilayer ceramic capacitors prepared in Examples 1-10 and Comparative Examples 1-6 were tested respectively. The resistivity of the alloy layer was tested by directly measuring the resistivity of the alloy layer slurry using a resistivity meter. The ESR value was tested by taking a sample of the multilayer ceramic capacitor prepared after electroplating and measuring its ESR value at room temperature using an impedance analyzer (Agilent 4287A) under conditions of 1MHz-3GHz (this frequency range is the natural frequency of the multilayer ceramic capacitor in this invention). SThe capacitance value was tested using an impedance analyzer at room temperature. The test voltage was 1V, and the test frequency was 1kHz. The specific test results are shown in Table 2 below.

[0104] Table 2. Resistivity, ESR value, and capacitance of the alloy layers in multilayer ceramic capacitors.

[0105]

[0106] As shown in Table 2, the multilayer ceramic capacitors prepared in Examples 1-10 of this invention have superior ESR values ​​compared to Comparative Examples 1-6. With increasing Cu content in the alloy layer, the resistivity of the alloy layer gradually decreases, and the ESR of the multilayer ceramic capacitor also gradually decreases; conversely, with increasing alloy layer thickness, the ESR value of the multilayer ceramic capacitor gradually increases. Therefore, to obtain a high ESR value, the Cu content in the alloy layer of the multilayer ceramic capacitor needs to be maintained within a suitable range, and the alloy layer needs to have an appropriate thickness. By setting Examples 1-10 and Comparative Examples 1-6, this invention screened out alloy layers with a Cu content of 50-80% and an alloy layer thickness of 1-20 μm. Within this range, the multilayer ceramic capacitor exhibits excellent ESR values; when the Cu content in the alloy layer is 50-60% and the alloy layer thickness is 10-20 μm, the ESR value of the multilayer ceramic capacitor is greater than 2 mΩ.

[0107] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A multilayer ceramic capacitor, comprising a ceramic chip and terminal electrodes, characterized in that: The ceramic chip has a terminal electrode on each side, and the ceramic chip is electrically connected to the terminal electrode. The terminal electrode includes a base electrode layer, an alloy layer and a metal layer stacked in sequence. The alloy layer contains 50-60% Cu and the balance is Ni; the thickness of the alloy layer is 10-20 μm. The substrate electrode layer is made of Cu; The metal layer is a Ni metal layer and a Sn metal layer; the Ni metal layer is located between the Sn metal layer and the alloy layer. The thickness of the substrate electrode layer is 15–40 μm; The thickness of the Ni metal layer is 0.5-5 μm; The thickness of the Sn metal layer is 2-10 μm.

2. The multilayer ceramic capacitor according to claim 1, characterized in that: The alloy layer contains 50% Cu.

3. The method for preparing the multilayer ceramic capacitor according to any one of claims 1 to 2, characterized in that: Includes the following steps: S1: Coat a base electrode layer paste on a ceramic chip, then coat an alloy layer electrode paste on the base electrode layer paste, dry and cure to obtain a ceramic chip containing an alloy layer and a base electrode layer. S2: A metal layer is formed on the alloy layer by electroplating deposition to obtain the multilayer ceramic capacitor.

4. The method for preparing a multilayer ceramic capacitor according to claim 3, characterized in that: The substrate electrode layer paste comprises the following components by mass percentage: 60-80% metallic materials, 10-25% organic carrier, 2-10% glass materials, 1-5% inorganic additives, and 0.5-1% dispersant.

5. The method for preparing a multilayer ceramic capacitor according to claim 4, characterized in that: The metallic material is copper powder, which includes spherical copper powder and flake copper powder, and the mass ratio of spherical copper powder to flake copper powder is (2.8~3.2):

1.

6. The application of the multilayer ceramic capacitor according to any one of claims 1 to 2 in electronic products.

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