Semiconductor structure and high electron mobility transistor

Abstract

A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a compositionally graded layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the compositionally graded layer is disposed between the electrical isolation layer and the superlattice structure. The compositionally graded layer and the superlattice structure include a same third group element, and the atomic percentage of the same third group element in the compositionally graded layer gradually decreases in a direction from the superlattice structure to the electrical isolation layer. Further, a high electron mobility transistor including the semiconductor structure is provided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a semiconductor structure and a high electron mobility transistor containing the semiconductor structure. Background Technology

[0002] In semiconductor technology, group III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are a type of transistor with a two-dimensional electron gas (2-DEG), where the 2-DEG is adjacent to the junction between two materials with different band gaps (i.e., a heterojunction). Because HEMTs do not use doped regions as carrier channels but rather use 2-DEGs, they possess several attractive characteristics compared to known metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] A known HEMT may consist of a channel layer, a barrier layer, a compound semiconductor capping layer, and a gate electrode stacked in sequence. By applying a bias voltage to the compound semiconductor capping layer using the gate electrode, the concentration of a two-dimensional electron gas in the channel layer located beneath the compound semiconductor capping layer can be controlled, thereby controlling the switching of the HEMT.

[0004] However, the stress caused by lattice mismatch in the above-mentioned HEMT stack leads to polarization effect, resulting in leakage current in the HEMT and thus reducing the electrical performance of the HEMT. Summary of the Invention

[0005] In view of this, it is necessary to propose an improved high electron mobility transistor to enhance the electrical performance of HEMT.

[0006] According to an embodiment of the present invention, a semiconductor structure is provided, including a superlattice structure, an electrically insulating layer, a channel layer, and a compositional gradient layer. The superlattice structure is disposed on a substrate, the electrically insulating layer is disposed on the superlattice structure, the channel layer is disposed on the electrically insulating layer, and the compositional gradient layer is disposed between the electrically insulating layer and the superlattice structure. The compositional gradient layer and the superlattice structure contain the same Group 3 element, and the atomic percentage of the same Group 3 element in the compositional gradient layer gradually decreases from the superlattice structure to the electrically insulating layer.

[0007] According to an embodiment of the present invention, a high electron mobility transistor is provided, comprising the above-described semiconductor structure, a barrier layer, a doped semiconductor capping layer, a gate electrode, a source electrode, and a drain electrode. The barrier layer is disposed on the channel layer, the doped semiconductor capping layer is disposed on the barrier layer, the gate electrode is disposed on the doped semiconductor capping layer, and the source electrode and drain electrode are respectively disposed on opposite sides of the gate electrode.

[0008] To make the features of the present invention clear and easy to understand, embodiments are provided below, and detailed descriptions are given in conjunction with the accompanying drawings. Attached Figure Description

[0009] To facilitate understanding of the following text, reference should be made to the accompanying drawings and their detailed description while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain figures may be intentionally enlarged or reduced.

[0010] Figure 1 This is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present invention.

[0011] Figure 2 This is an enlarged cross-sectional schematic diagram illustrating the first superlattice stack, tensile stress layer, gradient layer, and electrical isolation layer of a HEMT according to another embodiment of the present invention.

[0012] Figure 3 , 4 5 and 6 are concentration curves of the atomic percentage of the same Group III element, such as aluminum (Al), in the compositional gradient layer, tensile stress layer, and uppermost second superlattice layer of the HEMT according to different embodiments of the present invention, as varying with different depth positions.

[0013] Figure 7 , 8 Figures 9 and 10 are cross-sectional schematic diagrams illustrating an intermediate stage in the fabrication of a HEMT according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100… High electron mobility transistor

[0016] 102…base

[0017] 104…nucleation layer

[0018] 106… superlattice structure

[0019] 106-1…First Superlattice Stack

[0020] 106-2…Second Superlattice Stack

[0021] 106A…First Superlattice Layer

[0022] 106B…Second Superlattice Layer

[0023] 108…Tension stress layer

[0024] 110… forms a gradient layer

[0025] 112… Electrical isolation layer

[0026] 114…Channel Layer

[0027] 116…Barrier Layer

[0028] 118…Doped Semiconductor Cap Layer

[0029] 120…Isolation Zone

[0030] 122…Source Electrode

[0031] 124…Drain electrode

[0032] 125…contact hole

[0033] 126…Gate electrode

[0034] 128…passivation layer

[0035] 128-1…First passivation layer

[0036] 128-2… First passivation layer

[0037] 130… Two-dimensional electron gas region

[0038] 140… Two-dimensional electric hole gas

[0039] 150… Two-dimensional electronic gas

[0040] C1… value

[0041] C2… value

[0042] C3… value

[0043] 201…straight line

[0044] 202… arc

[0045] 203…stepped curve

[0046] 204…wavy curve Detailed Implementation

[0047] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0048] Furthermore, regarding the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one element or feature and another (or more) element or feature in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0049] Although this invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by such terminology. These terms are used only to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the elements, nor do they represent the order of arrangement of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0050] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0051] In this invention, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Furthermore, "Group III-V semiconductors" can be binary, ternary, or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), and their analogues or combinations thereof, but are not limited thereto. In addition, depending on requirements, Group III-V semiconductors may also include dopants to form Group III-V semiconductors with specific conductivity types, such as n-type or p-type Group III-V semiconductors. In the following text, Group III-V semiconductors may also be referred to as III-V semiconductors.

[0052] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0053] This invention relates to a semiconductor structure and a high electron mobility transistor (HEMT) including this semiconductor structure, which can be used as a power switching transistor for voltage converter applications. Compared to silicon power transistors, III-V semiconductor HEMTs (III-V HEMTs) have a wider band gap, thus exhibiting low on-state resistance and low switching losses.

[0054] Figure 1 This is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present invention. Figure 1As shown, according to an embodiment of the present invention, a high electron mobility transistor 100, such as an enhancement-mode HEMT, is disposed on a substrate 102, and a nucleation layer 104, a superlattice (SL) structure 106, a composition gradient layer 110, an electrical isolation layer 112, a channel layer 114, a barrier layer 116, a doped semiconductor capping layer 118, and a passivation layer 128 are sequentially disposed on the substrate 102. According to one embodiment, the superlattice structure 106 may include two or more different superlattice stacks, for example, a first superlattice stack 106-1 disposed on a second superlattice stack 106-2. Each superlattice stack may include multiple pairs of superlattice layers, and the superlattice layers may be periodically alternately stacked. Each superlattice layer may be composed of two or more materials, and the thickness of each superlattice layer is approximately several nanometers (nm) to tens of nanometers. The first superlattice stack 106-1 and the second superlattice stack 106-2 may have different material compositions, different material composition ratios, or different material periodic alternation stacking methods. According to another embodiment, the superlattice structure 106 may be a single superlattice stack, such as the first superlattice stack 106-1.

[0055] Furthermore, the high electron mobility transistor 100 also includes a gate electrode 126, a source electrode 122, and a drain electrode 124. The gate electrode 126 is disposed on a doped semiconductor capping layer 118 and extends through the passivation layer 128. The source electrode 122 and the drain electrode 124 are respectively disposed on opposite sides of the gate electrode 126. According to some embodiments, the source electrode 122 and the drain electrode 124 may extend downward from the passivation layer 128 into the barrier layer 116 or the channel layer 114, and are separated from the electrical isolation layer 112 by a vertical distance. In addition, an isolation region 120 is disposed around the source electrode 122 and the drain electrode 124 to isolate adjacent HEMTs. The isolation region 120 extends through the barrier layer 116 into the channel layer 114, and the bottom of the isolation region 120 is lower than the bottom of the source electrode 122 and the drain electrode 124, making the isolation region 120 closer to the electrical isolation layer 112 than the source electrode 122 and the drain electrode 124, thus achieving good electrical isolation. However, in other embodiments, the isolation region 120 may extend to other layers as needed to achieve electrical isolation.

[0056] According to one embodiment of the present invention, the channel layer 114 may comprise one or more III-V semiconductor layers. The composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. Furthermore, the channel layer 114 may be an undoped or doped one or more III-V semiconductor layers. A doped channel layer 114 may be, for example, a p-type III-V semiconductor layer. For a p-type III-V semiconductor layer, the dopant may be carbon (C), iron (Fe), magnesium (Mg), or zinc (Zn), but is not limited thereto. The aforementioned barrier layer 116 may comprise one or more III-V semiconductor layers, and its composition may differ from that of the III-V semiconductor layer 114. For example, the barrier layer 116 may comprise AlN, Al... z Ga (1-z) N (0 < z < 1) or a combination thereof. According to one embodiment, the channel layer 114 may be an undoped GaN layer, while the barrier layer 116 may be an undoped or essentially n-type AlGaN layer. Due to the discontinuous bandgap between the channel layer 114 and the barrier layer 116, by stacking the channel layer 114 and the barrier layer 116 together, electrons are concentrated at the heterojunction between the channel layer 114 and the barrier layer 116 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, namely a two-dimensional electron gas (2-DEG) region 130. For normally-off devices, when no voltage is applied to the gate electrode 126, the region covered by the doped semiconductor capping layer 118 does not form a 2-DEG and can be regarded as a 2-DEG cutoff region. At this time, there is no conduction between the source electrode 122 and the drain electrode 124. When a positive voltage is applied to the gate electrode 126, a 2-DEG is formed in the region covered by the doped semiconductor capping layer 118, resulting in a continuous 2-DEG region 130 between the source electrode 122 and the drain electrode 124, thus making the source electrode 122 and the drain electrode 124 conductive.

[0057] Figure 2 This is an enlarged cross-sectional schematic diagram illustrating the first superlattice stack, tensile stress layer, gradient layer, and electrical isolation layer of a high electron mobility transistor according to another embodiment of the present invention. Figure 2 and Figure 1 The difference lies in Figure 2 A tensile stress layer 108 is also provided between the first superlattice stack 106-1 and the gradient layer 110. For example... Figure 2 As shown, according to an embodiment of the present invention, the first superlattice stack 106-1 of the high electron mobility transistor 100 may be composed of a plurality of paired stacked first superlattice layers 106A and second superlattice layers 106B. Although Figure 2Only four pairs of superlattice layers are shown. According to other embodiments of the present invention, the first superlattice stack 106-1 can also be composed of more pairs of superlattice layers, for example, more than 100 pairs. The first superlattice layer 106A has tensile stress, the second superlattice layer 106B has compressive stress, and the second superlattice layer 106B is stacked on top of the first superlattice layer 106A. In other words, the first superlattice layer 106A generates tensile stress on the adjacent second superlattice layer 106B, and the second superlattice layer 106B generates compressive stress on the adjacent first superlattice layer 106A. By adjusting the thickness of each layer of the first superlattice layer 106A and the second superlattice layer 106B, the 2-DEG150 and 2-DHG140 in the other second superlattice layers 106B (excluding the topmost second superlattice layer 106B) can be paired to cancel each other out. Furthermore, according to an embodiment of the present invention, a tensile stress layer 108 is provided on the uppermost second superlattice layer 106B, which can generate 2-DEG in the uppermost second superlattice layer 106B to counteract 2-DHG in the uppermost second superlattice layer 106B. This can prevent the uppermost second superlattice layer 106B from generating a 2-DHG layer that is not paired with 2-DEG, thereby preventing the generation of lateral current transmission paths and avoiding leakage current between adjacent HEMTs.

[0058] Furthermore, according to one embodiment of the present invention, a compositional gradient layer 110 is provided between the electrical isolation layer 112 and the first superlattice stack 106-1 of the superlattice structure 106, and the compositional gradient layer 110 is disposed on the tensile stress layer 108. The compositional gradient layer 110 can be used to eliminate the compressive stress of the electrical isolation layer 112 on the tensile stress layer 108. According to one embodiment of the present invention, the superlattice structure 106, the tensile stress layer 108, and the compositional gradient layer 110 all contain the same Group 3 element, and the atomic percentage of this same Group 3 element in the compositional gradient layer 110 gradually decreases from the superlattice structure 106 to the electrical isolation layer 112 to avoid compressive stress in the electrical isolation layer 112. Therefore, 2-DHG is not generated at the interface between the electrical isolation layer 112 and the compositional gradient layer 110, which avoids the formation of a 2-DHG layer on the bottom surface of the electrical isolation layer 112, thereby preventing the generation of lateral current transmission paths and avoiding leakage current between adjacent HEMTs.

[0059] Furthermore, according to an embodiment of the present invention, by adjusting the composition of the graded layer 110, the bottom of the graded layer 110 can have tensile stress. Thus, tensile stress can be generated in the topmost second superlattice layer 106B, and 2-DEG can be generated in the topmost second superlattice layer 106B to cancel the 2-DHG in the topmost second superlattice layer 106B. Therefore, even if the tensile stress layer 108 is not provided, the degree of leakage current occurring between adjacent HEMTs can be reduced.

[0060] In addition, in the embodiment of the present invention, in addition to avoiding leakage current between adjacent HEMTs, due to the composition of the graded layer 110, the tensile stress layer 108, and the superlattice structure 106, good lattice matching exists between these stacked layers. Therefore, stress generation in the HEMT stacked layers can be avoided, and further polarization effect generation can be avoided, reducing various leakage currents of the HEMT of the present invention, thereby improving the electrical performance of the HEMT.

[0061] According to an embodiment of the present invention, the composition of the graded layer 110 can be a ternary III-V semiconductor, such as aluminum gallium nitride (Al x Ga (1-x) N), where 0.1 < x < 0.9, and the x value gradually decreases in the direction from the superlattice structure 106 to the electrical isolation layer 112. That is, in the depth direction, the atomic percentage of the aforementioned same group III element, such as aluminum (Al), in the graded layer 110 decreases from bottom to top, and the atomic percentage of another group III element, such as gallium (Ga), in the graded layer 110 increases from bottom to top. The electrical isolation layer 112 contains this another group III element, such as gallium (Ga). In one embodiment, the composition of the tensile stress layer 108 can be a binary III-V semiconductor, such as aluminum nitride (AlN). According to an embodiment, the average atomic concentration of the same group III element, such as aluminum (Al), in the tensile stress layer 108 is higher than the average atomic concentration of this same group III element, such as aluminum (Al), in the graded layer 110. In addition, in one embodiment, the thickness of the graded layer 110 can be 0.5% to 5% of the thickness of the electrical isolation layer 112, and the thickness of the tensile stress layer 108 can be 0.2% to 2% of the thickness of the electrical isolation layer 112. It should be noted that the thicknesses of the graded layer 110 and the tensile stress layer 108 must be greater than the thicknesses of each superlattice layer, such as greater than the thickness of the first superlattice layer 106A or the second superlattice layer 106B, to be sufficient to generate or eliminate the stress at the interface. According to an embodiment of the present invention, a dopant can be doped in the graded layer 110, and the dopant can be carbon or iron, thereby increasing the resistivity of the graded layer 110.

[0062] According to an embodiment of the present invention, when comparing the first superlattice layer 106A and the second superlattice layer 106B, the lattice constant of the composition of the first superlattice layer 106A is smaller and the energy gap is wider, such as aluminum nitride (AlN), and the lattice constant of the composition of the second superlattice layer 106B is larger and the energy gap is narrower, such as aluminum gallium nitride (Al y Ga (1-y) N, where 0.05 < y < 0.3). The average atomic concentration of the same group III element such as aluminum (Al) in the compositional graded layer 110 is higher than the average atomic concentration of the same group III element such as aluminum (Al) in these second superlattice layers 106B. According to an embodiment, the atomic percentage of aluminum (Al) in each second superlattice layer 106B in the first superlattice stack 106-1 can be different, that is, the atomic percentage of gallium (Ga) in each second superlattice layer 106B can be different. For example, the atomic percentage of aluminum (Al) in each second superlattice layer 106B can change with each layer and decrease from the lower layer to the upper layer to reduce the stress of the first superlattice stack 106-1. In addition, according to an embodiment, a dopant can be doped into the first superlattice layer 106A and the second superlattice layer 106B of the first superlattice stack 106-1, and the dopant can be carbon or iron, thereby increasing the resistivity of the first superlattice stack 106-1.

[0063] In addition, according to an embodiment of the present invention, as Figure 1 shown, the superlattice structure 106 may include a second superlattice stack 106-2 disposed below the first superlattice stack 106-1. Similar to Figure 2 the first superlattice stack 106-1 shown, the second superlattice stack 106-2 may be composed of a plurality of pairs of stacked third superlattice layers and fourth superlattice layers, where the third superlattice layer has tensile stress and the fourth superlattice layer has compressive stress, and the fourth superlattice layer is stacked on the third superlattice layer. By adjusting the thickness of each layer of the third superlattice layer and the fourth superlattice layer, unpaired 2-DEG layers and 2-DHG layers can be prevented from generating in the second superlattice stack 106-2. In addition, in an embodiment, the composition of the third superlattice layer is, for example, aluminum nitride (AlN), and the composition of the fourth superlattice layer is, for example, aluminum gallium nitride (Al w Ga (1-w)N, where 0.1 < w < 0.5), and the average atomic concentration of aluminum (Al) in the second superlattice stack 106-2 is higher than the average atomic concentration of aluminum (Al) in the first superlattice stack 106-1. In one embodiment, the atomic percentage of aluminum (Al) in each fourth superlattice layer can be different, that is, the atomic percentage of gallium (Ga) in each fourth superlattice layer can be different. For example, the atomic percentage of aluminum (Al) in each fourth superlattice layer can vary with each layer and decrease from the lower layer to the upper layer to reduce the stress of the second superlattice stack 106-2. In addition, according to one embodiment, a dopant can be doped in the third and fourth superlattice layers of the second superlattice stack 106-2, and the dopant can be carbon or iron, thereby increasing the resistance of the second superlattice stack 106-2. According to one embodiment, the average atomic concentration of the aforementioned same group III element such as aluminum (Al) in the composition grading layer 110 is higher than the average atomic concentration of this same group III element such as aluminum (Al) in these fourth superlattice layers.

[0064] In addition, according to an embodiment of the present invention, the average atomic concentration of the aforementioned same group III element such as aluminum (Al) in the composition grading layer 110 is lower than the average atomic concentration of this same group III element such as aluminum (Al) in the overall superlattice structure 106. According to one embodiment, the thickness of the tensile stress layer 108 is greater than the thickness of each superlattice layer in the superlattice structure 106, for example, greater than the thickness of the first superlattice layer 106A and the second superlattice layer 106B of the first superlattice stack 106-1, and also greater than the thickness of the third superlattice layer and the third superlattice layer of the second superlattice stack 106-2.

[0065] According to an embodiment of the present invention, the composition of the electrical isolation layer 112 can be a doped or undoped binary III-V semiconductor, such as carbon-doped gallium nitride (C-GaN), and the concentration of the carbon dopant in the electrical isolation layer 112 gradually increases in the direction from the composition grading layer 110 to the channel layer 114. That is, in the depth direction, the concentration of the carbon dopant in the electrical isolation layer 112 increases from bottom to top to prevent carbon accumulation at the interface between the electrical isolation layer 112 and the composition grading layer 110, thereby making the resistance of the surface of the electrical isolation layer 112 closer to the channel layer 114 higher to provide better electrical isolation.

[0066] Figure 3 It is a concentration curve showing the change of the atomic percentage of the same group III element such as aluminum (Al) in the composition grading layer, the tensile stress layer, and the uppermost second superlattice layer of a high electron mobility transistor (HEMT) shown according to an embodiment of the present invention with different depth positions. Figure 3The horizontal axis represents the depth position of the components of the gradient layer 110, the tensile stress layer 108, and the uppermost second superlattice layer 106B; the vertical axis represents the atomic percentage of aluminum (Al). According to one embodiment, such as... Figure 3 As shown, the aluminum (Al) atomic percentage of the uppermost second superlattice layer 106B is approximately value C3, the aluminum (Al) atomic percentage of the tensile stress layer 108 is the highest at value C2, and the aluminum (Al) atomic percentage of the gradient layer 110 decreases from bottom to top in the depth direction, gradually decreasing from value C1 to near 0, where value C3 is approximately 10%, value C2 is approximately 50%, and value C1 is approximately 30%. In this embodiment, the concentration change curve of the aluminum (Al) atomic percentage of the gradient layer 110 can be a straight line 201. In one embodiment, the aluminum (Al) atomic percentage of the gradient layer 110 can also gradually decrease to near 0 from other values ​​higher or lower than value C1. According to one embodiment of the present invention, the average atomic concentration of aluminum (Al) in the tensile stress layer 108 is higher than the average atomic concentration of aluminum (Al) in the gradient layer 110, and the average atomic concentration of aluminum (Al) in the gradient layer 110 is higher than the average atomic concentration of aluminum (Al) in the uppermost second superlattice layer 106B.

[0067] Figure 4 , Figure 5 and Figure 6 These are concentration curves showing the atomic percentage of the same Group III element, such as aluminum (Al), in the compositional gradient layer, tensile stress layer, and the uppermost second superlattice layer of a HEMT, as illustrated in some embodiments of the present invention, varying with different depth positions. Figure 4 Implementation examples and Figure 3 The difference lies in the fact that the concentration change curve of the percentage of aluminum (Al) atoms in the gradient layer 110 can be an arc 202. Figure 5 Implementation examples and Figure 3 The difference lies in the fact that the concentration change curve of the percentage of aluminum (Al) atoms in the gradient layer 110 can be a step-like curve 203. Figure 6 Implementation examples and Figure 3 The difference lies in the fact that the concentration change curve of the percentage of aluminum (Al) atoms constituting the gradient layer 110 can be a wavy curve 204. Other similar parts can be referred to the foregoing. Figure 3 Explanation.

[0068] Figure 7 , Figure 8 , Figure 9 and Figure 10 These are schematic cross-sectional views illustrating various intermediate stages in the fabrication of a high electron mobility transistor 100 according to embodiments of the present invention. Figure 7As shown, a substrate 102 is provided, on which a stacked layer comprising a nucleation layer 104, a superlattice structure 106, a tensile stress layer 108, a compositional gradient layer 110, an electrical isolation layer 112, a channel layer 114, a barrier layer 116, and a doped semiconductor capping layer 118 is sequentially formed. In one embodiment, the superlattice structure 106 may be composed of a first superlattice stack 106-1 disposed on a second superlattice stack 106-2. In another embodiment, the superlattice structure 106 may be composed of the first superlattice stack 106-1.

[0069] According to one embodiment, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, but is not limited thereto. In another embodiment, the substrate 102 further comprises one or more insulating material layers and / or other suitable material layers (e.g., semiconductor layers) and a core layer. The insulating material layers may be oxides, nitrides, oxynitrides, or other suitable insulating materials. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum gallium nitride (AlGaN), zinc oxide (ZnO), or gallium oxide (Ga2O3), or other suitable ceramic materials. In one embodiment, the single or multiple insulating material layers and / or other suitable material layers cover the core layer.

[0070] The nucleation layer 104 may optionally be disposed on the substrate 102, having fewer lattice defects, thereby improving the epitaxial quality of the superlattice structure 106 disposed on the nucleation layer 104. In one embodiment, the nucleation layer 104 may comprise a stack of nitride (AlN) layers, for example, a first nitride layer and a second nitride layer. According to one embodiment of the present invention, the first nitride layer may be, for example, a low-temperature aluminum nitride layer (LT-AlN), which can be formed via metal-organic chemical vapor deposition (MOCVD) at an ambient temperature of 800°C-1100°C; the second nitride layer may be, for example, a high-temperature aluminum nitride layer (HT-AlN), which can be formed via metal-organic chemical vapor deposition at an ambient temperature of 1100°C-1400°C, but is not limited thereto.

[0071] A superlattice structure 106 is disposed on a substrate 102. According to one embodiment of the present invention, a second superlattice stack 106-2 of the superlattice structure 106 may be selectively disposed on a nucleation layer 104. Then, a first superlattice stack 106-1 is disposed on the second superlattice stack 106-2. Alternatively, when the second superlattice stack 106-2 is omitted, the first superlattice stack 106-1 may be disposed on the nucleation layer 104. The superlattice structure 106 can be used to reduce the degree of lattice mismatch between the substrate 102 and the semiconductor layer disposed on the superlattice structure 106, and to reduce the stress caused by the lattice mismatch. According to one embodiment of the present invention, as... Figure 2 As shown, the first superlattice stack 106-1 may include a first superlattice layer 106A and a second superlattice layer 106B. Similarly, the second superlattice stack 106-2 may include multiple pairs of superlattice layers, such as a third superlattice layer and a fourth superlattice layer. Depending on the requirements, the first superlattice stack 106-1 and the second superlattice stack 106-2 may each be a structure composed of at least two types of III-V semiconductor layers stacked in a periodic alternation, for example, each including a plurality of pairs of AlN thin layers / AlGaN thin layers or a plurality of pairs of AlN thin layers / GaN thin layers, or each including a structure composed of multiple III-V semiconductor layers stacked with gradually varying composition ratios, such as aluminum gallium nitride (Al₂O₃). a Ga 1-a The aluminum composition ratio in (N, 0.15≦a≦0.9) can gradually decrease from the lower superlattice layer to the upper superlattice layer, but is not limited thereto. According to one embodiment, the superlattice structure 106 can be formed using an atomic layer deposition (ALD) process. By adjusting the source gas ratio of each atomic layer being deposited, for example, adjusting the ratio of aluminum (Al), nitrogen (N), and gallium (Ga) source gases, multiple superlattice layers with various composition ratios can be deposited.

[0072] According to one embodiment of the present invention, the tensile stress layer 108 may be selectively disposed on the superlattice structure 106, and the compositional gradient layer 110 may be formed on the tensile stress layer 108. The composition of the tensile stress layer 108 and the compositional gradient layer 110 is as described above and will not be repeated here. According to one embodiment, the compositional gradient layer 110 and the tensile stress layer 108 may be formed using an atomic layer deposition (ALD) process. By adjusting the proportion of source gases for each atomic layer to be deposited, for example, adjusting the proportion of aluminum (Al), nitrogen (N), and gallium (Ga) source gases, multiple atomic layers with gradually varying compositional proportions can be deposited to form, for example, a compositional gradient layer 110 with gradually varying aluminum (Al) atomic percentage or atomic concentration. According to one embodiment, the thickness of the tensile stress layer 108 may be 2 nm to 20 nm, or may be 0.2% to 2% of the thickness of the electrical isolation layer 112; the thickness of the compositional gradient layer 110 may be 5 nm to 50 nm, or may be 0.5% to 5% of the thickness of the electrical isolation layer 112.

[0073] According to one embodiment of the present invention, an electrical isolation layer 112 is disposed on the gradient layer 110. The electrical isolation layer 112 has a higher resistivity than other layers, thus preventing leakage current between the semiconductor layer disposed on the electrical isolation layer 112 and the substrate 102. A channel layer 114 may be disposed on the electrical isolation layer 112, and a barrier layer 116 may be disposed on the channel layer 114. The composition of the channel layer 114 and the barrier layer 116 is as described above and will not be repeated here. A doped semiconductor capping layer 118 may be formed on the barrier layer 116 to achieve the normally-off state of HEMT by depleting the two-dimensional electron gas (2-DEG) region. The doped semiconductor capping layer 118 may be one or more doped III-V semiconductor layers, such as GaN doped with p-type or n-type dopant. Its composition may be GaN, AlGaN, InGaN, or InAlGaN, and its dopant may be C, Fe, Mg, or Zn, but is not limited thereto. According to one embodiment, the doped semiconductor capping layer 118 may be a p-type GaN layer.

[0074] Next, according to an embodiment of the present invention, such as Figure 8As shown, a patterned doped semiconductor capping layer 118 is formed on the barrier layer 116. The patterned doped semiconductor capping layer 118 can be formed using photolithography and etching processes. Then, an isolation region 120 is formed around the HEMT to isolate adjacent HEMTs. According to one embodiment, the isolation region 120 extends downward through the barrier layer 116 into the channel layer 114 and is spaced apart from the electrical isolation layer 112. In one embodiment, the isolation region 120 can be a shallow trench isolation (STI), which can be formed by etching trenches in the barrier layer 116 and the channel layer 114, filling the trenches with one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a combination thereof, and forming the isolation region 120 by a chemical mechanical polishing (CMP) process. In another embodiment, the isolation region 120 can be formed by ion implantation, using a hard shield to cover the area outside the intended isolation region 120, and implanting a dopant into the barrier layer 116 and the channel layer 114 to form the isolation region 120, such as helium or carbon.

[0075] Next, according to an embodiment of the present invention, such as Figure 9 As shown, a first passivation layer 128-1 is formed on the isolation region 120 and the barrier layer 116, and a source electrode 122 and a drain electrode 124 are formed on both sides of the doped semiconductor capping layer 118. In one embodiment, the source electrode 122 and the drain electrode 124 extend downward into the channel layer 114 through the first passivation layer 128-1 and the barrier layer 116, such that the bottom of the source electrode 122 and the drain electrode 124 is higher than the bottom of the isolation region 120 and lower than the top surface of the channel layer 114. In another embodiment, the source electrode 122 and the drain electrode 124 extend downward into the barrier layer 116 through the first passivation layer 128-1, such that the bottom of the source electrode 122 and the drain electrode 124 is higher than the bottom of the isolation region 120 and lower than the top surface of the barrier layer 116.

[0076] According to one embodiment, a first passivation layer 128-1 can be deposited first to cover the isolation region 120, the barrier layer 116, and the doped semiconductor capping layer 118. Then, contact holes for source electrodes 122 and drain electrodes 124, located on both sides of the doped semiconductor capping layer 118, are formed in the first passivation layer 128-1, the barrier layer 116, and the channel layer 114. Then, a conductive material layer is deposited in the contact holes and on the first passivation layer 128-1. In one embodiment, the source electrodes 122 and drain electrodes 124 can be formed via a chemical mechanical polishing process, exposing the top surface of the doped semiconductor capping layer 118, wherein the top surfaces of the source electrodes 122 and drain electrodes 124 can be flush with the top surface of the doped semiconductor capping layer 118. In another embodiment, after depositing the conductive material layer, an etching process can be used to remove the conductive material layer outside the contact hole to form the source electrode 122 and the drain electrode 124, and the top surface of the doped semiconductor capping layer 118 can still be covered by the first passivation layer 128-1.

[0077] According to one embodiment, the source electrode 122 and the drain electrode 124 can be a single-layer or multi-layer structure, and their composition may include ohmic contact metal. Here, ohmic contact metal refers to a metal, alloy, or stacked layer thereof that can form an ohmic contact with a semiconductor layer (e.g., channel layer 114), such as Ti, Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, Ti / Al / Ni / Au, or Ti / Al / Mo / Au, but is not limited thereto.

[0078] Next, according to an embodiment of the present invention, such as Figure 10 As shown, a second passivation layer 128-2 is formed to cover the first passivation layer 128-1, the doped semiconductor capping layer 118, the source electrode 122, and the drain electrode 124. The first passivation layer 128-1 and the second passivation layer 128-2 can be collectively referred to as passivation layer 128. Then, a contact hole 125 for the gate electrode 126 is formed in the second passivation layer 128-2 to expose the top surface of the doped semiconductor capping layer 118. According to an embodiment of the present invention, when an etch stop layer (not shown) is provided on the top surface of the doped semiconductor capping layer 118, the etch stop layer can be exposed through the contact hole 125. The etch stop layer can be used to protect the doped semiconductor capping layer 118 to prevent the doped semiconductor capping layer 118 from directly contacting the etchant used when forming the contact hole 125. Subsequently, a conductive material layer is deposited in the contact hole 125 and on the second passivation layer 128-2. After patterning the conductive material layer through photolithography and etching processes, a structure is formed as shown. Figure 1 The gate electrode 126 is shown. According to one embodiment, the top surface of the gate electrode 126 is higher than the top surface of the passivation layer 128. In another embodiment, a portion of the gate electrode 126 may also extend to the top surface of the passivation layer 128.

[0079] According to one embodiment, the gate electrode 126 can be a single-layer or multi-layer structure, such as a bilayer structure comprising a first conductive layer and a second conductive layer. The first conductive layer can directly contact the doped semiconductor capping layer 118, and its composition includes a Schottky contact metal. The Schottky contact metal refers to a metal, alloy, or stacked layer thereof that can form a Schottky contact with the semiconductor layer (e.g., the doped semiconductor capping layer 118), such as TiN, W, Pt, Ni, or Ni, but is not limited thereto. The composition of the second conductive layer can include Ti, Al, Au, Mo, but is not limited thereto. According to one embodiment, the first conductive layer may further comprise a metal nitride of a refractory metal, and the refractory metal can be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, uranium, rhenium, ruthenium, osmium, rhodium, and iridium.

[0080] According to one embodiment, the materials of the first passivation layer 128-1 and the second passivation layer 128-2 comprise aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxide (SiO2), and the materials of the first passivation layer 128-1 and the second passivation layer 128-2 can be the same. In another embodiment, the materials of the first passivation layer 128-1 and the second passivation layer 128-2 can be different.

[0081] One objective of the embodiments of the present invention is to avoid the creation of current transport paths between the superlattice structure and the electrical isolation layer. Another objective of the embodiments of the present invention is to avoid mutual interference of leakage current between adjacent HEMTs. This not only improves the accuracy of pre-packaging die probing (CP) testing and enables a more accurate determination of whether the HEMT meets electrical specifications, but also maintains the 2-DEG performance of the HEMT, thus improving the electrical performance of the HEMT.

[0082] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure, characterized by, Comprising: a superlattice structure disposed on a substrate; an electrically isolating layer disposed on the superlattice structure, wherein the superlattice structure comprises a plurality of pairs of a first superlattice layer and a second superlattice layer stacked together, the first superlattice layer having tensile stress, the second superlattice layer having compressive stress, and in the pairs, the second superlattice layer is stacked on the first superlattice layer; a channel layer disposed on the electrically isolating layer; a compositionally graded layer disposed between the electrically isolating layer and the superlattice structure, wherein the compositionally graded layer has a thickness of 0.5% to 5% of the thickness of the electrically isolating layer, the compositionally graded layer and the superlattice structure comprise a same group III element, and the atomic percentage of the same group III element in the compositionally graded layer gradually decreases from the superlattice structure to the electrically isolating layer; and a tensile stress layer disposed between the superlattice structure and the compositionally graded layer, wherein the tensile stress layer has a thickness of 0.2% to 2% of the thickness of the electrically isolating layer.

2. The semiconductor structure of claim 1, wherein, The tensile stress layer comprises the same group III element.

3. The semiconductor structure of claim 2, wherein, The average atomic concentration of the same group III element in the tensile stress layer is higher than the average atomic concentration of the same group III element in the compositionally graded layer.

4. The semiconductor structure of claim 2, wherein, The composition of the compositionally graded layer includes aluminum gallium nitride Al x Ga (1-x) N, where 0.1 < x < 0.5, and the value of x gradually decreases in the direction from the superlattice structure to the electrically isolating layer, the composition of the tensile stress layer includes aluminum nitride.

5. The semiconductor structure of claim 4, wherein, The electrically isolating layer comprises carbon-doped gallium nitride.

6. The semiconductor structure of claim 1, wherein, The compositionally graded layer comprises a dopant, and the dopant comprises carbon or iron.

7. The semiconductor structure of claim 1, wherein, The electrically isolating layer comprises another group III element, and the compositionally graded layer comprises the another group III element, the atomic percentage of the another group III element in the compositionally graded layer gradually increases from the superlattice structure to the electrically isolating layer.

8. The semiconductor structure of claim 1, wherein, The electrically isolating layer comprises a carbon dopant, and the concentration of the carbon dopant in the electrically isolating layer gradually increases from the compositionally graded layer to the channel layer.

9. The semiconductor structure of claim 1, wherein, The average atomic concentration of the same group III element in the compositionally graded layer is lower than the average atomic concentration of the same group III element in the superlattice structure.

10. The semiconductor structure of claim 1, wherein, The average atomic concentration of the same group III element in the compositionally graded layer is higher than the average atomic concentration of the same group III element in the second superlattice layer.

11. A high electron mobility transistor, characterized by, Comprising: a semiconductor structure as claimed in claim 1; a barrier layer disposed on the channel layer; a doped semiconductor cap layer disposed on the barrier layer; a gate electrode disposed on the doped semiconductor cap layer; and a source electrode and a drain electrode disposed on two sides of the gate electrode, respectively.

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