Shutdown time control circuit for a DC-DC converter, and a DC-DC converter

Abstract

Embodiments of the present disclosure provide a turn-off time control circuit for a DC-DC converter, which includes: an error voltage scaling circuit, a selection circuit, an output voltage simulation circuit, a reference voltage generation circuit, and a clock signal generation circuit. The error voltage scaling circuit scales the error voltage to generate a scaled signal. The selection circuit generates first and second selection signals according to the feedback voltage and the second reference voltage and provides the scaled signal to the first node when the first selection signal is at an effective level. The output voltage simulation circuit generates and provides an analog output voltage to the first node when the second selection signal is at an effective level. The reference voltage generation circuit generates a third reference voltage according to the voltage of the first node and the input voltage. The clock signal generation circuit generates a clock signal according to the third reference voltage, the input voltage, and the voltage of the second pole of the power transistor. The clock signal is used to control the turn-off time of the power transistor. The on-time of the power transistor is controlled by the error voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and in particular, to a turn-off time control circuit for a DC-DC converter and a DC-DC converter. Background Art

[0002] DC-DC (direct current - direct current) converters are often used to convert DC voltages in various electronic devices. DC-DC converters include buck converters and boost converters. A buck converter can convert a higher DC voltage into a lower DC voltage. A boost converter can convert a lower DC voltage into a higher DC voltage. In a buck converter, a first pole (drain) of a power transistor (upper transistor) is coupled to an input voltage terminal. A second pole (source) of the power transistor is coupled to one end of an inductor. A control pole (gate) of the power transistor is provided with a power transistor conduction control signal. During a period when the power transistor conduction control signal is at an effective level, the power transistor conducts. During a period when the power transistor conduction control signal is at an invalid level, the power transistor turns off. The power transistor conduction control signal can be controlled by a pulse width modulation (PWM) signal. The duty cycle of the PWM signal can be controlled by a conduction time control circuit and a turn-off time control circuit. Summary of the Invention

[0003] Embodiments described herein provide a turn-off time control circuit for a DC-DC converter and a DC-DC converter.

[0004] According to a first aspect of the present disclosure, a turn-off time control circuit for a DC-DC converter is provided. Among them, the first pole of the power transistor of the DC-DC converter is coupled to the input voltage terminal. The second pole of the power transistor is coupled to the first end of the inductor. The turn-off time control circuit includes: an error voltage scaling circuit, a selection circuit, an output voltage simulation circuit, a reference voltage generation circuit, and a clock signal generation circuit. Among them, the error voltage scaling circuit is configured to scale the error voltage between the feedback voltage of the DC-DC converter and the first reference voltage to generate a scaling signal. The selection circuit is configured to: generate a first selection signal and a second selection signal according to the feedback voltage and the second reference voltage, and provide the scaling signal to the first node when the first selection signal is at an effective level. Among them, the first selection signal and the second selection signal are inverse signals to each other. The output voltage simulation circuit is configured to: generate an analog output voltage according to the input voltage from the input voltage terminal and the voltage of the second pole of the power transistor when the second selection signal is at an effective level, and provide the analog output voltage to the first node. Among them, the analog output voltage is equal to the output voltage of the DC-DC converter. The reference voltage generation circuit is configured to generate a third reference voltage according to the voltage of the first node and the input voltage, and provide the third reference voltage to the clock signal generation circuit via the second node. The clock signal generation circuit is configured to generate a clock signal according to the third reference voltage, the input voltage, and the voltage of the second pole of the power transistor. Among them, the clock signal is used to control the turn-off time of the power transistor. The turn-on time of the power transistor is controlled by the error voltage.

[0005] In some embodiments of the present disclosure, the second reference voltage is less than the first reference voltage.

[0006] In some embodiments of the present disclosure, the error voltage scaling circuit includes: a first amplifier. Among them, the first input terminal of the first amplifier is provided with the error voltage. The scaling signal is output from the first output terminal of the first amplifier. The second input terminal and the second output terminal of the first amplifier are coupled to the second voltage terminal.

[0007] In some embodiments of the present disclosure, the output voltage analog circuit includes: a first voltage-controlled switch to a third voltage-controlled switch, a first inverter, a first resistor, and a first capacitor. Wherein, the controlled terminal of the first voltage-controlled switch is coupled to the second pole of the power transistor. The first terminal of the first voltage-controlled switch is coupled to the input voltage terminal. The second terminal of the first voltage-controlled switch is coupled to the first terminal of the second voltage-controlled switch and the first terminal of the third voltage-controlled switch. The input terminal of the first inverter is coupled to the second pole of the power transistor. The output terminal of the first inverter is coupled to the controlled terminal of the second voltage-controlled switch. The second terminal of the second voltage-controlled switch is coupled to the second voltage terminal. The controlled terminal of the third voltage-controlled switch is provided with a second selection signal. The second terminal of the third voltage-controlled switch is coupled to the first terminal of the first resistor. The second terminal of the first resistor is coupled to the first node and the first terminal of the first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal.

[0008] In some embodiments of the present disclosure, the capacitance value of the first capacitor is equal to the capacitance value of the output capacitor of the DC-DC converter.

[0009] In some embodiments of the present disclosure, the selection circuit includes: a first voltage comparator, a monostable flip-flop, a second inverter, and a fourth voltage-controlled switch. Wherein, the first input terminal of the first voltage comparator is provided with a feedback voltage. The second input terminal of the first voltage comparator is provided with a second reference voltage. The output terminal of the first voltage comparator is coupled to the input terminal of the monostable flip-flop. The output terminal of the monostable flip-flop is coupled to the input terminal of the second inverter and the controlled terminal of the fourth voltage-controlled switch. The first terminal of the fourth voltage-controlled switch is provided with a scaling signal. The second terminal of the fourth voltage-controlled switch is coupled to the first node. Wherein, the second selection signal is output from the output terminal of the second inverter.

[0010] In some embodiments of the present disclosure, the reference voltage generation circuit includes: a first voltage-controlled current source, a second voltage-controlled current source, a second resistor, and a second capacitor. Wherein, the first input terminal of the first voltage-controlled current source is coupled to the first node. The second input terminal of the first voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the first voltage-controlled current source is coupled to the second output terminal of the second voltage-controlled current source, the first terminal of the second resistor, the first terminal of the second capacitor, and the second node. The second output terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the second terminal of the second resistor, and the second terminal of the second capacitor. The first input terminal of the second voltage-controlled current source is coupled to the input voltage terminal. The second input terminal of the second voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the second voltage-controlled current source is coupled to the first voltage terminal.

[0011] In some embodiments of the present disclosure, the clock signal generation circuit includes: a third voltage-controlled current source, a fifth voltage-controlled switch, a third capacitor, and a second voltage comparator. Among them, the first input terminal of the third voltage-controlled current source is coupled to the input voltage terminal. The second input terminal of the third voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the third voltage-controlled current source is coupled to the first voltage terminal. The second output terminal of the third voltage-controlled current source is coupled to the first terminal of the fifth voltage-controlled switch, the first terminal of the third capacitor, and the first input terminal of the second voltage comparator. The controlled terminal of the fifth voltage-controlled switch is coupled to the second pole of the power transistor. The second terminal of the fifth voltage-controlled switch is coupled to the second voltage terminal. The second terminal of the third capacitor is coupled to the second voltage terminal. The second input terminal of the second voltage comparator is coupled to the second node, and the clock signal is output from the output terminal of the second voltage comparator.

[0012] According to a second aspect of the present disclosure, a turn-off time control circuit for a DC-DC converter is provided. Among them, the first pole of the power transistor of the DC-DC converter is coupled to the input voltage terminal. The second pole of the power transistor is coupled to the first end of the inductor. The turn-off time control circuit includes: a first amplifier, a first voltage-controlled switch to a fifth voltage-controlled switch, a first inverter, a second inverter, a first resistor, a second resistor, a first capacitor to a third capacitor, a first voltage comparator, a second voltage comparator, a monostable flip-flop, and a first voltage-controlled current source to a third voltage-controlled current source. Among them, an error voltage between the feedback voltage of the DC-DC converter and the first reference voltage is provided to the first input terminal of the first amplifier. The first output terminal of the first amplifier is coupled to the first end of the fourth voltage-controlled switch. The second input terminal and the second output terminal of the first amplifier are coupled to the second voltage terminal. The controlled terminal of the first voltage-controlled switch is coupled to the second pole of the power transistor. The first end of the first voltage-controlled switch is coupled to the input voltage terminal. The second end of the first voltage-controlled switch is coupled to the first end of the second voltage-controlled switch and the first end of the third voltage-controlled switch. The input terminal of the first inverter is coupled to the second pole of the power transistor. The output terminal of the first inverter is coupled to the controlled terminal of the second voltage-controlled switch. The second end of the second voltage-controlled switch is coupled to the second voltage terminal. The controlled terminal of the third voltage-controlled switch is coupled to the output terminal of the second inverter. The second end of the third voltage-controlled switch is coupled to the first end of the first resistor. The second end of the first resistor is coupled to the first input terminal of the first voltage-controlled current source, the first end of the first capacitor, and the second end of the fourth voltage-controlled switch. The second end of the first capacitor is coupled to the second voltage terminal. The feedback voltage is provided to the first input terminal of the first voltage comparator. The second reference voltage is provided to the second input terminal of the first voltage comparator. The output terminal of the first voltage comparator is coupled to the input terminal of the monostable flip-flop. The output terminal of the monostable flip-flop is coupled to the input terminal of the second inverter and the controlled terminal of the fourth voltage-controlled switch. The second input terminal of the first voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the first voltage-controlled current source is coupled to the second output terminal of the second voltage-controlled current source, the first end of the second resistor, the first end of the second capacitor, and the second input terminal of the second voltage comparator. The second output terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the second end of the second resistor, and the second end of the second capacitor. The first input terminal of the second voltage-controlled current source is coupled to the input voltage terminal. The second input terminal of the second voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the second voltage-controlled current source is coupled to the first voltage terminal. The first input terminal of the third voltage-controlled current source is coupled to the input voltage terminal. The second input terminal of the third voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the third voltage-controlled current source is coupled to the first voltage terminal. The second output terminal of the third voltage-controlled current source is coupled to the first end of the fifth voltage-controlled switch, the first end of the third capacitor, and the first input terminal of the second voltage comparator. The controlled terminal of the fifth voltage-controlled switch is coupled to the second pole of the power transistor. The second end of the fifth voltage-controlled switch is coupled to the second voltage terminal. The second end of the third capacitor is coupled to the second voltage terminal. Among them, a clock signal is output from the output terminal of the second voltage comparator.The clock signal is used to control the turn-off time of the power transistor. The turn-on time of the power transistor is controlled by the error voltage.

[0013] According to a third aspect of the present disclosure, there is provided a DC-DC converter. The DC-DC converter includes the turn-off time control circuit according to the first aspect or the second aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To illustrate the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0015] Figure 1 is an exemplary circuit diagram of a part of a DC-DC converter;

[0016] Figure 2 is Figure 1 a timing diagram of some signals in the DC-DC converter shown in steady state;

[0017] Figure 3 is Figure 1 a timing diagram of some signals in the DC-DC converter shown when the transient load current increases;

[0018] Figure 4 is Figure 1 a timing diagram of some other signals in the DC-DC converter shown when the transient load current increases;

[0019] Figure 5 is an exemplary circuit diagram of a part of a DC-DC converter according to an embodiment of the present disclosure;

[0020] Figure 6 is a schematic block diagram of a turn-off time control circuit according to an embodiment of the present disclosure; and

[0021] Figure 7 is an exemplary circuit diagram of a turn-off time control circuit according to an embodiment of the present disclosure.

[0022] In the drawings, marks with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetric, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are respectively referred to as the first electrode and the second electrode. The transistors used in the embodiments of the present disclosure are mainly switching transistors. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] PCM (peak current control) is a commonly used fixed-frequency PWM control method in DC-DC converters. This control method requires a fixed-frequency clock signal as the start signal of PWM. When the duty cycle of PWM is greater than 50%, this control method will have the problem of subharmonic oscillation, and a harmonic compensation circuit needs to be added to correct the problem of subharmonic oscillation. The constant off time (CFT) control method does not require the use of a fixed-frequency clock signal and at the same time avoids the problem of subharmonic oscillation in the PCM method. However, when the PWM signal has a small duty cycle, the dynamic response of the CFT control method is not ideal due to the too long low-level time of the PWM signal.

[0027] The CFT control strategy can save the crystal oscillator and harmonic compensation circuit inside the DC-DC converter, which is beneficial to reducing the manufacturing cost and design difficulty of the DC-DC converter. However, in applications with small duty cycles and high dynamic requirements, the defects of the CFT control method are also very obvious.

[0028] Figure 1 An exemplary circuit diagram of a part of a DC-DC converter 100 adopting a CFT control mode is shown. To avoid obscuring the key points of the present disclosure with unnecessary details, only the turn-off time control circuit, a transconductance operational amplifier 110 (including an error amplifier EA, a resistor Rea, a capacitor Cea, and a capacitor Ce), a current-voltage conversion circuit, a voltage comparator CP, an RS flip-flop, a drive circuit, a power transistor HS, a freewheeling diode LS, an inductor Lx, an output capacitor Cout, and a load resistor RL are shown in Figure 1 .

[0029] In the DC-DC converter 100, the turn-off time control circuit obtains a fixed turn-off time Toff = k×(1 - Vout / Vin) according to the relationship between Vin and Vout. Combining Figure 2 it can be seen that when the fixed turn-off time Toff is reached, the RS flip-flop is triggered, so that the PWM signal flips to a high level. The PWM signal flipping to a high level can make the power transistor conduction control signal HG output by the drive circuit flip to an effective level, so that the power transistor HS conducts. At the same time, the freewheeling diode conduction control signal LG flips to an invalid level, so that the freewheeling diode LS turns off. In this way, the turn-off time control circuit can control the turn-off time of the power transistor HS to be Figure 2 Toff as shown in Figure 2 . The transconductance operational amplifier 110 outputs an error voltage Vc between the feedback voltage FB (a partial voltage of the output voltage Vout) of the DC-DC converter 100 and a first reference voltage Vref1. The inductor current IL flowing through the inductor Lx is supplied to the current-voltage conversion circuit and is thus converted into a voltage signal. By setting the amplitude of the converted voltage signal, when the inductor current IL reaches the peak value, the voltage comparator CP outputs a high-level signal. In this way, the RS flip-flop can be reset, so that the PWM signal flips to a low level. The PWM signal flipping to a low level can make the power transistor conduction control signal HG output by the drive circuit flip to an invalid level, so that the power transistor HS turns off. At the same time, the freewheeling diode conduction control signal LG flips to an effective level, so that the freewheeling diode LS conducts. In this way, the conduction time control circuit composed of the transconductance operational amplifier 110, the current-voltage conversion circuit, and the voltage comparator CP can control the conduction time of the power transistor HS to be

[0030] When operating in a steady state, if the input voltage Vin and the output voltage Vout of the DC-DC converter 100 are fixed and k takes a fixed value, the turn-off time Toff is fixed and the PWM period Ts is fixed. During transient operation, for example, when the load current Iload (the current flowing through the load resistor RL) of the DC-DC converter 100 suddenly increases at this time, the feedback voltage FB drops and the error voltage Vc rises. Refer to Figure 3 It can be seen that in this case, the conduction time Ton becomes longer, while the turn-off time Toff is fixed, so the PWM period Ts increases. Figure 4 It shows that when the load current Iload suddenly increases, the increase in the PWM period Ts will result in a larger drop value Vdrop of the output voltage Vout.

[0031] To address the above problems, embodiments of the present disclosure propose that when the load current suddenly increases, control the turn-off time Toff to decrease as the error voltage Vc rises, thereby increasing the switching frequency during transients and improving Figure 1 the dynamic performance of the DC-DC converter 100 shown.

[0032] Figure 5 It shows an exemplary circuit diagram of a part of the DC-DC converter 500 according to an embodiment of the present disclosure. To avoid obscuring the key points of the present disclosure with unnecessary details, in Figure 5 only the turn-off time control circuit 520, the transconductance operational amplifier 510 (including the error amplifier EA, the resistor Rea, the capacitor Cea, and the capacitor Ce), the current-voltage conversion circuit, the voltage comparator CP, the RS flip-flop, the drive circuit, the power transistor HS, the freewheeling diode LS, the inductor Lx, the output capacitor Cout, and the load resistor RL are shown. The first pole of the power transistor HS is coupled to the input voltage terminal Vin, and the second pole of the power transistor is coupled to the first end (node SW) of the inductor Lx. The second end of the inductor Lx is coupled to the output voltage terminal Vout. The transconductance operational amplifier 510, the current-voltage conversion circuit, and the voltage comparator CP constitute the conduction time control circuit. The conduction time control circuit can control the conduction time Ton of the power transistor HS. The error voltage Vc between the feedback voltage FB (the divided voltage of the output voltage Vout) and the first reference voltage Vref1 is provided to the turn-off time control circuit 520. When the load current Iload suddenly increases, the turn-off time control circuit 520 can control the turn-off time Toff to decrease as the error voltage Vc rises.

[0033] Figure 6 It shows a schematic block diagram of the turn-off time control circuit 620 according to an embodiment of the present disclosure. The turn-off time control circuit 620 may include: an error voltage scaling circuit 621, a selection circuit 622, an output voltage simulation circuit 623, a reference voltage generation circuit 624, and a clock signal generation circuit 625.

[0034] The error voltage scaling circuit 621 can be coupled to Figure 5 the output terminal of the error amplifier EA in. The voltage at the output terminal of the error amplifier EA is equal to the error voltage Vc between the feedback voltage FB of the DC-DC converter and the first reference voltage Vref1. As described above, the on-time of the power transistor is controlled by the error voltage Vc. The error voltage scaling circuit 621 can also be coupled to the selection circuit 622. The error voltage scaling circuit 621 can be configured to: scale the error voltage Vc between the feedback voltage FB of the DC-DC converter and the first reference voltage Vref1 to generate a scaled signal Vc', and provide the scaled signal Vc' to the selection circuit 622. In some embodiments of the present disclosure, the scaled signal Vc' = x × Vc. Wherein, x represents the scaling factor. x can be greater than 1, or equal to or less than 1.

[0035] The selection circuit 622 can be coupled to the error voltage scaling circuit 621 and the output voltage analog circuit 623. The selection circuit 622 can also be coupled to the feedback voltage terminal FB of the DC-DC converter and the second reference voltage terminal Vref2. The selection circuit 622 can be configured to: generate a first selection signal and a second selection signal slt2 according to the feedback voltage FB from the feedback voltage terminal FB and the second reference voltage Vref2 from the second reference voltage terminal Vref2. Wherein, the first selection signal and the second selection signal slt2 are inverse signals to each other. The selection circuit 622 can also be configured to: provide the scaled signal Vc' from the error voltage scaling circuit 621 to the first node N1 when the first selection signal is at an effective level. The selection circuit 622 can also be configured to: provide the second selection signal slt2 to the output voltage analog circuit 623.

[0036] In some embodiments of the present disclosure, the selection circuit 622 can make the second selection signal slt2 at an effective level when the feedback voltage FB is higher than or equal to the second reference voltage Vref2. The selection circuit 622 can make the first selection signal at an effective level when the feedback voltage FB is lower than the second reference voltage Vref2.

[0037] In some embodiments of the present disclosure, the second reference voltage Vref2 is less than the first reference voltage Vref1. In one example, Vref2 = 0.96 × Vref1.

[0038] In some embodiments of the present disclosure, the effective level of the first selection signal is a high level. The effective level of the second selection signal is also a high level.

[0039] The output voltage analog circuit 623 can be coupled to the selection circuit 622 and the reference voltage generation circuit 624. The output voltage analog circuit 623 can also be coupled to the input voltage terminal Vin and the second pole (node SW) of the power transistor. The output voltage analog circuit 623 can receive the second selection signal slt2 from the selection circuit 622. The output voltage analog circuit 623 can be configured to: when the second selection signal slt2 is at an effective level, generate an analog output voltage Vout' based on the input voltage Vin from the input voltage terminal Vin and the voltage of the second pole of the power transistor, and provide the analog output voltage Vout' to the first node N1. Among them, the analog output voltage Vout' is equal to the output voltage Vout of the DC-DC converter.

[0040] The reference voltage generation circuit 624 can be coupled to the selection circuit 622 and the output voltage analog circuit 623 via the first node N1. The reference voltage generation circuit 624 can be coupled to the clock signal generation circuit 625 via the second node N2. The reference voltage generation circuit 624 can also be coupled to the input voltage terminal Vin. The reference voltage generation circuit 624 can be configured to generate a third reference voltage Vref3 based on the voltage of the first node N1 and the input voltage Vin, and provide the third reference voltage Vref3 to the clock signal generation circuit 625 via the second node N2.

[0041] The clock signal generation circuit 625 can be coupled to the reference voltage generation circuit 624 via the second node N2. The clock signal generation circuit 625 can also be coupled to the input voltage terminal Vin and the second pole (node SW) of the power transistor. The clock signal generation circuit 625 can be configured to generate a clock signal CLK based on the third reference voltage Vref3, the input voltage Vin, and the voltage of the second pole of the power transistor. Among them, the clock signal CLK is used to control the turn-off time of the power transistor.

[0042] When the feedback voltage FB is higher than or equal to the second reference voltage Vref2 (when the DC-CD converter is in steady-state operation), the second selection signal slt2 is at an effective level. Therefore, the output voltage analog circuit 623 provides the analog output voltage Vout' to the first node N1. The reference voltage generation circuit 624 can generate a third reference voltage Vref3 based on the analog output voltage Vout' and the input voltage Vin. The clock signal generation circuit 625 can generate a clock signal CLK based on the third reference voltage Vref3, the input voltage Vin, and the voltage of the second pole of the power transistor. When the clock signal CLK flips to a high level, the PWM signal flips to a high level, and the power transistor conducts (at this time, the turn-off stage ends). Therefore, the clock signal CLK can be used to control the turn-off time Toff of the power transistor. In this case, the turn-off time Toff can be made equal to k×(1 - Vout / Vin).

[0043] When the feedback voltage FB is lower than the second reference voltage Vref2 (when the DC-DC converter is in transient operation), the first selection signal is at an active level. Therefore, the error voltage scaling circuit 621 provides the scaled signal Vc' to the first node N1. The reference voltage generation circuit 624 can generate the third reference voltage Vref3 based on the scaled signal Vc' and the input voltage Vin. The clock signal generation circuit 625 can generate the clock signal CLK based on the third reference voltage Vref3, the input voltage Vin, and the voltage of the second pole of the power transistor. As described above, the clock signal CLK is used to control the turn-off time Toff of the power transistor. Since the scaled signal Vc' is x times Vc, in this case, the turn-off time Toff is associated with Vc, so that the turn-off time Toff can be dynamically adjusted.

[0044] Figure 7 FIG. shows an exemplary circuit diagram of the turn-off time control circuit 720 according to an embodiment of the present disclosure. The error voltage scaling circuit 721 may include: a first amplifier Amp1. Wherein, the first input terminal of the first amplifier Amp1 is provided with the error voltage Vc. The scaled signal Vc' is output from the first output terminal of the first amplifier Amp1. The second input terminal and the second output terminal of the first amplifier Amp1 are coupled to the second voltage terminal V2. The amplification factor of the first amplifier Amp1 is x, so the scaled signal Vc' = x × Vc. Wherein, x can be greater than 1, or equal to or less than 1.

[0045] The output voltage simulation circuit 723 may include: a first voltage-controlled switch S1 to a third voltage-controlled switch S3, a first inverter NG1, a first resistor R1, and a first capacitor C1. Wherein, the controlled terminal of the first voltage-controlled switch S1 is coupled to the second pole of the power transistor. The first terminal of the first voltage-controlled switch S1 is coupled to the input voltage terminal Vin. The second terminal of the first voltage-controlled switch S1 is coupled to the first terminal of the second voltage-controlled switch S2 and the first terminal of the third voltage-controlled switch S3. The input terminal of the first inverter NG1 is coupled to the second pole of the power transistor (node SW). The output terminal of the first inverter NG1 is coupled to the controlled terminal of the second voltage-controlled switch S2. The second terminal of the second voltage-controlled switch S2 is coupled to the second voltage terminal V2. The controlled terminal of the third voltage-controlled switch S3 is provided with the second selection signal slt2. The second terminal of the third voltage-controlled switch S3 is coupled to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is coupled to the first node N1 and the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2.

[0046] In some embodiments of the present disclosure, the capacitance value of the first capacitor C1 is equal to Figure 5 the capacitance value of the output capacitor Cout of the DC-DC converter 500 in

[0047] The selection circuit 722 may include: a first voltage comparator Comp1, a monostable flip-flop 7221, a second inverter NG2, and a fourth voltage-controlled switch S4. Among them, the first input terminal of the first voltage comparator Comp1 is provided with a feedback voltage FB. The second input terminal of the first voltage comparator Comp1 may be coupled to a second reference voltage terminal Vref2, so that a second reference voltage Vref2 can be provided. The output terminal of the first voltage comparator Comp1 is coupled to the input terminal of the monostable flip-flop 7221. The output terminal of the monostable flip-flop 7221 is coupled to the input terminal of the second inverter NG2 and the controlled terminal of the fourth voltage-controlled switch S4. The first terminal of the fourth voltage-controlled switch S4 is provided with a scaled signal Vc'. The second terminal of the fourth voltage-controlled switch S4 is coupled to a first node N1. Among them, a first selection signal slt1 is output from the output terminal of the monostable flip-flop 7221. A second selection signal slt2 is output from the output terminal of the second inverter NG2.

[0048] In some embodiments of the present disclosure, the monostable flip-flop 7221 is a rising-edge triggered monostable flip-flop 7221. The effective level of the trigger signal output after the monostable flip-flop 7221 is triggered is a high level. In one example, the effective level of the trigger signal is maintained for at least 2 μs. The monostable flip-flop 7221 can be used to keep the effective level of the first selection signal slt1 maintained for a period of time in the transient state where the feedback voltage FB is lower than the second reference voltage Vref2 so that the fourth voltage-controlled switch S4 has enough time to respond.

[0049] The reference voltage generation circuit 724 may include: a first voltage-controlled current source G1, a second voltage-controlled current source G2, a second resistor R2, and a second capacitor C2. Among them, the first input terminal of the first voltage-controlled current source G1 is coupled to the first node N1. The second input terminal of the first voltage-controlled current source G1 is coupled to a second voltage terminal V2. The first output terminal of the first voltage-controlled current source G1 is coupled to the second output terminal of the second voltage-controlled current source G2, the first terminal of the second resistor R2, the first terminal of the second capacitor C2, and a second node N2. The second output terminal of the first voltage-controlled current source G1 is coupled to the second voltage terminal V2, the second terminal of the second resistor R2, and the second terminal of the second capacitor C2. The first input terminal of the second voltage-controlled current source G2 is coupled to an input voltage terminal Vin. The second input terminal of the second voltage-controlled current source G2 is coupled to the second voltage terminal V2. The first output terminal of the second voltage-controlled current source G2 is coupled to a first voltage terminal V1.

[0050] In some embodiments of the present disclosure, the transconductance of the first voltage-controlled current source G1 is denoted as gm1. The first voltage-controlled current source G1 can convert the voltage V of the first node N1 N1 into a first current (gm1×V N1)。The transconductance of the second voltage-controlled current source G2 is denoted as gm2. The second voltage-controlled current source G2 can convert the input voltage Vin into a second current (gm2×Vin). The difference current between the second current and the first current (gm2×Vin - gm1×V N1 ) can charge the second capacitor C2 to generate a third reference voltage Vref3. Vref3 = (gm2×Vin - gm1×V N1 )×R2. Wherein, R2 represents the resistance value of the second resistor R2.

[0051] The clock signal CLK generation circuit 725 may include: a third voltage-controlled current source G3, a fifth voltage-controlled switch S5, a third capacitor C3, and a second voltage comparator Comp2. Wherein, the first input terminal of the third voltage-controlled current source G3 is coupled to the input voltage terminal. The second input terminal of the third voltage-controlled current source G3 is coupled to the second voltage terminal V2. The first output terminal of the third voltage-controlled current source G3 is coupled to the first voltage terminal V1. The second output terminal of the third voltage-controlled current source G3 is coupled to the first terminal of the fifth voltage-controlled switch S5, the first terminal of the third capacitor C3, and the first input terminal of the second voltage comparator Comp2. The controlled terminal of the fifth voltage-controlled switch S5 is coupled to the second pole of the power transistor. The second terminal of the fifth voltage-controlled switch S5 is coupled to the second voltage terminal V2. The second terminal of the third capacitor C3 is coupled to the second voltage terminal V2. The second input terminal of the second voltage comparator Comp2 is coupled to the second node N2, and the clock signal CLK is output from the output terminal of the second voltage comparator Comp2.

[0052] In some embodiments of the present disclosure, the transconductance of the third voltage-controlled current source G3 is denoted as gm3. The third voltage-controlled current source G3 can convert the input voltage Vin into a third current (gm3×Vin).

[0053] In Figure 7In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the first amplifier Amp1 is the non-inverting input terminal. The second input terminal of the first amplifier Amp1 is the inverting input terminal. The first output terminal of the first amplifier Amp1 is the non-inverting output terminal. The second output terminal of the first amplifier Amp1 is the inverting output terminal. The first input terminal of the first voltage comparator Comp1 is the non-inverting input terminal. The second input terminal of the first voltage comparator Comp1 is the inverting input terminal. The output terminal of the first voltage comparator Comp1 is the inverting output terminal. The first input terminal of the second voltage comparator Comp2 is the non-inverting input terminal. The second input terminal of the second voltage comparator Comp2 is the inverting input terminal. The output terminal of the second voltage comparator Comp2 is the non-inverting output terminal. The first input terminal of the first voltage-controlled current source G1 is the non-inverting input terminal. The second input terminal of the first voltage-controlled current source G1 is the inverting input terminal. The first output terminal of the first voltage-controlled current source G1 is the non-inverting output terminal. The second output terminal of the first voltage-controlled current source G1 is the inverting output terminal. The first input terminal of the second voltage-controlled current source G2 is the non-inverting input terminal. The second input terminal of the second voltage-controlled current source G2 is the inverting input terminal. The first output terminal of the second voltage-controlled current source G2 is the non-inverting output terminal. The second output terminal of the second voltage-controlled current source G2 is the inverting output terminal. The first input terminal of the third voltage-controlled current source G3 is the non-inverting input terminal. The second input terminal of the third voltage-controlled current source G3 is the inverting input terminal. The first output terminal of the third voltage-controlled current source G3 is the non-inverting output terminal. The second output terminal of the third voltage-controlled current source G3 is the inverting output terminal. When the control terminal of any one of the first voltage-controlled switch S1 to the fifth voltage-controlled switch S5 is provided with a high level, the voltage-controlled switch is closed; otherwise, the voltage-controlled switch is open. Those skilled in the art should understand that based on the above inventive concept, the modifications made to the Figure 7 circuit shown should also fall within the protection scope of the present disclosure. Figure 7 The internal structure of each circuit in

[0054] is exemplary, and can also be implemented by other circuit structures. Figure 7 The following takes the example of

[0055] When the feedback voltage FB is higher than or equal to the second reference voltage Vref2 (when the DC-CD converter is in steady-state operation), the first voltage comparator Comp1 outputs a low-level signal. Therefore, the first selection signal slt1 output by the monostable flip-flop 7221 is at a low level. The second selection signal slt2 output by the second inverter NG2 is at a high level. Therefore, the fourth voltage-controlled switch S4 is turned off, and the third voltage-controlled switch S3 is closed. When the voltage at node SW is at a high level, the first voltage-controlled switch S1 is closed, and the second voltage-controlled switch S2 is turned off. The input voltage Vin is supplied to the first resistor R1. When the voltage at node SW is at a low level, the first voltage-controlled switch S1 is turned off, and the second voltage-controlled switch S2 is closed. The voltage at the first end of the first resistor R1 is pulled down to ground. In this way, the output voltage analog circuit 723 can make the analog output voltage Vout' equal to the output voltage Vout of the DC-CD converter. The analog output voltage Vout' is supplied to the first node N1. As described above, the third reference voltage Vref3 generated by the reference voltage generation circuit 724 = (gm2 × Vin - gm1 × V N1 ) × R2. In this case, Vref3 = (gm2 × Vin - gm1 × Vout') × R2 = (gm2 × Vin - gm1 × Vout) × R2. When the voltage at node SW is at a high level, the fifth voltage-controlled switch S5 is closed, and the voltage at the non-inverting input terminal of the second voltage comparator Comp2 is pulled down to ground, causing the clock signal CLK output by the second voltage comparator Comp2 to be at a low level. When the voltage at node SW flips to a low level (the power transistor HS is turned off), the fifth voltage-controlled switch S5 is turned off, and the third current (gm3 × Vin) output by the third voltage-controlled current source G3 starts to charge the third capacitor C3. When the voltage at the first end of the third capacitor C3 is equal to the third reference voltage Vref3, the clock signal CLK output by the second voltage comparator Comp2 flips to a high level, thereby causing the PWM signal to flip to a high level. In this way, the period during which the PWM signal is at a low level is controlled to be a fixed time Toff from when the voltage at node SW is at a low level to when CLK flips to a high level. Toff = C3 × Vref3 / (gm3 × Vin) = C3 × (gm2 × Vin - gm1 × Vout) × R2 / (gm3 × Vin). Where C3 represents the capacitance value of the third capacitor C'3. By setting C3, gm2, gm1, R2, and gm3, Toff = k × (1 - Vout / Vin) can be achieved.

[0056] When the feedback voltage FB is lower than the second reference voltage Vref2 (when the DC-DC converter is in transient operation), the first voltage comparator Comp1 outputs a high-level signal. Therefore, the monostable flip-flop 7221 is triggered at the rising edge of the output signal of the first voltage comparator Comp1, so that the first selection signal slt1 output by the monostable flip-flop 7221 can be maintained at a high level for a period of time (for example, 2 μs). Therefore, the fourth voltage-controlled switch S4 is closed. The second selection signal slt2 output by the second inverter NG2 is at a low level. Therefore, the third voltage-controlled switch S3 is turned off. The scaled signal Vc' (x × Vc) is supplied to the first node N1. As described above, the third reference voltage Vref3 generated by the reference voltage generation circuit 724 = (gm2 × Vin - gm1 × V N1 ) × R2. In this case, Vref3 = (gm2 × Vin - gm1 × x × Vc) × R2. When the voltage at the node SW is at a high level, the fifth voltage-controlled switch S5 is closed, and the voltage at the non-inverting input terminal of the second voltage comparator Comp2 is pulled down to ground, so that the clock signal CLK output by the second voltage comparator Comp2 is at a low level. When the voltage at the node SW flips to a low level (the power transistor HS is turned off), the fifth voltage-controlled switch S5 is turned off, and the third current (gm3 × Vin) output by the third voltage-controlled current source G3 starts to charge the third capacitor C3. When the voltage at the first end of the third capacitor C3 is equal to the third reference voltage Vref3, the clock signal CLK output by the second voltage comparator Comp2 flips to a high level, so that the PWM signal flips to a high level. In this way, the time period during which the PWM signal is at a low level is controlled to be the dynamic time Toff from the time when the voltage at the node SW is at a low level to the time when CLK flips to a high level. Toff = C3 × Vref3 / (gm3 × Vin) = C3 × (gm2 × Vin - gm1 × x × Vc) × R2 / (gm3 × Vin). Where C3 represents the capacitance value of the third capacitor C3. In this way, Toff can change dynamically with the value of Vc. When Vc rises, Toff decreases accordingly, so that the transient switching frequency can be increased and the change value of the output voltage Vout can be reduced.

[0057] In summary, the turn-off time control circuit according to the embodiment of the present disclosure improves the transient switching frequency of the DC-DC converter by associating the turn-off time Toff during transient with the error voltage Vc, so as to reduce the change value of the output voltage Vout, thereby maintaining the stability of the output of the DC-DC converter.

[0058] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when reference is made to the singular, it generally includes the plural of the corresponding term. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" shall be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "exemplary" is used herein, particularly when it is after a list of terms, the "exemplary" is merely illustrative and explanatory and should not be considered exclusive or exhaustive.

[0059] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present application.

[0060] The above has described in detail several embodiments of the present disclosure. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A turn-off time control circuit for a DC-DC converter, wherein, The first pole of the power transistor of the DC-DC converter is coupled to the input voltage terminal, and the second pole of the power transistor is coupled to the first end of the inductor. The turn-off time control circuit includes: an error voltage scaling circuit, a selection circuit, an output voltage simulation circuit, a reference voltage generation circuit, and a clock signal generation circuit. Among them, the error voltage scaling circuit is configured to scale the error voltage between the feedback voltage of the DC-DC converter and the first reference voltage to generate a scaling signal. The selection circuit is configured to: generate a first selection signal and a second selection signal according to the feedback voltage and the second reference voltage, and provide the scaling signal to the first node when the first selection signal is at an effective level, where the first selection signal and the second selection signal are complementary signals; the second reference voltage is less than the first reference voltage, and the selection circuit makes the first selection signal at an effective level when the feedback voltage is lower than the second reference voltage, and makes the second selection signal at an effective level when the feedback voltage is higher than or equal to the second reference voltage. The output voltage simulation circuit is configured to: when the second selection signal is at an effective level, generate an analog output voltage according to the input voltage from the input voltage terminal and the voltage of the second pole of the power transistor, and provide the analog output voltage to the first node, where the analog output voltage is equal to the output voltage of the DC-DC converter. The reference voltage generation circuit is configured to generate a third reference voltage according to the voltage of the first node and the input voltage, and provide the third reference voltage to the clock signal generation circuit via the second node. The clock signal generation circuit is configured to generate a clock signal according to the third reference voltage, the input voltage, and the voltage of the second pole of the power transistor. Among them, the clock signal is used to control the turn-off time of the power transistor, and the turn-on time of the power transistor is controlled by the error voltage.

2. The turn-off time control circuit according to claim 1, wherein, The error voltage scaling circuit includes: a first amplifier. Among them, the first input terminal of the first amplifier is provided with the error voltage, the scaling signal is output from the first output terminal of the first amplifier, and the second input terminal and the second output terminal of the first amplifier are coupled to the second voltage terminal.

3. The turn-off time control circuit according to claim 1, wherein, The output voltage simulation circuit includes: a first voltage-controlled switch to a third voltage-controlled switch, a first inverter, a first resistor, and a first capacitor. Among them, the controlled terminal of the first voltage-controlled switch is coupled to the second pole of the power transistor, the first end of the first voltage-controlled switch is coupled to the input voltage terminal, and the second end of the first voltage-controlled switch is coupled to the first end of the second voltage-controlled switch and the first end of the third voltage-controlled switch. The input terminal of the first inverter is coupled to the second pole of the power transistor, and the output terminal of the first inverter is coupled to the controlled terminal of the second voltage-controlled switch. The second end of the second voltage-controlled switch is coupled to the second voltage terminal. The controlled terminal of the third voltage-controlled switch is supplied with the second selection signal, and the second terminal of the third voltage-controlled switch is coupled to the first terminal of the first resistor; The second terminal of the first resistor is coupled to the first node and the first terminal of the first capacitor; The second terminal of the first capacitor is coupled to the second voltage terminal.

4. The turn-off time control circuit according to claim 3, wherein, The capacitance value of the first capacitor is equal to the capacitance value of the output capacitor of the DC-DC converter.

5. The turn-off time control circuit according to claim 1, wherein, The selection circuit includes: a first voltage comparator, a monostable flip-flop, a second inverter, and a fourth voltage-controlled switch, wherein, the first input terminal of the first voltage comparator is supplied with the feedback voltage, the second input terminal of the first voltage comparator is supplied with the second reference voltage, and the output terminal of the first voltage comparator is coupled to the input terminal of the monostable flip-flop; The output terminal of the monostable flip-flop is coupled to the input terminal of the second inverter and the controlled terminal of the fourth voltage-controlled switch; The first terminal of the fourth voltage-controlled switch is supplied with the scaling signal, and the second terminal of the fourth voltage-controlled switch is coupled to the first node; wherein, the second selection signal is output from the output terminal of the second inverter.

6. The turn-off time control circuit according to claim 1, wherein, The reference voltage generation circuit includes: a first voltage-controlled current source, a second voltage-controlled current source, a second resistor, and a second capacitor, wherein, the first input terminal of the first voltage-controlled current source is coupled to the first node, the second input terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the first voltage-controlled current source is coupled to the second output terminal of the second voltage-controlled current source, the first terminal of the second resistor, the first terminal of the second capacitor, and the second node, and the second output terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the second terminal of the second resistor, and the second terminal of the second capacitor; The first input terminal of the second voltage-controlled current source is coupled to the input voltage terminal, the second input terminal of the second voltage-controlled current source is coupled to the second voltage terminal, and the first output terminal of the second voltage-controlled current source is coupled to the first voltage terminal.

7. The turn-off time control circuit according to claim 1, wherein, The clock signal generation circuit includes: a third voltage-controlled current source, a fifth voltage-controlled switch, a third capacitor, and a second voltage comparator, wherein, the first input terminal of the third voltage-controlled current source is coupled to the input voltage terminal, the second input terminal of the third voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the third voltage-controlled current source is coupled to the first voltage terminal, and the second output terminal of the third voltage-controlled current source is coupled to the first terminal of the fifth voltage-controlled switch, the first terminal of the third capacitor, and the first input terminal of the second voltage comparator; The controlled terminal of the fifth voltage-controlled switch is coupled to the second pole of the power transistor, and the second terminal of the fifth voltage-controlled switch is coupled to the second voltage terminal; The second terminal of the third capacitor is coupled to the second voltage terminal; The second input terminal of the second voltage comparator is coupled to the second node, and the clock signal is output from the output terminal of the second voltage comparator.

8. A turn-off time control circuit for a DC-DC converter, wherein, The first pole of the power transistor of the DC-DC converter is coupled to the input voltage terminal, the second pole of the power transistor is coupled to the first end of the inductor, and the turn-off time control circuit includes: a first amplifier, a first to fifth voltage-controlled switches, a first inverter, a second inverter, a first resistor, a second resistor, a first to third capacitors, a first voltage comparator, a second voltage comparator, a monostable flip-flop, and a first to third voltage-controlled current sources. Wherein, an error voltage between the feedback voltage and the first reference voltage of the DC-DC converter is provided to the first input terminal of the first amplifier, the first output terminal of the first amplifier is coupled to the first end of the fourth voltage-controlled switch, and the second input terminal and the second output terminal of the first amplifier are coupled to the second voltage terminal. The controlled terminal of the first voltage-controlled switch is coupled to the second pole of the power transistor, the first end of the first voltage-controlled switch is coupled to the input voltage terminal, and the second end of the first voltage-controlled switch is coupled to the first ends of the second and third voltage-controlled switches. The input terminal of the first inverter is coupled to the second pole of the power transistor, and the output terminal of the first inverter is coupled to the controlled terminal of the second voltage-controlled switch. The second end of the second voltage-controlled switch is coupled to the second voltage terminal. The controlled terminal of the third voltage-controlled switch is coupled to the output terminal of the second inverter, and the second end of the third voltage-controlled switch is coupled to the first end of the first resistor. The second end of the first resistor is coupled to the first input terminal of the first voltage-controlled current source, the first end of the first capacitor, and the second end of the fourth voltage-controlled switch. The second end of the first capacitor is coupled to the second voltage terminal. The feedback voltage is provided to the first input terminal of the first voltage comparator, the second reference voltage is provided to the second input terminal of the first voltage comparator, and the output terminal of the first voltage comparator is coupled to the input terminal of the monostable flip-flop. The output terminal of the monostable flip-flop is coupled to the input terminal of the second inverter and the controlled terminal of the fourth voltage-controlled switch. The second input terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the first voltage-controlled current source is coupled to the second output terminal of the second voltage-controlled current source, the first end of the second resistor, the first end of the second capacitor, and the second input terminal of the second voltage comparator, and the second output terminal of the first voltage-controlled current source is coupled to the second voltage terminal, the second end of the second resistor, and the second end of the second capacitor. The first input terminal of the second voltage-controlled current source is coupled to the input voltage terminal, the second input terminal of the second voltage-controlled current source is coupled to the second voltage terminal, and the first output terminal of the second voltage-controlled current source is coupled to the first voltage terminal. The first input terminal of the third voltage-controlled current source is coupled to the input voltage terminal, the second input terminal of the third voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the third voltage-controlled current source is coupled to the first voltage terminal, and the second output terminal of the third voltage-controlled current source is coupled to the first terminal of the fifth voltage-controlled switch, the first terminal of the third capacitor, and the first input terminal of the second voltage comparator; The controlled terminal of the fifth voltage-controlled switch is coupled to the second pole of the power transistor, and the second terminal of the fifth voltage-controlled switch is coupled to the second voltage terminal; The second terminal of the third capacitor is coupled to the second voltage terminal; Wherein, a clock signal is output from the output terminal of the second voltage comparator, the clock signal is used to control the turn-off time of the power transistor, and the turn-on time of the power transistor is controlled by the error voltage.

9. A DC-DC converter, comprising: The turn-off time control circuit according to any one of claims 1 to 8.

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