Phase-locked loop and clock synchronization system

Abstract

Phase-locked loops (PLLs) and clock synchronization systems are provided in accordance with various aspects of the present application. The phase-locked loop is implemented with another (second) phase-locked loop in place of the controlled oscillator. When a frequency change of the output clock is needed that is known, in addition to changing the configuration of the phase-locked loop (first phase-locked loop), the configuration of the second phase-locked loop is changed to cause the frequency of the output clock to change rapidly. In various embodiments, the configuration of the second phase-locked loop is changed by changing the divisor of the feedback divider of the second phase-locked loop, the divisor in a pre-divider in the second phase-locked loop, the control voltage of a voltage-controlled oscillator used in the second phase-locked loop, and any other user-controlled point in the second phase-locked loop.

Description

[0001] Cross-references

[0002] This patent application relates to and claims priority to the aforementioned Indian provisional patent application, entitled "Rapid Frequency Change in a Phase-Locked Loop," filed October 18, 2021, and entitled "Rapid Switching of PLL Output Frequency," filed June 14, 2022, and entitled "Rapid Switching of PLL Output Frequency." Technical Field

[0003] The embodiments of the present invention generally relate to phase-locked loops (PLLs), and more specifically to the rapid switching of the output frequency of a PLL. Background Technology

[0004] Phase-locked loops (PLLs) are often used to generate one or more clock signals. A PLL receives an input clock and generates an output clock (clock signal), the frequency of which (output frequency) is typically a desired multiple of the input clock frequency.

[0005] In stable conditions, there are often situations where it's necessary to switch the PLL's output frequency from the current frequency to a higher or lower frequency. There may be a need to achieve this switching quickly. However, PLLs are typically designed with low bandwidth, for example, to reduce or avoid jitter in the output clock.

[0006] Various aspects of this invention are aimed at the rapid switching of the output frequency of a PLL. Summary of the Invention

[0007] An exemplary embodiment of the present invention relates to a phase-locked loop (PLL). This PLL generates an output clock with a frequency locked to an input clock and switches to a different frequency for the output clock after generation, the frequency of which is the product of the input clock's frequency in normal operating mode and a desired divisor. The PLL includes a first phase detector, a first low-pass filter with a first passband, a first oscillator, and a first feedback divider. The first phase detector is coupled to receive a first input clock on an input path and a feedback clock on a feedback path, and generates an error signal characterizing the phase difference between the first input clock and the feedback clock. The first low-pass filter generates a filtered error signal by filtering the error signal. The first oscillator is coupled to generate an output clock based on the filtered error signal, wherein the frequency of the output clock is determined by the strength of the filtered error signal. The first feedback divider divides the output clock by a desired divisor having a first value in normal operating mode. The first phase detector, the first low-pass filter, the first oscillator, and the first feedback divider collectively form a first PLL with a first bandwidth. The first oscillator is implemented as a second phase-locked loop (PLL) with a second bandwidth greater than the first bandwidth. The PLL is configured to change the configuration of the first and second PLLs to generate output clocks with different frequencies, thereby switching to different frequencies of the output clock.

[0008] In some embodiments, the phase-locked loop is configured to change the desired divisor of the first feedback divider to be equal to a second value in order to change the configuration of the first phase-locked loop; and after the configuration of the first and second phase-locked loops is changed, the second phase-locked loop with higher bandwidth quickly generates an output clock with a different frequency, thereby causing the first phase-locked loop to quickly change to a different frequency.

[0009] In some embodiments, the second phase-locked loop (PLL) includes a second phase detector, a second oscillator, and a second feedback divider. The second phase detector receives a second input clock on a corresponding input path and a second feedback clock on a corresponding feedback path. The second phase detector generates a second error signal characterizing a second phase difference between the second input clock and the second feedback clock. The second oscillator generates an output clock based on the second error signal. The second feedback divider divides the output clock by a second divisor to generate the second feedback clock. The PLL is configured to change the second divisor to a new value corresponding to a different frequency to modify the configuration of the second PLL.

[0010] In some embodiments, the second divisor is the sum of the filtered error signal and the third divisor, wherein the value of the third divisor is provided by the user, thereby generating a new value as a sum.

[0011] In some embodiments, the second phase-locked loop (PLL) includes a second prescaler, a second phase detector, a second oscillator, and a second feedback divider. The second prescaler divides a third input clock by the prescaler divisor to generate a second input clock. The second phase detector receives the second input clock on the corresponding input path and the second feedback clock on the second feedback path, and generates a second error signal characterizing a second phase difference between the second input clock and the second feedback clock. The second oscillator generates an output clock based on the second error signal. The second feedback divider divides the output clock by the second divisor to generate a second feedback clock. The PLL is configured to change the prescaler divisor to a new value corresponding to a different frequency to modify the configuration of the second PLL.

[0012] In some embodiments, the phase-locked loop is further configured to force the voltage input to another new value corresponding to a different frequency in order to change the configuration of the second phase-locked loop, wherein the voltage input represents a second error signal.

[0013] Embodiments of the present invention also relate to a clock synchronization system, including a line card and a first timing card. The line card is coupled to receive data packets, and is used to reset the timing of the data packets with reference to a selected clock, and to send the reset timing data packets. The first timing card is used to generate a first clock. The line card includes a phase-locked loop (PLL) coupled to receive the first clock, which is used to generate an output clock with a frequency locked to an input clock based on the first clock, which is the selected clock, and to switch to a different frequency of the output clock after the output clock is generated, the frequency of which is the product of the frequency of the input clock in normal operating mode and a desired divisor. The PLL includes a first phase detector, a first low-pass filter having a first passband, a first oscillator, and a first feedback divider. The first phase detector is coupled to receive a first clock on an input path and a feedback clock on a feedback path, and is used to generate an error signal characterizing the phase difference between the first clock and the feedback clock. The first low-pass filter is used to generate a filtered error signal by filtering the error signal. A first oscillator is coupled to generate an output clock based on a filtered error signal, wherein the frequency of the output clock is determined by the strength of the filtered error signal. A first feedback divider is used to divide the output clock by a desired divisor having a first value in normal operating mode. A first phase detector, a first low-pass filter, a first oscillator, and a first feedback divider work together to form a first phase-locked loop (PLL) with a first bandwidth. The first oscillator is implemented as a second PLL with a second bandwidth greater than the first bandwidth. The PLLs are configured to change the configuration of the first and second PLLs to generate output clocks with different frequencies, thereby switching to different frequencies of the output clock.

[0014] In some embodiments, the phase-locked loop (PLL) is configured to change the desired divisor of the first feedback divider to equal a second value in order to change the configuration of the first PLL. Wherein, after changing the configuration of the first and second PLLs, the second PLL, with its higher bandwidth, rapidly generates an output clock with a different frequency, thereby causing the first PLL to rapidly change to the different frequency.

[0015] In some embodiments, the second phase-locked loop (PLL) includes a second phase detector, a second low-pass filter having a second passband, a second oscillator, and a second feedback divider. The second phase detector receives a second input clock on a corresponding input path and a second feedback clock on a corresponding feedback path, and generates a second error signal characterizing a second phase difference between the second input clock and the second feedback clock. The second low-pass filter generates a filtered second error signal by filtering the second error signal, wherein the second passband is larger than a first passband. The second oscillator generates an output clock based on the filtered second error signal. The second feedback divider divides the output clock by a second divisor to generate a second feedback clock. The PLL is configured to change the second divisor to a new value corresponding to a different frequency to modify the configuration of the second PLL.

[0016] In some embodiments, the second divisor is the sum of the filtered error signal and the third divisor, wherein the value of the third divisor is provided by the user, thereby generating a new value as a sum.

[0017] In some embodiments, the second phase-locked loop (PLL) includes a second prescaler, a second phase detector, a second low-pass filter having a second passband, a second oscillator, and a second feedback divider. The second prescaler divides a third input clock by the prescaler divisor to generate a second input clock. The second phase detector receives the second input clock on the corresponding input path and the second feedback clock on the second feedback path, and generates a second error signal characterizing a second phase difference between the second input clock and the second feedback clock. The second low-pass filter generates a filtered second error signal by filtering the second error signal, wherein the second passband is larger than the first passband. The second oscillator generates an output clock based on the filtered second error signal. The second feedback divider divides the output clock by the second divisor to generate a second feedback clock. The PLL is configured to change the prescaler divisor to a new value corresponding to a different frequency to modify the configuration of the second PLL.

[0018] In some embodiments, the phase-locked loop is further configured to force the voltage input to another new value corresponding to a different frequency in order to change the configuration of the second phase-locked loop, wherein the voltage input represents a second error signal.

[0019] In some embodiments, the second phase-locked loop (PLL) includes a second source oscillator, a second phase detector, a second low-pass filter having a second passband, a second oscillator, and a second feedback divider. The second source oscillator generates a second input clock. The second phase detector receives the second input clock on a corresponding input path and the second feedback clock on a second feedback path, and generates a second error signal characterizing a second phase difference between the second input clock and the second feedback clock. The second low-pass filter generates a filtered second error signal by filtering the second error signal, wherein the second passband is larger than the first passband. The second oscillator generates an output clock based on the filtered second error signal. The second feedback divider divides the output clock by a second divisor to generate the second feedback clock. The PLL is configured to change the frequency of the second input clock to a new value corresponding to a different frequency, thereby changing the configuration of the second PLL. Attached Figure Description

[0020] The following is a brief description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram of an example device in which several aspects of the invention can be implemented.

[0022] Figure 2 This is a block diagram of a second PLL used in an embodiment of the present invention to replace the first PLL of a controlled oscillator.

[0023] Figure 3 This is a block diagram of a system that may include devices implemented according to several aspects of the present invention in embodiments of the present invention.

[0024] In the accompanying drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral in the corresponding reference numeral. Detailed Implementation

[0025] 1. Overview

[0026] According to one aspect of the invention, a PLL (referred to as a first PLL) uses a second PLL as a controlled oscillator for the first PLL. Due to the high bandwidth of the second PLL, the frequency of the output clock of the first PLL can be quickly changed by changing the configuration of the second PLL, in addition to changing the configuration of the first PLL. In one embodiment, changing the configuration of the first PLL requires setting a divisor in the first PLL for a feedback divider corresponding to the desired frequency change.

[0027] In one embodiment, changing the configuration of the second PLL requires changing the divisor of the feedback divider and / or the divisor of the prescaler of the second PLL. Furthermore, the operation of the second phase-locked loop can be further controlled by configuring the voltage input that drives the output frequency of the second PLL.

[0028] Several aspects of the invention are described below with reference to examples used for illustration. However, those skilled in the art will recognize that the invention can be implemented without one or more specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown in detail to avoid obscuring the features of the invention. Furthermore, the described features or aspects can be implemented in various combinations, although only a few combinations are described herein for the sake of brevity.

[0029] 2. Example Device

[0030] Figure 1 A block diagram illustrating details of an example component in which several aspects of the invention can be implemented is shown. The PLL 100 is shown to include a prescaler 105, a phase detector (PD) 110, a low-pass filter (LPF) 120, a controlled oscillator 130, a feedback divider 140, an output divider 150, and a control unit 160. Figure 1 The components and blocks are shown in an illustrative manner only. For example, when implemented primarily using analog components (e.g., LPF 120 as an analog filter), PLL 100 may include a charge pump between PD 110 and LPF 120. In alternative embodiments, PLL 100 may include more blocks, fewer blocks, or blocks with different implementations. For example, PLL 100 may be implemented as an all-digital PLL (ADPLL) having PD 110 implemented as a time-to-digital converter (TDC), a digital filter instead of LPF 120, and a voltage-controlled oscillator (VCO) implemented as a digitally-controlled oscillator (DCO). PLL 100 may also be implemented using a combination of analog and digital blocks, as will be apparent to those skilled in the art. The following description is provided in the context of ADPLL. However, several aspects of the present invention can be achieved through changes corresponding to other implementations of the PLL 100.

[0031] The prescaler 105 acts as a frequency divider and receives a source clock (src-clk) 101 from a clock source such as, for example, a crystal oscillator. The prescaler 105 also receives input from the control unit 160 on path 162B. The prescaler 105 divides the frequency of src-clk by the value received on path 162B to generate a reference clock (ref-clk) 106.

[0032] PD 110 receives ref-clk and feedback clock (fb-clk) 141 and generates an error signal representing the phase difference between the reference clock 106 and the feedback clock 141. The phase difference can be obtained based on the number of rising (or falling) edges of clocks 106 and 141. PD 110 can be implemented as a TDC, where the error signal is represented by a digital value, which is well known in the relevant field.

[0033] The LPF 120, implemented as a digital filter, receives the error signal generated by the PD 110 and performs low-pass filtering on the error signal to generate a filtered error signal as an output in digital form on path 123. Although it is noted that the LPF 120 is implemented as a digital filter, the LPF 120 can be implemented entirely as an analog filter or as a combination of analog and digital components.

[0034] The controlled oscillator 130 receives the filtered error signal on path 123 and generates an output clock (out-clk) 135 at a frequency determined by the strength of the filtered error signal (represented by the amplitude with a sign).

[0035] Feedback divider 140 represents a divider and receives out-clk as input. Feedback divider 140 divides the frequency of out-clk by the number (divisor) received on path 162A to produce fb-clk. Feedback divider 140 can be implemented as an integer-only divider or as a fractional divider that can be divided by a decimal (a number of the form MN, where M and N are integers and "." represents the decimal point). As is known in the related art, one way to implement a fractional divider is to generate a sequence of divisors (all integers) using a delta-sigma modulator (DSM), thereby effectively dividing out-clk by the divider circuitry within feedback divider 140 to divide it by the desired decimal.

[0036] Output divider 150 is another divider that divides the frequency of out-clk to produce a divided output clock (out-clk-div) 151.

[0037] Control unit 160 receives one or more user inputs from user equipment (e.g., a microprocessor system, a general-purpose computer, etc.) on path 161 (which may represent a single path or multiple paths). The inputs on path 161 can be provided in a suitable format, specifying the desired frequencies for out-clk and out-clk-div. Alternatively, the inputs on path 161 may include a divisor value to be used by feedback divider 140, prescaler 105, and output divider 150. Therefore, control unit 160 forwards the divisor value to the appropriate divider, or calculates the corresponding values ​​(digits) on paths 162A, 162B, and 162C and forwards these values ​​to feedback divider 140, prescaler 105, and output divider 150 to generate out-clk and out-clk-div at the desired frequencies. Control unit 160 can be implemented with the internal logic required to derive the divisor value from the user inputs on path 161. Alternatively or additionally, the control unit 160 may internally include registers to store division values ​​provided by the user via path 161.

[0038] The PLL 100 is typically implemented with a very narrow bandwidth (e.g., approximately a few millihertz to a few hertz (Hz)). Therefore, the LPF 120 can be implemented with a very narrow passband or bandwidth. Furthermore, the gain provided by the PD 110 and the controlled oscillator 130 can be correspondingly smaller to minimize jitter in the out-clk. Due to the narrow bandwidth of the PLL 100, any (large) changes in the out-clk frequency typically require a considerable amount of time. An example environment is described below where a clock with very low jitter is required, i.e., a jitter-attenuated PLL is needed.

[0039] As mentioned above, there are several environments where it is necessary to change (from the current frequency) to a known new frequency for out-clk135. For example, a very frequent requirement regarding jitter attenuation PLLs is to make a known frequency change of the output clock 135. The user can make this change occur by providing a corresponding division value to the feedback divider 140 (or to the prescaler 105, or to both the feedback divider 140 and the prescaler 105). However, the very low bandwidth of the PLL 100 results in a very long time elapsed from the start of the change until the new frequency reaches the desired value. This change is often referred to as overall PLL 100 operation in CNC oscillator mode.

[0040] As described below, one aspect of the invention enables known frequency changes of out-clk to be achieved very quickly.

[0041] 3. Rapid frequency changes

[0042] According to one aspect of the invention, the controlled oscillator 130 is implemented as another (second) PLL, and a plurality of frequency modification points are provided in the second PLL for rapid frequency changes at out-clk. To distinguish the main PLL 100 from the second PLL, the main PLL 100 can be regarded as the first PLL.

[0043] The second PLL does not require a narrow bandwidth, so the bandwidth can be very wide. Furthermore, the bandwidth of the second PLL can be substantially unrelated to (or independent of) the bandwidth of the first PLL. Therefore, in addition to changing one or more divisors of the feedback divider 140 and / or prescaler 105, the frequency of the out-clk can be rapidly changed by altering the parameters (configuration) of the high-bandwidth second loop at one or more locations (described below). Alternatively or additionally, the frequency of the clock source in the first PLL can also be changed. Generally, changes to the various parameters of the first PLL as described above can be considered changes to the configuration of the first PLL.

[0044] Figure 2 This is a block diagram illustrating an implementation of a controlled oscillator 130 as another (second) PLL. The second PLL 130 is shown as including a reference oscillator 210 (or "source oscillator"), a prescaler 220, a PD 230, a wide-bandwidth LPF 240, a controlled oscillator 250, a feedback divider 260, an output divider 270, and a control unit 280. In some embodiments, the wide-bandwidth LPF 240 is not implemented at all, resulting in a very large bandwidth for the second PLL. Alternatively, the LPF 240 is implemented with a bandwidth much larger (e.g., several times) than that of the first PLL. To distinguish the corresponding blocks of the first and second PLLs that perform similar or identical types of operations, these blocks are prefixed with the word "second" or "first" for quick reference.

[0045] Oscillator 210 generates a source clock (src-ck) as an output, and oscillator 210 can be implemented using any oscillator design technique.

[0046] The second prescaler 220 acts as a frequency divider and receives src-ck. The second prescaler 220 also receives input from the control unit 280 on path 282B. The second prescaler 220 divides the frequency of src-ck by the value received on path 282B to generate a reference clock (ref-ck) 223.

[0047] The second PD 230 receives the ref-ck and feedback clock (fb-ck) 263 and generates an error signal representing the phase difference between ref-ck and fb-ck. The phase difference can be obtained based on the number of rising (or falling) edges of each clock cycle. The second PD 230 can be implemented as a TDC, where the error signal is represented by a digital value.

[0048] A wide-bandwidth LPF (second LPF) 240, implemented as a digital filter, receives the error signal generated by the second PD 230 and performs low-pass filtering on the error signal received from the second PD 230 to generate a filtered error signal as an output in digital form on path 245. Alternatively, the wide-bandwidth LPF 240 can be an analog filter that performs frequency-selective filtering of the input current or input voltage based on the architecture of the second PLL. Typically, a charge pump is additionally implemented at the output of the PD 230, although for clarity in the figure, this charge pump can be considered to be implemented in either the PD 230 or the LPF 240.

[0049] The second controlled oscillator 250 receives the filtered error signal on path 245 and generates an intermediate output clock (out-c) 257 at a frequency determined by the strength of the filtered error signal.

[0050] The second output divider 270 is another divider that divides the frequency of out-c 257 to produce out-clk 135, which is Figure 1 The output clock of PLL 100. In some embodiments, no second output divider is implemented, and the output of the controlled oscillator 250 is itself the output clock out-clk 135 of PLL 100.

[0051] The second feedback divider 260 represents a divider and receives out-c as input. The second feedback divider 260 divides the frequency of out-c by the number received on path 282A (the divisor) to generate the feedback clock 263. In the case of fractional division, as is well known in the relevant art, the second feedback divider may include a DSM to receive the value on path 282A and generate a series of divisors for sequential use by the divider circuitry in the feedback divider 260. The feedback divider 260 can be implemented similarly to the first feedback divider 140, and will not be described again for the sake of brevity.

[0052] There are multiple ways that can be used to control the second PLL (e.g., via path 123, or via other paths in the first PLL). In other words, error values ​​on path 123 can propagate within the second PLL in various ways to control the second PLL to perform the operations required for the controlled oscillator in the PLL. For example, in one embodiment, voltage or current correction is applied to the oscillator 210 on control path 123A. The voltage / current can be DC voltage / DC current, or it can be the output of a digital-to-analog converter (DAC) that digitally corrects the voltage or current from the first PLL to convert it to voltage or current on path 123A. In another embodiment, or additionally, the division factor applied by prescaler 220 is set by the first PLL via control path 123B. In yet another embodiment, the division factor used by the feedback divider 260 of the second PLL is set by the first PLL via path 123C. It is important to note that a combination of two or more of the aforementioned control techniques can be used, rather than just one, as will be apparent to those skilled in the art. Furthermore, the second PLL 130 can be controlled by changing the division factor of the output divider 270 or the controlled oscillator 250 via corresponding paths 123E and 123D. It should also be noted that any changes to the controlled oscillator 250 can be in addition to the corresponding changes to the feedback divider 260 and / or the prescaler 220 and / or the oscillator 210.

[0053] Therefore, the second PLL can be controlled at one or more of the "control points," namely, controlling the oscillator 210, prescaler 220, controlled oscillator 250, output divider 270, and feedback divider 260, in order to achieve control over... Figure 1 The response is to the signal on path 123, where the corresponding control paths are represented by 123A-123E. Therefore, the second PLL is shown as including a control unit 280 that receives the value on path 123 of the first PLL. Control unit 280 is implemented to convert the value on path 123 into one or more corresponding values ​​on control paths 123A-123E to achieve a response.

[0054] Paths 282A-282E can be considered "configuration paths" through which the second PLL can be configured for operation. For example, a user can provide an input value on path 282 to specify an initial value for the frequency of the output clock 135. Control unit 280 can convert the value on path 282 to one or more values ​​on configuration paths 282A-282E to initialize the second PLL. Similarly, any desired change in the frequency of the output clock 135, i.e., a new frequency of the output clock 135, is specified by user input on paths 161 and 282. Control unit 280 can convert the value on path 282 to one or more values ​​on configuration paths 282A-282E to initialize the second PLL or cause a change in the frequency of the output clock 135. It can be observed that one or more control points can also be configuration points. Therefore, each control point can be implemented to include an arithmetic unit, such as an adder, to add pairs of values ​​received at inputs on paths 123X and 282X (where X is one of A, B, C, D, and E). Then the sum of the corresponding pairs is applied to the corresponding block so that the PLL 100 can quickly change the frequency of the output clock 135 to the new value.

[0055] The control unit 280 may internally include suitable digital logic and / or registers or memory for storing, calculating, and forwarding the corresponding values. Furthermore, the control unit 280 may perform any format conversion before forwarding the corresponding values.

[0056] Therefore, when the frequency of the PLL 100's output clock out-clk 135 requires a known frequency change, the user provides the desired value for the change on paths 161 and 282. The corresponding control units 160 and 280 then generate corresponding values ​​on one or more sets of paths 162A-162C (and paths not shown for changing the frequency of the clock source generating source clock 101) and paths 282A-282E, respectively, so that the PLL 100 can implement the change.

[0057] The values ​​required on paths 161 and 282 can be pre-calculated by the user because the new frequency is known prior. Therefore, the user can pre-calculate the required values ​​on paths 161 and 282 for several known values ​​of the frequency of the output clock 135. The pre-calculated values ​​can be stored in either control unit 160 or control unit 280.

[0058] Because the second PLL 130 has a wide bandwidth, it can quickly switch to generating out-c 257 and thus out-clk 135. When the second output divider 270 is not implemented, as described above, the output of the second controlled oscillator 250 is itself out-clk 135. Depending on whether the second output divider 270 is implemented, the divisor value to be provided to the second feedback divider 260 may differ. However, since the user knows / controls the divisor used by the second output divider 270, the user can easily calculate the two divisor values.

[0059] Therefore, by changing the corresponding “configuration values” provided to the first PLL and the second PLL simultaneously or in either order with small time gaps, the frequency of the output clock 135 can be rapidly changed.

[0060] Let f() represent the clock frequency. The following relationship illustrates how, in the example embodiment, the output frequency can be quickly changed by altering the divisors in the respective feedback dividers of the first and second PLLs. For example, if the current value of the divisor used by the output feedback divider 140 is k2, and if k2*Δ2 is the change required to shift k2 to the desired new frequency f(new-out-clk) of out-clk 135, then:

[0061] f(new-out-clk) = k2*(1+Δ2)*f(ref-clk), where ref-clk is the reference clock 106 of the first PLL100.

[0062] If the current value of the divisor used by the second output feedback divider 260 is k1, then in order to achieve the frequency change to f(new-out-clk), the new output frequency required in out-clk is also expressed as:

[0063] f(new-out-clk) = k1*(1+control(t))*f(ref-ck); where f(ref-ck) is the current frequency of reference clock 223.

[0064] The required change to k1 is represented by the function control(t). In the absence of any direct user changes to k1, control(t) represents the time-related correction that will occur normally due to the operation of the low-bandwidth (and therefore slow) main PLL loop 100.

[0065] However, according to various aspects of the invention, the user also changes the divisor k1 to k1*(1+Δ1), where Δ1 represents the change in k1 required to achieve the desired change in the frequency of the output clock out-clk. That is, the function control(t) is replaced by the change in k1. Since the second PLL 130 is very fast (high bandwidth), out-clk 135 quickly changes to the new desired frequency.

[0066] It is important to note that, in addition to changing k1 of the feedback divider 260, rapid changes can also be achieved by altering the divisor of the prescaler 220 via path 282B. Alternatively, the divisors of both the prescaler 220 and the feedback divider 260 can be changed accordingly. If the oscillator 210 is implemented in a manner that allows the user to adjust the frequency of its output ref-ck, then the oscillator 210 can also be adjusted accordingly to replace or supplement the other configuration changes described above.

[0067] When the controlled oscillator 250 is implemented as a voltage-controlled oscillator, a digital value can be written to the control input of the VCO via path 282D to change the capacitance value of the tuning circuit used within the VCO. When the controlled oscillator 250 is implemented as another PLL, the corresponding division value, etc., can be changed in a similar manner. Any level of PLL nesting can be used to replace both the controlled oscillator 250 and the controlled oscillator 130. In general, any parameter or value that can be user-controlled in one or more blocks of the second PLL and allows for rapid changes in the frequency of the output clock of the PLL 100 can be changed, as will be apparent to those skilled in the art who have read this disclosure.

[0068] The values ​​of all configuration parameters of the second PLL (e.g., excluding numerical values) can be calculated a priori by the user in a known manner and stored in the control unit 280, control unit 160 or memory unit inside the phase-locked loop 100.

[0069] The PLL 100 implemented as described above can be included in a larger device or system, as briefly described below.

[0070] 4. Clock synchronization system

[0071] Figure 3This is a block diagram of an example clock synchronization system, which includes a PLL implemented according to various aspects of the invention as detailed above. The clock synchronization system 300 is shown as including Synchronous Ethernet (SyncE) timing cards (timing card 310 and timing card 320) and line cards 1 to N, wherein only two line cards, line card 330 and line card 350, are shown for simplicity. Line card 330 is shown as including a jitter attenuator PLL 340 and a SyncE physical layer (PHY) transmitter 345. Line card 350 is shown as including a jitter attenuator PLL 360 and a SyncE PHY transmitter 365. Figure 3 The components can operate in a manner consistent with the Synchronous Ethernet network standard. As is well known in the relevant field, SyncE is a PHY-based technology used to achieve synchronization in packet-based Ethernet networks. The SyncE clock signal transmitted through the physical layer should be traceable to an external master clock (e.g., this SyncE clock signal comes from a timing card such as timing card 310 or timing card 320). Therefore, the timing of Ethernet packets is reset relative to the master clock, and then the Ethernet packet is transmitted in the physical layer. Thus, the timing of packets (e.g., packets on paths 331 and 351) is reset and sent without any timestamp information being recorded in the packets. The packets can be generated by appropriate applications, such as IPTV (Internet Protocol Television), VoIP (Voice over Internet Protocol), etc.

[0072] Therefore, line card 330 receives data packets on path 331, and after the timing of the data packets has been reset (synchronized) by the master clock, line card 330 forwards the data packets on output terminal 346. Similarly, line card 350 receives data packets on path 351, and after the timing of the data packets has been reset (synchronized) by the master clock, line card 350 forwards the data packets on output terminal 366.

[0073] The master clock (clock 311 or clock1) is generated by timing card 310. Timing card 320 generates a redundant clock (clock 321 or clock2), which is used by line cards 330 and 350 when the master clock 311 fails. The master clock 311 and the redundant clock 321 are provided to each of line cards 330 and 350 via a backplane (indicated by reference numeral 370).

[0074] In the online card 330, the jitter attenuator phase-locked loop 340 can be implemented as phase-locked loop 100 as detailed above, and this jitter attenuator phase-locked loop receives clocks 311 and 321. Phase-locked loop 340 generates an output clock 341, which is used to synchronize (re-timing) data packets received on path 331, after which the data packets are forwarded as re-timing data packets on path 346. Phase-locked loop 340 is implemented as detailed above to enable rapid frequency switching.

[0075] Similarly, in the online card 350, the jitter attenuator phase-locked loop 360 can also be implemented as the phase-locked loop 100 as detailed above, and this jitter attenuator phase-locked loop receives clocks 311 and 321. Phase-locked loop 360 generates an output clock 361, which is used to synchronize (re-timing) data packets received on path 351, after which the data packets are forwarded as re-timing data packets on path 366. Phase-locked loop 360 is implemented as detailed above to enable rapid frequency switching.

[0076] 5. Conclusion

[0077] Throughout this specification, references to "an embodiment," "embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but not necessarily all, refer to the same embodiment.

[0078] Although Figure 1 , Figure 2 and Figure 3 In the illustrations, terminals or nodes are shown as being directly connected (i.e., “connected”) to various other terminals, but it should be understood that additional components (as applicable to a particular environment) may also be present in the path, so the connection can be considered as being “electrically coupled” to the same connection terminals.

[0079] Although various embodiments of the invention have been described above, it should be understood that these embodiments are presented by way of example only and are not intended to be limiting. Therefore, the breadth and scope of the invention should not be limited by any of the foregoing embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A phase-locked loop for generating an output clock having a frequency locked to an input clock and for switching to a different frequency of the output clock after the output clock is generated, the frequency of the output clock being a product of a frequency of the input clock in a normal mode of operation and a desired divisor, the phase-locked loop comprising: a first phase detector coupled to receive a first input clock on an input path and a feedback clock on a feedback path, the first phase detector for generating an error signal representing a phase difference between the first input clock and the feedback clock; a first low pass filter having a first passband for producing a filtered error signal by filtering the error signal; a first oscillator coupled to produce the output clock from the filtered error signal, wherein the frequency of the output clock is determined by a strength of the filtered error signal; a first feedback divider for dividing the output clock by the desired divisor having a first value in the normal mode of operation; wherein the first phase detector, the first low pass filter, the first oscillator, and the first feedback divider collectively operate as a first phase-locked loop having a first bandwidth, wherein the first oscillator is implemented as a second phase-locked loop having a second bandwidth greater than the first bandwidth, wherein the phase-locked loop is configured to change a configuration of the first phase-locked loop and the second phase-locked loop to generate the output clock having the different frequency to switch to the different frequency of the output clock; and after changing the configuration of the first phase-locked loop and the second phase-locked loop, the second phase-locked loop having a higher bandwidth quickly generates the output clock having the different frequency so that the first phase-locked loop quickly changes to the different frequency in turn.

2. The phase-locked loop of claim 1, wherein, the phase-locked loop is configured to change the desired divisor of the first feedback divider to a second value equal to in order to change the configuration of the first phase-locked loop.

3. The phase-locked loop of claim 2, wherein, the second phase-locked loop comprises: a second phase detector for receiving a second input clock on a corresponding input path and a second feedback clock on a second feedback path, the second phase detector for generating a second error signal representing a second phase difference between the second input clock and the second feedback clock; a second oscillator for producing the output clock from the second error signal; a second feedback divider for dividing the output clock by a second divisor to produce the second feedback clock, wherein the phase-locked loop is configured to change the second divisor to a new value corresponding to the different frequency in order to change the configuration of the second phase-locked loop.

4. The phase-locked loop of claim 3, wherein, the second divisor is a sum of the filtered error signal and a third divisor, wherein the third divisor is provided by a user so that the new value is produced as the sum.

5. The phase-locked loop of claim 2, wherein, the second phase-locked loop comprises: a second prescaler for dividing a third input clock by a prescaler divisor to produce the second input clock; a second phase detector for receiving the second input clock on a corresponding input path and a second feedback clock on a second feedback path, the second phase detector for generating a second error signal characterizing a second phase difference between the second input clock and the second feedback clock; a second oscillator for generating the output clock from the second error signal; a second feedback divider for dividing the output clock by a second divisor to produce the second feedback clock, wherein the phase-locked loop is configured to change the prescaler divisor to a new value corresponding to the different frequency in order to change the configuration of the second phase-locked loop.

6. The phase-locked loop of claim 3, wherein, the phase-locked loop is further configured to force a voltage input to another new value corresponding to the different frequency in order to change the configuration of the second phase-locked loop, wherein the voltage input represents the second error signal.

7. A clock synchronization system, comprising: a line card coupled to receive a data packet, the line card for resetting a timing of the data packet with reference to a selected clock, and for transmitting the data packet with the reset timing; and a first timing card for generating a first clock; wherein the line card comprises a phase-locked loop coupled to receive the first clock, the phase-locked loop for generating an output clock locked to an input clock having a frequency based on the first clock as the selected clock, and for switching to a different frequency of the output clock after generating the output clock, the frequency of the output clock being a product of a frequency of the input clock in a normal mode of operation and a desired divisor, wherein the phase-locked loop comprises: a first phase detector coupled to receive the first clock on an input path and a feedback clock on a feedback path, the first phase detector for generating an error signal characterizing a phase difference between the first clock and the feedback clock; a first low pass filter having a first passband for producing a filtered error signal by filtering the error signal; a first oscillator coupled to generate the output clock from the filtered error signal, wherein the frequency of the output clock is determined by a strength of the filtered error signal; a first feedback divider for dividing the output clock by the desired divisor having a first value in the normal mode of operation; wherein the first phase detector, the first low pass filter, the first oscillator, and the first feedback divider collectively operate as a first phase-locked loop having a first bandwidth, wherein the first oscillator is implemented as a second phase-locked loop having a second bandwidth, the second bandwidth being greater than the first bandwidth, wherein the phase-locked loop is configured to change the configuration of the first phase-locked loop and the second phase-locked loop to generate the output clock having the different frequency in order to switch to the different frequency of the output clock; and after changing the configuration of the first phase-locked loop and the second phase-locked loop, the second phase-locked loop having the higher bandwidth quickly generates the output clock having the different frequency in order for the first phase-locked loop to quickly change to the different frequency in turn.

8. The clock synchronization system of claim 7, wherein, The phase-locked loop is configured to change the desired divisor of the first feedback divider to a second value to change the configuration of the first phase-locked loop.

9. The clock synchronization system of claim 8, wherein, The second phase-locked loop includes: a second phase detector to receive a second input clock on a corresponding input path and a second feedback clock on a second feedback path, the second phase detector to generate a second error signal characterizing a second phase difference between the second input clock and the second feedback clock; a second low pass filter having a second passband to produce a filtered second error signal by filtering the second error signal, wherein the second passband is greater than the first passband; a second oscillator to generate the output clock as a function of the filtered second error signal; a second feedback divider to divide the output clock by a second divisor to produce the second feedback clock, wherein the phase-locked loop is configured to change the second divisor to a new value corresponding to the different frequency to change the configuration of the second phase-locked loop.

10. The clock synchronization system of claim 9, wherein, The second divisor is a sum of the filtered error signal and a third divisor, wherein the value of the third divisor is provided by a user, such that the new value is produced as the sum.

11. The clock synchronization system of claim 8, wherein, The second phase-locked loop includes: a second pre-divider to divide a third input clock by a pre-divider divisor to produce a second input clock; a second phase detector to receive the second input clock on a corresponding input path and a second feedback clock on a second feedback path, the second phase detector to generate a second error signal characterizing a second phase difference between the second input clock and the second feedback clock; a second low pass filter having a second passband to produce a filtered second error signal by filtering the second error signal, wherein the second passband is greater than the first passband; a second oscillator to generate the output clock as a function of the filtered second error signal; a second feedback divider to divide the output clock by a second divisor to produce the second feedback clock, wherein the phase-locked loop is configured to change the pre-divider divisor to a new value corresponding to the different frequency to change the configuration of the second phase-locked loop.

12. The clock synchronization system of claim 9, wherein, The phase-locked loop is further configured to force a voltage input to another new value corresponding to the different frequency to change the configuration of the second phase-locked loop, wherein the voltage input represents the second error signal.

13. The clock synchronization system of claim 8, wherein, The second phase-locked loop includes: a second source oscillator to generate a second input clock; a second phase detector to receive the second input clock on a corresponding input path and a second feedback clock on a second feedback path, the second phase detector to generate a second error signal characterizing a second phase difference between the second input clock and the second feedback clock; a second low pass filter having a second passband to produce a filtered second error signal by filtering the second error signal, wherein the second passband is greater than the first passband; a second oscillator for generating the output clock in dependence on the filtered second error signal; a second feedback divider for dividing the output clock by a second divisor to produce the second feedback clock, wherein the phase-locked loop is configured to change the frequency of the second input clock to a new value corresponding to the different frequency in order to change the configuration of the second phase-locked loop.

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