Intelligent Low-Voltage Two-Phase Cold Plate with Flow Stability for Data Center Cooling Systems

Abstract

Systems and methods for cooling a data center are disclosed. In at least one embodiment, a cold plate includes an evaporator for removing heat from at least one computing device using a two-phase fluid, and a buffer is used to perform flow stabilization represented by different volumes or different flow rates of the two-phase fluid such that the two-phase fluid can flow between the evaporator and a condensation or compressor unit located outside the cold plate.

Description

[0001] Cross - Reference to Related Applications

[0002] This is a PCT application of U.S. Patent Application No. 17 / 224,814, filed on April 7, 2021. The disclosure of this application is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] At least one embodiment relates to cooling systems, including systems and methods for operating such cooling systems. In at least one embodiment, such a cooling system can be utilized in a data center that includes one or more racks or computing servers. Background Art

[0004] Data center cooling systems use fans to circulate air through server components. Certain supercomputers or other high-capacity computers may use water or other cooling systems instead of air-cooling systems to draw heat from server components or racks in the data center to an area outside the data center. The cooling system can include a cooler within the data center area (which can include areas outside the data center itself). Additionally, the area outside the data center can include a cooling tower or other external heat exchanger that receives the heated coolant from the data center and dissipates the heat to the environment (or external cooling medium) by forced air or other means. The cooled coolant is recirculated back into the data center. The cooler and the cooling tower together form a cooling facility. Brief Description of the Drawings

[0005] Figure 1 An exemplary data center cooling system that is subject to the improvements described in at least one embodiment is shown;

[0006] Figure 2 Server-level characteristics associated with an intelligent low-pressure two-phase cold plate with flow stability for a data center cooling system according to at least one embodiment are shown;

[0007] Figure 3 Rack-level characteristics associated with an intelligent low-pressure two-phase cold plate with flow stability for a data center cooling system according to at least one embodiment are shown;

[0008] Figure 4 Data center-level characteristics associated with an intelligent low-pressure two-phase cold plate with flow stability for a data center cooling system according to at least one embodiment are shown;

[0009] Figure 5 Shows according to at least one embodiment the Figures 2 - 4 method associated with a data center cooling system;

[0010] Figure 6 illustrates a distributed system according to at least one embodiment;

[0011] Figure 7 illustrates an exemplary data center according to at least one embodiment;

[0012] Figure 8 illustrates a client - server network according to at least one embodiment;

[0013] Figure 9 illustrates a computer network according to at least one embodiment;

[0014] Figure 10A illustrates a networked computer system according to at least one embodiment;

[0015] Figure 10B illustrates a networked computer system according to at least one embodiment;

[0016] Figure 10C illustrates a networked computer system according to at least one embodiment;

[0017] Figure 11 illustrates one or more components of a system environment according to at least one embodiment, in which services can be provided as third - party network services;

[0018] Figure 12 illustrates a cloud computing environment according to at least one embodiment;

[0019] Figure 13 illustrates a set of functional abstraction layers provided by a cloud computing environment according to at least one embodiment;

[0020] Figure 14 illustrates a supercomputer at the chip level according to at least one embodiment;

[0021] Figure 15 illustrates a supercomputer at the rack module level according to at least one embodiment;

[0022] Figure 16 illustrates a supercomputer at the rack level according to at least one embodiment;

[0023] Figure 17 illustrates a supercomputer at the overall system level according to at least one embodiment;

[0024] Figure 18A illustrates inference and / or training logic according to at least one embodiment;

[0025] Figure 18B illustrates inference and / or training logic according to at least one embodiment;

[0026] Figure 19 Shows the training and deployment of a neural network according to at least one embodiment;

[0027] Figure 20 Shows the architecture of a network system according to at least one embodiment;

[0028] Figure 21 Shows the architecture of a network system according to at least one embodiment;

[0029] Figure 22 Shows the control plane protocol stack according to at least one embodiment;

[0030] Figure 23 Shows the user plane protocol stack according to at least one embodiment;

[0031] Figure 24 Shows the components of a core network according to at least one embodiment;

[0032] Figure 25 Shows the components of a system supporting network function virtualization (NFV) according to at least one embodiment;

[0033] Figure 26 Shows a processing system according to at least one embodiment;

[0034] Figure 27 Shows a computer system according to at least one embodiment;

[0035] Figure 28 Shows a system according to at least one embodiment;

[0036] Figure 29 Shows an exemplary integrated circuit according to at least one embodiment;

[0037] Figure 30 Shows a computing system according to at least one embodiment;

[0038] Figure 31 Shows an APU according to at least one embodiment;

[0039] Figure 32 Shows a CPU according to at least one embodiment;

[0040] Figure 33 Shows an exemplary accelerator integrated slice according to at least one embodiment;

[0041] Figures 34A - 34B Shows an exemplary graphics processor according to at least one embodiment;

[0042] Figure 35AShows a graphics core according to at least one embodiment;

[0043] Figure 35B Shows a GPGPU according to at least one embodiment;

[0044] Figure 36A Shows a parallel processor according to at least one embodiment;

[0045] Figure 36B Shows a processing cluster according to at least one embodiment;

[0046] Figure 36C Shows a graphics multiprocessor according to at least one embodiment;

[0047] Figure 37 Shows the software stack of a programming platform according to at least one embodiment;

[0048] Figure 38 Shows according to at least one embodiment Figure 37 of the CUDA implementation of the software stack;

[0049] Figure 39 Shows according to at least one embodiment Figure 37 of the ROCm implementation of the software stack;

[0050] Figure 40 Shows according to at least one embodiment Figure 37 of the OpenCL implementation of the software stack;

[0051] Figure 41 Shows the software supported by a programming platform according to at least one embodiment; and

[0052] Figure 42 Shows according to at least one embodiment for use in Figures 37 - 40 compiled code to be executed on the programming platform. Detailed Description

[0053] In at least one embodiment, it is possible to utilize, such as Figure 1The exemplary data center 100 shown has a cooling system that undergoes the improvements described herein. In at least one embodiment, numerous specific details are set forth to provide a thorough understanding, but the concepts herein may be practiced without one or more of these specific details. In at least one embodiment, the data center cooling system can respond to sudden high heat demands caused by changing computational loads in current computing components. In at least one embodiment, since these demands vary from a minimum to a maximum of different cooling requirements or tend to range from a minimum to a maximum, an appropriate cooling system must be used to meet these demands in an economical manner. In at least one embodiment, for medium to high cooling demands, a liquid cooling system can be used. In at least one embodiment, high cooling demands are economically met by local immersion cooling. In at least one embodiment, these different cooling demands also reflect different thermal characteristics of the data center. In at least one embodiment, the heat generated from these components, servers, and racks is cumulatively referred to as the thermal characteristic or cooling demand because the cooling demand must fully address the thermal characteristic.

[0054] In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses the thermal characteristics in associated computing or data center equipment, such as those in a graphics processing unit (GPU), a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). In at least one embodiment, these components may be referred to herein as high heat density computing components. Additionally, in at least one embodiment, the associated computing or data center equipment may be a processing card having one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPU, switch, and CPU can be a heat generating characteristic of the computing device. In at least one embodiment, the GPU, CPU, or switch can have one or more cores, and each core can be a heat generating characteristic.

[0055] In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow in a data center cooling system can be supported by a two-phase refrigerant-air (R2A) heat exchanger. In at least one embodiment, such a low-pressure two-phase cold plate is adapted to support a two-phase fluid passing therethrough at a pressure below 50 psi. In at least one embodiment, such an R2A heat exchanger can be provided for cooling independently of an auxiliary cooling loop and its associated primary cooling loop and cooling facilities in the data center cooling system or in a supplementary configuration with an auxiliary cooling loop and its associated primary cooling loop and cooling facilities. In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow can be achieved by a two-phase fluid (such as a refrigerant or a dielectric engineering fluid) from at least one cold plate, and heat is released into the hot aisle of the data center using a compressor or a condensing unit within the data center.

[0056] In at least one embodiment, the R2A heat exchanger has an associated fan and a compressor unit within the data center. In at least one embodiment, such an R2A heat exchanger can have a pump that implements a condensing unit within the data center. In at least one embodiment, this combination of a condensing unit and a pump can be referred to as or can support a two-phase R2A heat exchanger, which is also supported by a two-phase capable cold plate. Thus, in at least one embodiment, the condensing unit uses the pump to circulate the fluid through the R2A heat exchanger to dissipate heat in such a fluid, while the compressor unit uses the compressor to compress the vapor or gas into a fluid before circulating through the R2A heat exchanger to dissipate heat in such a fluid. In at least one embodiment, the condensing unit or the compressor unit can be interchangeable with at least the R2A heat exchanger and associated hardware (such as a buffer for flow stability) to collectively refer to a two-phase fluid loop. In at least one embodiment, such a buffer provides flow stability by allowing the two-phase fluid to expand therein and allowing two-phase fluids with different flow velocities and flow rates to pass through a closed two-phase fluid loop (or cooling loop).

[0057] In the present application, a two-phase capable cold plate includes microchannels, which can be a gasket heat exchanger directly attached to high heat density components (such as GPUs, CPUs, and switches) within a data center server. In at least one embodiment, the heat removed from such a cold plate can be dissipated through a condensing or compressor unit, which can be attached to the server or can be part of the condensing or compressor unit wall of the server rack (including the R2A heat exchanger). In at least one embodiment, metal fluid line connectors can be used between the condensing or compressor unit, the R2A heat exchanger, and the cold plate, which allows the refrigerant forming the two-phase fluid to migrate from the high pressure stage to the low pressure stage of the two-phase fluid (or refrigeration) cooling cycle. In at least one embodiment, a pump can be used in a location within the server or throughout the rack to assist the two-phase fluid in moving through the two-phase cooling cycle. In at least one embodiment, a buffer or tank allows the two-phase fluid to expand at the server or within the rack. In at least one embodiment, the size of such a buffer can be adjusted in part based on the server or rack-level design intended for the two-phase fluid cooling cycle. In at least one embodiment, sensors (such as temperature, flow, pressure, and mass sensors) allow for intelligent control of an intelligent low-pressure two-phase cold plate with stable flow in a data center cooling system.

[0058] In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow uses a two-phase refrigerant or engineering fluid, such as 7000, or some of the engineering fluids of, wherein the cold plate and the compressor or condensing unit are used to remove heat from at least one computing device. In at least one embodiment, such a cold plate is adapted to support an evaporator section therein. In at least one embodiment, stable flow can be represented by different volumes or different flow rates of the two-phase fluid, which is enabled to flow between such an evaporator section and a condensing unit external to the cold plate. In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow utilizes a two-phase refrigerant or engineering fluid, which can address cooling requirements generating up to 100 kW of heat. In at least one embodiment, different flow rates or volumes of the two-phase fluid can be provided as needed according to at least different cooling requirements set within a closed loop represented by a data center cooling system with an intelligent low-pressure two-phase cold plate (with stable flow).

[0059] In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability allows two-phase fluid to flow directly into the two-phase cold plate having at least one evaporator. In at least one embodiment, an expansion valve associated with at least one cold plate or R2A heat exchanger enables the two-phase fluid to pass through the cold plate to cause a phase change of the two-phase fluid and to absorb heat from at least one computing device. In at least one embodiment, heat from at least one computing device is absorbed into the two-phase fluid, which is then transferred to a condensation unit (with a low-capacity pump) or a compressor unit and an R2A heat exchanger to cause at least a portion of the absorbed heat to be released into the hot aisle within the data center. In at least one embodiment, sensors (such as temperature, flow, humidity, leakage, pressure, and fluid or coolant chemistry) allow for intelligent operation of the intelligent low-pressure two-phase cold plate with flow stability in the event of any problems in the secondary or primary cooling loop.

[0060] In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability can address the problem in a cold plate that can mainly support a coolant for cooling purposes. In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability can address the problem of a refrigerant-based system that requires an external condensation unit. In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability uses a condensation or compressor unit within the data center and a cold plate suitable for two-phase fluid, such as having microchannels for coolant flow, different from the microchannels for two-phase fluid. Thus, in at least one embodiment, for cooling requirements using an intelligent low-pressure two-phase cold plate with flow stability, no external access is required relative to the data center. In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability can support heat absorption from at least one computing device and can cause at least a portion of the absorbed heat to be released into the hot aisle, which enables a refrigerant-based system to be used with the cold plate.

[0061] In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability refers to a system having at least one associated cold plate and a condensation unit that is adapted to support a two-phase fluid that transitions from vapor to liquid and vice versa at different operating stages. In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stability can address the liquid cooling of data center servers and switches having R2A heat exchangers, which have application limitations due to the limited heat removal capacity from high heat density computing components (such as GPUs / CPUs / switches). In at least one embodiment, single-phase coolants, such as water and those with additives (including Water (as a coolant) exhibits such application limitations. In at least one embodiment, the heat density of data center racks is increasing continuously, and there is a continuous need for innovative methods for removing heat, while being limited by the preconditions of existing air-cooled data centers.

[0062] In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow includes an R2A heat exchanger and utilizes a two-phase fluid. In at least one embodiment, the two-phase fluid may include or other similar working two-phase fluids. In at least one embodiment, the two-phase fluid can be used for heat removal using a direct-to-chip two-phase cold plate having an evaporator section. In at least one embodiment, such a cold plate can be attached to a GPU, CPU, or switch in a rack. In at least one embodiment, the associated condensing unit (or compressor unit) of the R2A heat exchanger utilizes a compressor (or pump) and a condensing coil (such as the R2A heat exchanger) to release at least a portion of the heat collected from one or more server components. In at least one embodiment, such a condensing unit or compressor unit (having an associated R2A heat exchanger) is placed in a row of server racks and can dissipate the heat within the data center from the two-phase fluid flowing through the R2A heat exchanger.

[0063] In at least one embodiment, the two-phase fluid undergoes a liquid-to-gas phase change within the evaporator section of the cold plate. In at least one embodiment, the two-phase fluid is in a gaseous phase when entering the compressor but is in a fluid state in the pump. In at least one embodiment, the compressor generates high-pressure and high-temperature vapor. In at least one embodiment, the condensing unit or compressor unit of the intelligent low-pressure two-phase cold plate with stable flow enables the cooling of the vapor (or fluid), where at least the gaseous phase condenses to a liquid phase within the compressor unit. In at least one embodiment, when there is a condensing unit or compressor unit of the intelligent low-pressure two-phase cold plate, the two-phase fluid is in a liquid phase. In at least one embodiment, the two-phase fluid transforms into a gaseous phase in a low-pressure environment and is capable of absorbing heat within the evaporator section of the cold plate. In at least one embodiment, the two-phase fluid transforms into vapor when it absorbs heat and is sent to the compressor to cycle back to a liquid after heat is released at the applied pressure and at least at the R2A heat exchanger.

[0064] In at least one embodiment, such an intelligent low-pressure two-phase cold plate with flow stability can provide an intelligent low-pressure two-phase cold plate with flow stability, which is provided via a buffer zone between a condensation unit placed outside the cold plate and an evaporator within the cold plate. In at least one embodiment, this enables the provision of a two-phase fluid for directly cooling an associated computing device. In at least one embodiment, the problem solved by such an intelligent low-pressure two-phase cold plate with flow stability is to overcome cold plates designed to be used with separate coolants or refrigerant systems operating at very high pressures (such as 700 psi or about 700 psi), which makes them prone to leakage and difficult to handle.

[0065] In at least one embodiment, the improvement provided by the intelligent low-pressure two-phase cold plate with flow stability is the ability to use a low-pressure fluid system (such as a two-phase fluid for cooling). In at least one embodiment, such a fluid can be an engineered dielectric fluid operable at such low pressures (including at 50 psi). In at least one embodiment, such a fluid can be directly provided to the evaporator section within the cold plate. In at least one embodiment, this makes refrigerant cooling less prone to catastrophic leakage. In at least one embodiment, a surge tank (referred to as a buffer zone) is used between a refrigerant-adapted cold plate (which may be simply referred to as a cold plate herein) and a condensation unit within a data center to manage flow variations of the two-phase fluid, which may be caused by sudden high heat generation from an associated computing device, which subsequently triggers a high cooling demand for the intelligent low-pressure two-phase cold plate with flow stability. In at least one embodiment, because such a system can be a closed loop, the buffer zone enables cycling and expansion characteristics within such a closed loop, with the ability to respond to a wide range of cooling demands. Additionally, in at least one embodiment, such a buffer zone is adapted to support at a pressure of 50 psi, even in the most extreme surge tank events that may otherwise require complex safety and relief features.

[0066] In at least one embodiment, it is possible to utilize, such as Figure 1The exemplary data center 100 shown has a cooling system that undergoes the improvements described herein. In at least one embodiment, the data center 100 can be one or more rooms 102 with racks 110 and auxiliary equipment to house one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside the data center 100. In at least one embodiment, the cooling tower 104 dissipates heat from within the data center 100 by acting on a primary cooling circuit 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling circuit 106 and a second or auxiliary cooling circuit 108 to enable heat absorption from the second or auxiliary cooling circuit 108 into the primary cooling circuit 106. In at least one embodiment, in one aspect, the auxiliary cooling circuit 108 can access different ducts leading into the server trays as needed. In at least one embodiment, the circuits 106, 108 are shown as line diagrams, but one of ordinary skill in the art will recognize that one or more pipe connection features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) pipes can be used with the associated pipes to move fluid along each provided circuit 106; 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the coolant circuits 106, 108 so that the coolant can move in accordance with temperature sensors at different locations, including in the room, in one or more racks 110, and / or in server enclosures or server trays within one or more racks 110.

[0067] In at least one embodiment, the coolant in the primary cooling circuit 106 and the auxiliary cooling circuit 108 can be at least water and an additive. In at least one embodiment, the additive can be ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling circuit and the auxiliary cooling circuit can have its own coolant. In at least one embodiment, the coolant in the auxiliary cooling circuit can be dedicated to the requirements of components in the server trays or the associated racks 110. In at least one embodiment, the CDU 112 is capable of performing sophisticated control of the coolant within the provided coolant circuits 106, 108 independently or simultaneously. In at least one embodiment, the CDU is adapted to control the flow rate of the coolant such that the coolant is appropriately distributed to absorb the heat generated within the associated racks 110. In at least one embodiment, more flexible ducts 114 are provided from the auxiliary cooling circuit 108 to enter each server tray to supply coolant to the electrical and / or computing components therein.

[0068] In at least one embodiment, a duct 118 forming part of the auxiliary cooling loop 108 may be referred to as a chamber manifold. Separately, in at least one embodiment, an additional duct 116 may extend from the row manifold duct 118 and may also be part of the auxiliary cooling loop 108, but may be referred to as a row manifold. In at least one embodiment, the coolant duct 114 enters the rack as part of the auxiliary cooling loop 108, but may be referred to as a rack cooling manifold within one or more racks. In at least one embodiment, the row manifold 116 extends along the rows in the data center 100 to all the racks. In at least one embodiment, the ducts of the auxiliary cooling loop 108 including the coolant manifolds 118, 116, and 114 may be improved by at least one embodiment herein. In at least one embodiment, a cooler 120 may be provided in the primary cooling loop within the data center 102 to support cooling before the cooling tower. In at least one embodiment, for the present disclosure, an additional cooling loop that may be present in the primary control loop and that provides cooling external to the racks and external to the auxiliary cooling loop may be different from the primary cooling loop and may be associated with the primary cooling loop.

[0069] In at least one embodiment, in operation, heat generated within the server tray of the provided rack 110 may be transferred via the flexible tubing of the row manifold 114 of the second cooling loop 108 to the coolant exiting one or more racks 110. In at least one embodiment, a second coolant (in the auxiliary cooling loop 108) for cooling the provided rack 110 from the CDU 112 moves via the provided tubing toward one or more racks 110. In at least one embodiment, the second coolant from the CDU 112 is transferred from one side of the chamber manifold having the tubing 118 via the row manifold 116 to one side of the rack 110 and is transferred through one side of the server tray via a different tubing 114. In at least one embodiment, the used or returned second coolant (or the heat-carrying second coolant exiting the computing components) exits from the other side of the server tray (such as entering the left side of the rack and exiting the right side of the rack for the server tray after circulating through the server tray or through the components on the server tray). In at least one embodiment, the used second coolant exiting the server tray or the rack 110 exits from a different side (such as the exit side) of the tubing 114 and moves to the parallel but also exit side of the row manifold 116. In at least one embodiment, the used second coolant from the row manifold 116 moves within the parallel portion of the chamber manifold 118 and travels toward the CDU 112 in a direction opposite to the entering second coolant (which may also be the updated second coolant).

[0070] In at least one embodiment, the used secondary coolant exchanges its heat with the primary coolant in the primary cooling loop 106 via the CDU 112. In at least one embodiment, the used secondary coolant can be refreshed (such as relatively cooled when compared to the temperature of the used secondary coolant stage) and be ready to cycle back to one or more computing components through the secondary cooling loop 108. In at least one embodiment, the various flow and temperature control features in the CDU 112 enable the control of the heat exchanged from the used secondary coolant or the flow of the secondary coolant into and out of the CDU 112. In at least one embodiment, the CDU 112 is also capable of controlling the flow of the primary coolant in the primary cooling loop 106.

[0071] In at least one embodiment, as Figure 2 shown, the server-level feature 200 can be associated with an intelligent low-pressure two-phase cold plate with flow stabilization for a data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or enclosure 202. In at least one embodiment, the server tray or enclosure 202 includes a server manifold 204 that is intermediately coupled between the provided cold plates 210A-D of the server tray or enclosure 202 and the rack manifold of the rack that houses the server tray or enclosure 202. In at least one embodiment, the server tray or enclosure 202 includes one or more cold plates 210A-D associated with one or more computing or data center components or devices 220A-D.

[0072] In at least one embodiment, one or more server-level cooling loops 214A, 214B can be provided between the server manifold 204 and one or more cold plates 210A-D. In at least one embodiment, each server-level cooling loop 214A, 214B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when there are cold plates 210A, 210B in a series configuration, an intermediate line 216 can be provided. In at least one embodiment, one or more cold plates 210A-D can support different ports and channels for a secondary coolant or a different fluid (such as a two-phase fluid) for circulating from a pre-loaded two-phase R2A heat exchanger with a buffer. In at least one embodiment, the cooling loop with a two-phase fluid is a closed loop using a buffer with a determined capacity to be able to address different cooling requirements at low pressure as the flow rate or flow of this two-phase fluid increases. In at least one embodiment, the secondary coolant for cooling the associated computing device can be provided to the server manifold 204 via the provided inlets and outlets 206A, 206B. In at least one embodiment, the two-phase fluid for cooling can be provided to the server manifold 204 via the provided inlets and outlets 208A, 208B.

[0073] In at least one embodiment, the server tray 202 is a server tray for immersion cooling that can be fluid-immersed. In at least one embodiment, the fluid for the server tray for immersion cooling can be a dielectric engineering fluid that can be used in an immersion-cooled server. In at least one embodiment, an auxiliary coolant or a two-phase fluid can be used to cool the engineering fluid. In at least one embodiment, the two-phase fluid can be used to cool the engineering fluid when the main cooling loop associated with the auxiliary cooling loop for circulating the auxiliary coolant has failed or is failing. In at least one embodiment, at least one cold plate thus has ports for the auxiliary cooling loop and for the two-phase fluid cooling loop, and can support the two-phase fluid cooling loop that is activated in the event of a failure of the main cooling loop. In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow can be used without an auxiliary cooling loop.

[0074] In at least one embodiment, at least one dual-cooling cold plate 210B; 250 can be configured to operate beside the conventional cold plates 210A, C, D. In at least one embodiment, a three-dimensional (3D) magnified view (of cold plate 250) provides internal details of at least some of the features that can be included in the dual-cooling cold plate 210B. In at least one embodiment, a cutaway view of a first portion 250B of the cold plate 250 having microchannels 270 (also 270A) shows a different second portion 250A having different microchannels 264. In at least one embodiment, a conventional cold plate can have a set of microchannels 264; 270 instead of the two sets shown. In at least one embodiment, the dual-cooling cold plate 250 has different paths 264, 270 (each path also referred to as a microchannel) for the auxiliary coolant for the auxiliary cooling loop and for the two-phase fluid for the two-phase fluid cooling loop. In at least one embodiment, the nature of the auxiliary coolant or the two-phase fluid may not be dielectric. In at least one embodiment, under the use case of an immersion-cooled server, the two-phase fluid, which can be a dielectric engineering fluid, can be applicable to both cold plate applications and server tray applications for immersion cooling.

[0075] In at least one embodiment, some of the microchannels 270 are paths provided by fins 270A or other such aspects that bulge internally and perpendicularly to the base of the cold plate portion 250B, such that there is a gap therebetween for fluid or coolant flow. In at least one embodiment, some of the microchannels 264 are fluid passageways in different cold plate portions 250A of the cold plate 250. In at least one embodiment, some of the microchannels 264 for two-phase fluid represent the evaporation (or evaporator) portion of the cold plate 250. In at least one embodiment, the flow controller 280 located on the inlet side of the cold plate 250 can act as an expansion valve; and this enables the two-phase fluid to enter the cold plate 250 and expand at a lower pressure, and to change phase before leaving the cold plate 250 during heat absorption from at least one computing device. In at least one embodiment, the reference to the cold plate and its dual cooling feature may imply a reference to a cold plate that can support at least two types of cooling circuits, unless otherwise stated. In at least one embodiment, both types of cold plates receive two-phase fluid for cooling, but one type can support both an auxiliary cooling circuit and a two-phase fluid cooling circuit. In at least one embodiment, a standard coolant (such as facility water) can be used in the auxiliary cooling circuit.

[0076] In at least one embodiment, the two-phase fluid can only support cold plate use and is not available for immersion cooling. In at least one embodiment, each type of cold plate receives different two-phase fluids and auxiliary coolants from a respective two-phase fluid cooling circuit, or an auxiliary cooling circuit or other cooling circuit that interfaces with the main cooling circuit. In at least one embodiment, in the case where different fluids (such as coolants) are used with different coolant distribution units (CDUs) of different auxiliary circuits, then different cooling circuits can be applicable to the dual-cooling cold plate along with the two-phase fluid cooling circuit, such that different channels can be used for each of the two-phase fluids and for different auxiliary coolants. In at least one embodiment, any cold plate mentioned herein is capable of operating above the dew point to prevent moisture formation, for example above 20 degrees Fahrenheit, or above the determined ambient dew point.

[0077] In at least one embodiment, the dual-cooling cold plate 250 is adapted to receive two types of fluids (such as an auxiliary coolant and a two-phase fluid) and keep the two types of fluids distinct from each other via its different ports 252, 272, 268, 262 and their different paths 264, 270; such as by different sections separated by gaskets and plates (e.g., in a gasket-type cold plate). In at least one embodiment, each different path is a fluid path. In at least one embodiment, fluids (such as a two-phase fluid) from a two-phase fluid source and an auxiliary coolant can be provided simultaneously to address additional cooling requirements.

[0078] In at least one embodiment, the dual-cooling cold plate 250 includes ports 252, 272 to receive a two-phase fluid into the cold plate 250 and transfer the two-phase fluid out of the cold plate 250. In at least one embodiment, the dual-cooling cold plate 250 includes ports 268, 262 for receiving an auxiliary coolant into the cold plate 250 and transferring the auxiliary coolant out of the cold plate 250. In at least one embodiment, the ports 252, 272 may have valve caps 254, 260 (or expansion valve features) that may be directional and pressure-controlled such that the two-phase fluid can expand through the cold plate 250. In at least one embodiment, the valve caps may be associated with all of the provided ports, but the expansion valve may be dedicated to the two-phase fluid inlet. In at least one embodiment, each such valve may be rated to support pressures up to 50 psi. In at least one embodiment, the provided valve caps 254, 260 are mechanical features of an associated flow controller that also has corresponding electronic features (such as at least one processor for executing instructions stored in an associated memory and controlling the mechanical features of the associated flow controller).

[0079] In at least one embodiment, each valve may be actuated by the electronic features of the associated flow controller. In at least one embodiment, the electronic and mechanical features of the provided flow controller are integrated. In at least one embodiment, the electronic and mechanical features of the provided flow controller are physically distinct. In at least one embodiment, the reference to the flow controller may be to one or more or a combination of the provided electronic and mechanical features, but at least the reference enables control of the flow of coolant or two-phase fluid through each cold plate or through a server tray or enclosure for immersion cooling.

[0080] In at least one embodiment, the electronic features of the provided flow controller receive a control signal and assert control over the mechanical features. In at least one embodiment, the electronic features of the provided flow controller may be other electronic components such as an actuator or other similar electromechanical feature. In at least one embodiment, a flow pump may be used as the flow controller. In at least one embodiment, an impeller, piston, or bellows may be the mechanical feature, and an electric motor and circuitry form the electronic features of the provided flow controller.

[0081] In at least one embodiment, the circuitry of the provided flow controller may include a processor, a memory, a switch, sensors, and other components that together form the electronic characteristics of the provided flow controller. In at least one embodiment, the provided ports 252, 262, 272, 268 of the provided flow controller are adapted to allow immersion fluid to enter or to allow immersion fluid to exit. In at least one embodiment, a flow controller 280 (capable of acting as an expansion valve) may be associated with a fluid line 276 (also 256, 274) that enables a two-phase fluid (such as a refrigerant or engineered fluid) to enter and exit to a cold plate 210B. In at least one embodiment, other flow controllers may similarly be associated with coolant lines 210, 216, 212 (also 266, 258) to enable an auxiliary coolant to enter and exit the cold plate 210B.

[0082] In at least one embodiment, a buffer 276A may be provided within the fluid line 276 of the two-phase fluid. In at least one embodiment, such buffer placement may be based in part on the range of cooling requirements achieved for the associated cold plate 210B. In at least one embodiment, higher cooling requirements may require a higher flow rate or flow of the two-phase fluid. In at least one embodiment, such cooling requirements may be addressed by buffer 276A, but may be addressed by other series buffers between the cold plate 210B and the condensation unit external to the cold plate 210B.

[0083] In at least one embodiment, the size of buffer 276A may be determined by the type of two-phase fluid used and its thermal properties (e.g., the minimum temperature in its fluid phase versus the maximum temperature in its gas phase). In at least one embodiment, this information may be used to determine how long the buffer stores the two-phase fluid in a particular area before ambient heat renders the two-phase fluid ineffective for removing heat from the associated computing device 220B. In at least one embodiment, buffer 276A is continuously replenished and caches the two-phase fluid, which is represented by the ability to retain at least some of the two-phase fluid for a short period of time by such caching before it flows past, and the buffer is designed as a pass-through reservoir within a closed loop of the two-phase fluid circuit between the cold plate (its evaporator), the buffer, and the condensation unit (with its associated R2A heat exchanger). In at least one embodiment, such buffer 276A also provides an expansion tank feature by allowing some of the two-phase fluid to evaporate and expand due to ambient heat within the two-phase fluid circuit.

[0084] In at least one embodiment, the two-phase fluid enters the provided fluid line 276 via dedicated fluid inlet and outlet lines 208A, B. In at least one embodiment, the server manifold 204 is adapted to have channels (shown by the dashed lines) therein to support different paths to different fluid lines 276 (also 256, 274) and to any remaining loops 214A, B associated with the auxiliary coolant inlet and outlet lines 206A, B. In at least one embodiment, there may be multiple manifolds to differently support the two-phase fluid and the auxiliary coolant. In at least one embodiment, there may be multiple manifolds to differently support the inlets and outlets for each of the two-phase fluid and the auxiliary coolant. In at least one embodiment, if the two-phase fluid is used alone without an auxiliary cooling loop, the fluid flow through one of the provided fluid paths (at least within the cold plate or the server tray) can be enabled to a two-phase fluid source or a coolant row manifold (such as row manifold 360, different from Figure 3 the auxiliary coolant row manifold 350 in

[0085] In at least one embodiment, a first flow can be used to enable the auxiliary coolant to flow through one or more of the provided ports 252, 272 and the associated paths 270. In at least one embodiment, the dual-cooling cold plate 250 can have isolated plate portions 250A, 250B filled with the two-phase fluid and / or the auxiliary coolant while being kept distinct from each other by gaskets or seals. In at least one embodiment, a second flow can be used to enable the two-phase fluid to flow through the provided ports 268, 262 and the associated paths 264 through fins or microchannels 270A that extend across the base of the cold plate portion 250B.

[0086] In at least one embodiment, the flow controller 278 can be associated with the fluid inlet 276 and the outlet portion at the server manifold 204 rather than with the provided flow controller 280 at the respective cold plate. In at least one embodiment, the first flow uses only the two-phase fluid and can be enabled when a fault is determined in the auxiliary cooling loop or the primary cooling loop such that the auxiliary coolant cannot effectively absorb heat from at least one computing device. In at least one embodiment, the fault can be that the auxiliary coolant is not sufficiently cooled via the CDU and thus it may not be able to absorb sufficient heat from at least one computing device via its associated cold plate.

[0087] In at least one embodiment, as Figure 3The rack-level feature 300 shown in [[ ]] can be associated with an intelligent low-pressure two-phase cold plate with flow stabilization for a data center cooling system. In at least one embodiment, the rack-level feature 300 includes a rack 302 having brackets 304, 306 for suspending cooling manifolds 314A, 314B. In at least one embodiment, although the rack 330 is shown separately from the rack 302, the rack 330 can show a rear perspective view of the rack 302. In at least one embodiment, similarly, the brackets 334, 336 provided on the rack 330 are perspective views of the brackets 304, 306 provided on the rack 302. In at least one embodiment, the brackets 304, 306 provided for the rack are flat structures against the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack extend from the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack are attached to the inner wall of the rack and have a plurality of mounting points facing one or more directions (including inside the rack or towards the rear of the rack).

[0088] In at least one embodiment, cooling manifolds 314A, 314B can be provided to transfer auxiliary coolant between server-level features 200 (and shown as server trays or enclosures 308 in [[ ]]) of a data center cooling system and a CDU of an auxiliary cooling loop, such as Figure 3 the CDU 406 of [[ ]]. In at least one embodiment, different CDUs can serve different racks. In at least one embodiment, different rack cooling manifolds can differently be part of an auxiliary cooling loop and a two-phase fluid cooling loop. Figure 4

[0089] ​In at least one embodiment, the row manifold 350 can be part of an auxiliary cooling loop for feeding the inlet rack manifold 314A via the provided pipelines 310A, 310. In at least one embodiment, the auxiliary coolant travels via the provided pipeline 316 to the cold plate 326 to extract or absorb heat from the associated computing device 324 within the server 308; and travels via the provided pipeline 318 to the outlet rack manifold 314B and through the provided pipelines 312, 312A, and returns to the same or a different row manifold 350. In at least one embodiment, an intelligent low-pressure two-phase cold plate with flow stabilization can operate independently of the auxiliary cooling loop and can cool at least one computing device associated with the cold plate 326 enabling two-phase fluid (dual cooling or single cooling) via the provided pipelines 312B, 310B of the two-phase fluid cooling loop and the two-phase fluid cooling manifold 360 associated with the R2A heat exchanger 364. In at least one embodiment, a buffer 372 can be provided on the inlet side to the cold plate 326 as shown or after the manifold 360. In at least one embodiment, such a buffer 372 achieves flow stabilization represented by different volumes or different flow rates of the two-phase fluid, which is enabled to flow between the condensation unit 362 (and the R2A heat exchanger) located outside the cold plate 326 and its evaporator (implemented by Figure 2 the channel 264 in

[0090] In at least one embodiment, one or more diverter flow controllers 310C, 312C isolate each of the auxiliary cooling loop and the two-phase fluid cooling loop. In at least one embodiment, one or more diverter flow controllers have a downstream expansion valve for providing an expansion characteristic to the two-phase fluid for efficient heat absorption at an appropriate pressure. In at least one embodiment, such a downstream expansion valve can be adapted for low-pressure operation at a pressure below 50 psi. In at least one embodiment, the two-phase fluid can be used with at least one cold plate 326 and an intelligent two-phase fluid R2A heat exchanger. In at least one embodiment, the provided pipelines 320, 322, 354 can be associated with the two-phase fluid and can be associated with the inlet 310B and the outlet 312B to engage with the R2A heat exchanger 364 and the associated pipelines 370 and the associated components 360, 362, 366, 368.

[0091] In at least one embodiment, a data center cooling system includes a refrigerant - to - air (R2A) heat exchanger 364 that is associated with a fan 366 and a condensing unit and a pump 362 or may be associated with a compressor unit. In at least one embodiment, an intelligent low - pressure two - phase cold plate with flow stabilization includes heat - exchange tubes or gasket heat exchangers that form the R2A heat exchanger 364. In at least one embodiment, parts, components, or assemblies 362 - 366 of the intelligent two - phase fluid R2A heat exchanger may be integrated together into a single unit. In at least one embodiment, parts, components, or assemblies 362 - 366 of the R2A heat exchanger may be integrated between racks and may be associated with the racks at or via bracket areas provided on the racks 330. In at least one embodiment, such integration uses a buffer to provide flow stabilization of the two - phase fluid at the outlet of such an integrated system between the provided racks.

[0092] In at least one embodiment, the heat - exchange tubes or gasket heat exchangers in the first (two - phase fluid) part 364 may be adapted to circulate a two - phase fluid that enters through one of the provided flow controllers 368 and exits through another of the provided flow controllers 368. In at least one embodiment, on such an outlet side, a buffer 372 may be provided for flow stabilization. In at least one embodiment, the buffer may be used when a sudden demand is imposed on a two - phase cooling loop that may be a closed loop. In at least one embodiment, a two - phase fluid may be immediately required to address a high cooling demand. In at least one embodiment, such a two - phase fluid may be provided from such a buffer 372 without straining the closed - loop strain of the two - phase fluid cooling loop. In at least one embodiment, such straining is with respect to the compressor or condensing unit 362, which may be required to handle a lower or higher fluid flow passing through it. In at least one embodiment, the heat - exchange tubes or gasket heat exchangers in the second (fan) part 366 enable air to circulate for cooling the R2A heat exchanger 364 within the integrated or discrete features of the intelligent low - pressure two - phase cold plate with flow stabilization.

[0093] In at least one embodiment, the R2A with a flow-stabilized intelligent low-pressure two-phase cold plate is part of or incorporated within the rear door of the rack 302 (or 330). In at least one embodiment, a separate facility or main manifold 360 provides two-phase fluid between one or more R2A heat exchangers 364 and one or more racks 302. In at least one embodiment, the R2A heat exchanger 364 includes a plurality of channels instead of a plurality of tubes or plates for the two-phase fluid to pass through, in order to cool the two-phase fluid or dissipate the heat retained therein. In at least one embodiment, the data center cooling system can address the first cooling requirement of the rack 330 (or 302) in a first mode through the R2A heat exchanger 364 of the rack 330 (and its supporting infrastructure - such as a two-phase-capable cold plate and a compressor or pump 362). In at least one embodiment, in the first mode, the R2A heat exchanger 364 can be used to dissipate heat from the two-phase fluid of the cold plate via circulating air from the fan 366. In at least one embodiment, the data center cooling system can address the second cooling requirement of the rack 330 (or 302) in a second mode through an auxiliary cooling loop that engages with the CDU, the main coolant, and the cooling facility. In at least one embodiment, for high-density computing components, both modes are in operation for any cooling requirement determined for the rack.

[0094] In at least one embodiment, the first cooling requirement and the second cooling requirement can relate to different thermal characteristics of the data center. In at least one embodiment, the first cooling requirement can be associated with the heat generated from one or more computing devices, which can be addressed by the flow-stabilized feature of at least a buffer that can provide a varying volume (such as flow rate) or varying flow velocity of the two-phase fluid to address such first cooling requirement. In at least one embodiment, the second cooling requirement can also be associated with the heat generated from one or more computing devices, for example, by the heat retained in the two-phase fluid and / or the auxiliary coolant via the cold plate, and this heat may need to be dissipated through one or more of the R2A heat exchangers using condensation or compressor units and / or through the main coolant via the CDU. In at least one embodiment, the amount of heat generated, absorbed, extracted, or retained can be a temperature value that needs to be below an operating value or operating range; or needs to be maintained within an operating value or range.

[0095] In at least one embodiment, at least one processor may be provided to determine the temperature associated with the computing device 324 in the rack 330 (or 302). In at least one embodiment, the at least one processor is capable of causing the data center cooling system to operate in a first mode or a second mode at least in part based on the temperature associated with or determined from the computing device 324. In at least one embodiment, the at least one processor may cause the first mode of the data center cooling system to be capable of providing cooling using a first volume or flow rate of different volumes or different flow rates of a two-phase fluid. In at least one embodiment, such at least one processor may cause the second mode of the data center cooling system to be capable of providing cooling using a second volume or flow rate of different volumes or different flow rates of a two-phase fluid.

[0096] In at least one embodiment, the immersion-cooled server 352 within the rack 302 (or 330) may have its cooling requirements addressed concurrently with the air-cooled, coolant-cooled, or two-phase fluid-cooled servers 308 within the rack 302 (or 330). In at least one embodiment, the immersion-cooled server 352 may include a dielectric engineered fluid surrounding the computing device. In at least one embodiment, the immersion-cooled server 352 may include a second heat exchanger for exchanging heat between the dielectric engineered fluid and the two-phase fluid to be circulated in the R2A heat exchanger 364.

[0097] In at least one embodiment, at least one server tray or enclosure 308 (such as the bottom-most server tray or enclosure 308 in the rack 302) may be designated for a control system with a smart low-pressure two-phase cold plate with stable flow, such that if a two-phase fluid is used, such a system may be isolated from the auxiliary cooling loop. In at least one embodiment, the control system in the server tray or enclosure 308 may include safety features (such as sensors for providing sensor data or appropriate functions), communication features (for communicating with at least one flow controller in an active mode and with an external monitor), power features for powering one or more flow controllers and at least one processor (and its associated features), and control features provided by at least one processor that may be associated with at least one flow controller.

[0098] In at least one embodiment, the cold plate 326 can be associated with the computing device 324. In at least one embodiment, the cold plate can have a first port for a first portion of the microchannels that support the secondary coolant, which is different from a second portion of the microchannels that support the two-phase fluid of the R2A heat exchanger. In at least one embodiment, at least one processor can be adapted to receive sensor input from sensors associated with the computing device 324. In at least one embodiment, the sensors can also be associated with one or more of the rack, the secondary coolant, or the two-phase fluid. In at least one embodiment, at least one processor can be adapted to determine a first cooling requirement and a second cooling requirement based at least in part on the sensor input. In at least one embodiment, the sensor input can be a temperature sensed from the sensors as described at one or more time intervals. In at least one embodiment, at least one processor can cause the two-phase fluid loop to provide cooling for at least one computing device and use a buffer to provide flow stability for the two-phase fluid loop.

[0099] In at least one embodiment, one or more neural networks are adapted to receive sensor input from the provided sensors and are adapted to infer a first cooling requirement and a second cooling requirement of a data center cooling system, such as a two-phase fluid loop of a data center cooling system. In at least one embodiment, a flow controller of such a two-phase fluid loop implements different flow velocities or flow rates of the two-phase fluid therein. In at least one embodiment, at least one processor can cause at least one flow controller to enable the two-phase fluid to flow through the R2A heat exchanger and can be adapted to prevent the secondary coolant from flowing into the secondary cooling loop. In at least one embodiment, one or more diverter flow controllers 310C, 312C can be enabled to cause such flow and prevent the flow of the two-phase fluid and the secondary coolant. In at least one embodiment, the provided pipelines 310B, 312B can be provided to be fluidly coupled to the inlet pipeline and the outlet pipeline 370 of the R2A heat exchanger 364. In at least one embodiment, other flow controllers 368 on the R2A heat exchangers 340A, 340B can be enabled to prevent or cause the two-phase fluid to flow through the R2A heat exchanger 364.

[0100] In at least one embodiment, at least one processor may cause one or more flow controllers to control the flow rate and flow volume of a two-phase fluid when cooling within an R2A heat exchanger in a first mode, which is different from cooling based on an auxiliary cooling loop in an auxiliary cooling mode using both an auxiliary coolant and the two-phase fluid. In at least one embodiment, at least one processor may cause one or more flow controllers 368; 368A to control the flow rate and flow volume of the two-phase fluid when cooling within the R2A heat exchanger in a second mode, which may require more (such as a higher cooling demand) than the first mode. In at least one embodiment, one or more flow controllers 368A of buffer 372 may achieve more or less volume or flow rate of the two-phase fluid without any back pressure in a closed system. In at least one embodiment, similarly, one or more flow controllers 368A may throttle the flow of the two-phase fluid in a closed two-phase fluid loop. In at least one embodiment, electrical coupling may be provided to power at least one component of flow controllers 368; 368A. In at least one embodiment, at least one processor may be adapted to receive sensor input from sensors associated with at least one computing device (such as computing device 324). In at least one embodiment, at least one processor may determine a change in coolant state based at least in part on the sensor input. In at least one embodiment, the coolant state may relate to the temperature, flow rate, flow volume, or state (e.g., flowing or not flowing) of the coolant (or two-phase fluid).

[0101] In at least one embodiment, the coolant state may be sensed from an outlet or inlet of one or more of a cold plate, a rack, or a cooling manifold. In at least one embodiment, at least one processor may cause the data center cooling system to operate in the first mode, the auxiliary cooling mode, or the second mode based at least in part on the determined change in coolant state. In at least one embodiment, when it is determined that the coolant temperature at the outlet of the cold plate does not exceed a threshold (indicating that the associated computing device is not generating much heat), the first mode may be enabled to cause the two-phase fluid to flow through the R2A heat exchanger and the appropriate cold plate. In at least one embodiment, this enables an economical use of the data center cooling system to provide cooling from one or more of the auxiliary cooling loop or the R2A heat exchanger.

[0102] In at least one embodiment, when the temperature at the hot aisle of the rack, near the computing device, or of the fluid (secondary coolant or local coolant) is determined to exceed a threshold (indicating that the associated computing device is generating more heat than can be handled by standalone forced air), the second cooling mode or even the secondary cooling mode of the data center cooling system can be enabled to use more two-phase fluid or a higher flow rate of two-phase fluid, or assistance from a secondary cooling loop to provide cooling for the computing device. In at least one embodiment, in addition to the first mode or the second mode that has been provided to cool at least one computing device via the R2A heat exchanger, the secondary cooling mode also engages or enables a secondary cooling loop, the R2A heat exchanger having a two-phase fluid circulating from a cold plate associated with at least one computing device to provide more cooling than the cooling provided by the secondary cooling loop.

[0103] In at least one embodiment, the R2A heat exchanger is engaged or associated with at least one cold plate to absorb heat from at least one computing device using a two-phase fluid. In at least one embodiment, the R2A heat exchanger is further engaged or associated with a condensing or compressor unit, and with a buffer between the condensing or compressor unit and the cold plate and its evaporator section. In at least one embodiment, the condensing or compressor unit can cause at least a portion of the heat to be dissipated from the two-phase fluid to an area within the data center, such as above the racks of the data center or in the hot aisle of the data center. In at least one embodiment, before being associated or interfaced with the coils or plates of the R2A heat exchanger, the condensing or compressor unit includes a pump or compressor and an associated flow controller (e.g., valve) and pipelines.

[0104] In at least one embodiment, as Figure 4 shown, the data center-level feature 400 can be associated with an intelligent low-pressure two-phase cold plate with flow stabilization for the data center cooling system. In at least one embodiment, the data center-level feature 400 within the data center 402 can include: racks 404 for hosting one or more server trays or enclosures; one or more CDU 406 for exchanging heat between a secondary cooling loop 412 and a primary cooling loop 422; one or more row manifolds 410 for distributing coolant from the CDU 406; and associated various flow controllers 420, as well as inlet and outlet pipelines 412, 414, 416, 418.

[0105] In at least one embodiment, an intelligent low-pressure two-phase cold plate with stable flow is provided in association with a rack 404 in a data center 402 or the back door of each provided rack 404. In at least one embodiment, the channel behind the rack 404 is a hot channel for discharging heat from at least one computing device in at least one rack 404 via a condensation or compressor unit (shown together as unit 432 or 434) associated with an R2A heat exchanger during a first operating mode of the data center cooling system. In at least one embodiment, the condensation or compressor unit associated with the R2A heat exchanger (shown together as unit 432 or 434) can be provided together with a two-phase fluid manifold 430 so that heat can be dissipated from the R2A heat exchanger to the ceiling area of the data center, where it can be discharged from the data center. In at least one embodiment, one or more buffers 432A, 434A can be provided for stabilizing the flow of the two-phase fluid from the R2A heat exchanger of unit 432 or 434. In at least one embodiment, different racks 404 of the data center cooling system can cooperatively have intelligent low-pressure two-phase cold plates with stable flow for liquid cooling. In at least one embodiment, a two-phase fluid manifold 430 can be provided to directly supply the two-phase fluid to the cold plates of the server trays or enclosures of the rack 404.

[0106] In at least one embodiment, different row manifolds 410 can be associated with different racks. In at least one embodiment, different coolants can be chemically matched or mismatched relative to an auxiliary coolant. In at least one embodiment, depending on the chemistry of the different auxiliary coolants used with each of the provided different CDUs, different fluid sources are provided to the different CDUs as a redundancy feature. In at least one embodiment, there is no need to have an auxiliary cooling loop and CDU for one or more racks 404, and instead, the intelligent two-phase fluid R2A heat exchanger can be sufficient to provide cooling for the rack 404. In at least one embodiment, these racks not associated with an auxiliary cooling loop can be adequately addressed by an intelligent low-pressure two-phase cold plate with stable flow.

[0107] In at least one embodiment, the rack 404 can be associated with at least one processor for operating an intelligent low-pressure two-phase cold plate with stable flow. In at least one embodiment, the processor can include one or more circuits. In at least one embodiment, one or more circuits of the processor can be adapted to determine the cooling requirements of the data center cooling system. In at least one embodiment, the processor can cause the first operating mode or the second operating mode of the data center cooling system to address a first cooling requirement and a second cooling requirement by exchanging heat between the cold plate and the R2A heat exchanger via a buffer and using a two-phase fluid through the R2A heat exchanger.

[0108] In at least one embodiment, such operations can be independent of the secondary coolant and the primary coolant from the cooling facility 408. In at least one embodiment, the processor can cause the secondary cooling operation mode of the data center cooling system to address further cooling requirements (compared to the first or second cooling requirements addressed by the two-phase fluid) through a secondary cooling loop having a row manifold 410, flow controllers 416, 418, and a CDU 406, which in turn is coupled to a primary cooling loop 422 having a cooling facility 408.

[0109] In at least one embodiment, the two-phase fluid cooling loop can be more economical than the secondary cooling loop, but the secondary cooling loop can address higher cooling requirements than the two-phase fluid cooling loop. In at least one embodiment, all cooling modes are made to occur concurrently for the provided racks 404. In at least one embodiment, a gasket or tube heat exchanger can be used as a cold plate to support the secondary coolant and the two-phase fluid differently.

[0110] In at least one embodiment, a processor used with an intelligent low-pressure two-phase cold plate with flow stabilization includes an output for providing signals to one or more flow controllers. In at least one embodiment, one or more flow controllers can cause the two-phase fluid to flow through the R2A heat exchanger and the buffer zone, and can prevent the secondary coolant from flowing into the secondary cooling loop in the mode of the data center cooling system, such that the intelligent low-pressure two-phase cold plate with flow stabilization provides a single cooling source in the rack. In at least one embodiment, this feature enables the use of an isolated intelligent low-pressure two-phase cold plate with flow stabilization without a secondary cooling loop, a primary cooling loop, a CDU, and an associated cooling tower. In at least one embodiment, such cooling can be provided for a period of time until any problems in the primary cooling loop have been resolved. In at least one embodiment, such cooling can have a capacity defined by the downtime in a service level agreement (SLA).

[0111] In at least one embodiment, a processor used with an intelligent low-pressure two-phase cold plate with flow stabilization includes an input for receiving sensor input from sensors associated with at least one computing device of the rack 404. In at least one embodiment, the sensors can be associated with the rack, the secondary coolant, or the two-phase fluid of the associated cold plate from the rack concurrently or individually. In at least one embodiment, the processor can determine a first cooling requirement and a second cooling requirement based in part on the sensor input from these associated sensors. In at least one embodiment, based in part on the sensor input from these associated sensors, the flow rate or flow of one or more of the primary coolant, the secondary coolant, or the two-phase fluid can be adjusted through the cold plate (for the secondary coolant), through the CDU (for the primary coolant), or through the R2A heat exchanger and the two-phase adapted cold plate (for the two-phase fluid).

[0112] In at least one embodiment, one or more neural networks may be provided within at least one processor to receive sensor inputs and infer a first cooling requirement and a second cooling requirement from a computing device or aspect of a data center cooling system. In at least one embodiment, one or more neural networks may infer a failure of an auxiliary cooling loop or a primary cooling loop. In at least one embodiment, based in part on sensor inputs associated with flow rate, flow volume, temperature, humidity, and leakage, one or more circuits of the processor may cause one or more flow controllers to support a first cooling mode, a second cooling mode, or an auxiliary cooling mode.

[0113] In at least one embodiment, a processor used with a rack 404 and an intelligent low-pressure two-phase cold plate with flow stabilization includes one or more circuits. In at least one embodiment, one or more circuits of the processor may cause a first mode, a second mode, or an auxiliary cooling mode in different operating modes for a data center cooling system. In at least one embodiment, causing the first mode, the second mode, or the auxiliary cooling mode means causing the data center cooling system to operate in the first mode, the second mode, or the auxiliary cooling mode.

[0114] In at least one embodiment, a data center cooling system includes an R2A heat exchanger for a two-phase fluid cooling loop. In at least one embodiment, one or more circuits of a processor may be provided to train one or more neural networks to infer cooling requirements from sensor inputs of sensors associated with a rack, a computing device, an auxiliary coolant, or a two-phase fluid from at least one cold plate from the rack. In at least one embodiment, the processor may cause the cold plate to use an evaporator within the cold plate to provide cooling for the computing device. In at least one embodiment, such cooling may be to remove heat from the computing device by a two-phase fluid flowing through the evaporator within the cold plate. In at least one embodiment, as the two-phase fluid absorbs or removes heat from the computing device, it becomes a gas phase. In at least one embodiment, the evaporator may be associated with a buffer to perform flow stabilization before the two-phase fluid enters the cold plate. In at least one embodiment, the flow stabilization may be represented by different volumes or different flow rates of the two-phase fluid that are enabled to flow between a condensation or compressor unit located outside the cold plate and the evaporator.

[0115] In at least one embodiment, the output of a processor used with an intelligent low-pressure two-phase cold plate having flow stabilization may be adapted to provide a signal to one or more flow controllers. In at least one embodiment, this enables two-phase fluid to flow through the R2A heat exchanger and enables prevention of auxiliary coolant flow into the auxiliary cooling loop in a first mode or a second mode of the data center cooling system. In at least one embodiment, such an output may be used to control the flow rate and / or velocity of two-phase fluid from a buffer. In at least one embodiment, the auxiliary cooling loop is not used with an intelligent low-pressure two-phase cold plate having flow stabilization; however, when used, at least one shunt flow controller may be used to cause two-phase fluid to flow between the cold plate and the R2A heat exchanger or to cause auxiliary coolant to flow between the cold plate and the CDU, for concurrent or separate use with an intelligent low-pressure two-phase cold plate having flow stabilization. In at least one embodiment, one or more flow controllers associated with the buffer of an intelligent low-pressure two-phase cold plate having flow stabilization may be controlled by such an output to support different flow rates or velocities of two-phase fluid therethrough.

[0116] In at least one embodiment, one or more neural networks of a processor may be adapted to receive sensor inputs. In at least one embodiment, one or more neural networks may be trained to infer a first cooling demand and a second cooling demand as part of an analysis of previous sensor inputs and previous cooling demands. In at least one embodiment, one or more neural networks may be trained with relevant data of previous sensor inputs and previous cooling demands such that new sensor inputs within a threshold of the previous sensor inputs may be related to the previous cooling demands or changes thereof.

[0117] In at least one embodiment, the output of a processor used with an intelligent low-pressure two-phase cold plate having flow stabilization may be adapted to provide a signal to cause one or more flow controllers to be adjusted in a first mode such that two-phase fluid flow occurs in a first mode or a second mode, different from the auxiliary coolant flow that occurs in an auxiliary cooling mode. In at least one embodiment, depending on which mode is active, the flow rate or volume of two-phase fluid to the R2A heat exchanger may be increased or decreased.

[0118] In at least one embodiment, the input of a processor used with an intelligent low-pressure two-phase cold plate having stable flow is adapted to receive sensor input associated with the temperature of at least one computing device, auxiliary coolant, or two-phase fluid exiting the cold plate. In at least one embodiment, one or more neural networks of the processor can be trained to reason about a change in coolant state that has occurred, based at least in part on the temperature and previous temperature of at least one computing device, auxiliary coolant, or two-phase fluid. In at least one embodiment, one or more circuits of the processor can be adapted to cause a first mode, a second mode, or an auxiliary cooling mode of operation for a data center cooling system. In at least one embodiment, one or more circuits can use a buffer, cold plate, and condensation or compressor unit to enable or disable a two-phase fluid circuit.

[0119] In at least one embodiment, a processor used with an intelligent low-pressure two-phase cold plate having stable flow includes one or more circuits for causing a first mode, a second mode, or an auxiliary cooling mode of operation for a data center cooling system. In at least one embodiment, one or more circuits or the processor will include one or more neural networks for reasoning about cooling requirements from sensor input of sensors associated with rack 404 or with auxiliary coolant or two-phase fluid from at least one cold plate. In at least one embodiment, the processor can be adapted to cause the first mode or second mode to address a first or second cooling requirement by flowing the two-phase fluid through the R2A heat exchanger at one or more flow rates or volumes. In at least one embodiment, the processor can be adapted to also cause the auxiliary cooling mode to address a further cooling requirement of the auxiliary cooling circuit and CDU to cool the fluid circulated from the cold plate.

[0120] In at least one embodiment, throughout Figures 1 - 4Each of the at least one described processors has inference and / or training logic 1815, which can include but is not limited to: code and / or data storage 1801 for storing and / or forwarding output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 1815 can include or be coupled to the code and / or data storage 1801 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information can be loaded to configure the logic, which includes integer and / or floating-point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weights or other parameter information into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, the code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of the neural network used or trained in combination with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any part of the code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0121] In at least one embodiment, the inference and / or training logic 1815 of at least one processor can be part of a building management system (BMS) for controlling traffic controllers at one or more of the server level, rack level, and row level. In at least one embodiment, determination of engagement with traffic controllers associated with an auxiliary cooling loop, intelligent low-pressure two-phase cold plates with flow stabilization, CDU, cold plates, or other cooling manifolds can be provided to one or more neural networks of the inference and / or training logic 1815 such that the one or more neural networks reason from the R2A heat exchanger or auxiliary cooling loop of the data center cooling system the coolant requirements for one or more cold plates, servers, or racks to gracefully engage or disengage which traffic controllers. In at least one embodiment, an increase or decrease in the fluid flow rate through the R2A heat exchanger can be achieved by a traffic controller controlled by the inference and / or training logic 1815 of at least one processor associated with control logic associated with a local cooling loop.

[0122] In at least one embodiment, at least one processor may be associated with a local cooling loop and with an auxiliary cooling loop. In at least one embodiment, at least one processor may be associated with an intelligent low-pressure two-phase cold plate with flow stabilization. In at least one embodiment, at least one processor includes control logic such as inference and / or training logic 1815, which is associated with at least one flow controller. In at least one embodiment, at least one flow controller may have its own respective processor or microcontroller. In at least one embodiment, the processor or microcontroller executes instructions sent to it from the control logic. In at least one embodiment, the control logic can be used to determine changes in coolant status, such as a fault in an auxiliary cooling loop (such as a CDU and a cooling manifold) or a primary cooling loop (such as a cooling facility, a cooling manifold, and an associated CDU). In at least one embodiment, a fault may also occur for a cooling manifold that needs to be replaced. In at least one embodiment, the control logic can cause at least one flow controller to provide a response, such as by engaging a two-phase fluid cooling loop having a condensing or compressor unit, a two-phase fluid, and a supportive cold plate to provide cooling for at least one computing device.

[0123] In at least one embodiment, the control logic can cause a first signal to at least one flow controller to enable the stoppage of auxiliary coolant from the auxiliary cooling loop as part of a coolant response. In at least one embodiment, the control logic can cause a second signal to at least one flow controller to enable the start of a two-phase fluid from the two-phase fluid cooling loop as part of a response. In at least one embodiment, the control logic can receive sensor input from sensors associated with the auxiliary coolant, the two-phase fluid, and / or at least one computing device of the CDU. In at least one embodiment, at least one processor can determine a change in coolant status based in part on the sensor input. In at least one embodiment, one or more neural networks of the inference and / or training logic 1815 can be adapted to receive the sensor input and infer a change in coolant status.

[0124] In at least one embodiment, at least one processor can include one or more circuits for one or more neural networks, such as the inference and / or training logic 1815. In at least one embodiment, the inference and / or training logic 1815 can be adapted to infer a change in coolant status from sensor input associated with at least one server or at least one rack, such as coolant from the CDU being ineffective or retaining too much heat when entering the rack. In at least one embodiment, one or more circuits can be adapted to cause at least one flow controller to provide a response from the two-phase fluid cooling loop.

[0125] In at least one embodiment, control logic associated with one or more circuits may cause a first signal (along with any associated signals) to at least one flow controller to respond to a secondary cooling loop or a two-phase fluid cooling loop with an intelligent low-pressure two-phase cold plate with flow stabilization. In at least one embodiment, a second signal may be provided to at least the flow controller and may also enable only the R2A heat exchanger in a different mode without a secondary cooling loop, but the secondary cooling loop may be engaged or activated if further cooling is required. In at least one embodiment, a distributed or integrated architecture is enabled by one or more circuits of at least one processor. In at least one embodiment, the distributed architecture may be supported by circuits located differently in one or more circuits.

[0126] In at least one embodiment, one or more neural networks of the inference and / or training logic 1815 may be adapted to infer an increase or decrease in the cooling requirements of at least one computing component of at least one server. In at least one embodiment, one or more circuits may be adapted to cause a cooling loop to economically address a reduced cooling requirement or supplement an increased cooling requirement for at least one computing component. In at least one embodiment, enabling the cooling loop represents that a response from the two-phase fluid cooling loop partially pre-empts a corresponding increase or corresponding decrease in the cooling requirements of at least one computing component of at least one server based on the workload sent to at least one computing component.

[0127] In at least one embodiment, at least one processor includes one or more circuits (such as the inference and / or training logic 1815) for training one or more neural networks to make inferences from the provided data. In at least one embodiment, the inference and / or training logic 1815 may infer a change in the coolant state from sensor inputs associated with at least one server or at least one rack. In at least one embodiment, inferences may be used to enable one or more circuits to cause at least one flow controller of the two-phase fluid cooling loop to provide a response. In at least one embodiment, the response may be to cause a two-phase fluid response from the two-phase fluid cooling loop to absorb heat into the two-phase fluid and exchange the absorbed heat to the environment via a condensing or compressor unit with a fan rather than a secondary cooling loop with a CDU.

[0128] In at least one embodiment, one or more circuits may be adapted to train one or more neural networks to infer an increase or decrease in the cooling requirements of at least one computing component of at least one server. In at least one embodiment, one or more circuits may be adapted to train one or more neural networks to infer an increase or decrease in the flow output from a secondary cooling loop associated with an inappropriate flow of secondary coolant due to a CDU failure or a corresponding increase or decrease in the power requirements of at least one computing component of at least one server.

[0129] In at least one embodiment, one or more neural networks can be trained to make inferences based on previously associated thermal characteristics or cooling requirements from a computing device, server, or rack, and the cooling capacity or ability indicated by the fluid source of a local cooling loop (such as through an intelligent low-pressure two-phase cold plate with stable flow), where the intelligent low-pressure two-phase cold plate has a specific cooling capacity that is higher than forced air cooling capacity but can be lower than the cooling capacity of an auxiliary cooling loop. In at least one embodiment, the previously satisfied cooling requirements of the two-phase fluid cooling loop can be used to enable one or more neural networks to make similar inferences about future similar cooling requirements (taking into account small variations therefrom) that are satisfied by engaging the two-phase fluid cooling loop at different flow rates or velocities by adjusting one or more flow controllers.

[0130] Figure 5 A method 500 associated with a Figures 2 - 4 data center cooling system according to at least one embodiment is shown. In at least one embodiment, method 500 includes step 502 of providing a cold plate having an evaporator to remove heat from at least one computing device using a two-phase fluid. In at least one embodiment, step 504 is for effecting the determination or determination of the cooling requirements of at least one computing device of a rack. In at least one embodiment, step 506 is for verifying the at least one cooling requirement of at least one computing device. In at least one embodiment, step 508 is for enabling the cold plate to absorb heat from at least one computing device using a two-phase fluid. In at least one embodiment, step 510 is for enabling a buffer to perform flow stabilization represented by different volumes or different flow rates of the two-phase fluid, which is enabled to flow between the evaporator and a condensation or compressor unit located external to the cold plate. In at least one embodiment, if step 506 determines that there are no further cooling requirements for at least one computing device or the existing cooling requirements have not changed, step 504 can be repeated.

[0131] In at least one embodiment, method 500 can include a further step or sub-step of using at least one processor to determine the temperature associated with at least one computing device in a rack. In at least one embodiment, method 500 can include a further step or sub-step of using the temperature associated with at least one computing device in a rack to determine a first cooling requirement or a second cooling requirement. In at least one embodiment, method 500 can include a further step or sub-step of causing a two-phase fluid loop or an auxiliary cooling loop to be engaged based at least in part on the first cooling requirement or the second cooling requirement. In at least one embodiment, such an auxiliary cooling loop can be associated with a main cooling loop.

[0132] In at least one embodiment, method 500 may include further steps or sub-steps for receiving, in at least one processor, sensor input from sensors associated with at least one computing device, rack, secondary coolant, or two-phase fluid. In at least one embodiment, method 500 may include further steps or sub-steps for using at least one processor to determine a first cooling requirement and a second cooling requirement, at least in part based on the sensor input received by the at least one processor. In at least one embodiment, method 500 may include further steps or sub-steps for enabling an R2A heat exchanger to dissipate heat into a hot aisle within a data center. In at least one embodiment, method 500 may include further steps or sub-steps for receiving, by at least one processor, sensor input from sensors associated with at least one computing device. In at least one embodiment, method 500 may include further steps or sub-steps for determining, by at least one processor, a change in coolant state, at least in part based on the sensor input received therein. In at least one embodiment, method 500 may include further steps or sub-steps for causing a two-phase fluid loop to be implemented using a buffer, cold plate, and condensation or compressor unit, at least in part based on the determined change in coolant state.

[0133] Servers and Data Centers

[0134] The following figures illustrate, but are not limited to, systems based on exemplary network servers and data centers that may be used to implement at least one embodiment.

[0135] Figure 6 A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, the distributed system 600 includes one or more client computing devices 602, 604, 606, and 608 configured to execute and operate client applications, such as a web browser, a proprietary client, and / or variants thereof, over one or more networks 610. In at least one embodiment, a server 612 may be communicatively coupled to remote client computing devices 602, 604, 606, and 608 via the network 610.

[0136] In at least one embodiment, server 612 may be adapted to run one or more services or software applications, such as services and applications that can manage session activities for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 612 may also provide other services, or software applications, which may include non-virtual and virtual environments. In at least one embodiment, these services may be provided to users of client computing devices 602, 604, 606, and / or 608 as web-based services or cloud services or under a software as a service (SaaS) model. In at least one embodiment, users operating client computing devices 602, 604, 606, and / or 608 may in turn utilize one or more client applications to interact with server 612 to utilize the services provided by these components.

[0137] In at least one embodiment, software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or services provided by these components may also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices may then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components may be implemented in hardware, firmware, software, or a combination thereof. It should be understood that various different system configurations are possible, which may be different from distributed system 600. Thus, Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0138] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 may include different types of computing systems. In at least one embodiment, client computing devices may include portable handheld devices (e.g., cellular phones, computing tablets, personal digital assistants (PDAs)) or wearable devices (e.g., Google head-mounted displays), running software such as Microsoft Windows ) and / or various mobile operating systems (such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS and / or their variants). In at least one embodiment, the device may support different applications, such as different Internet-related applications, email, Short Message Service (SMS) applications, and may use various other communication protocols. In at least one embodiment, the client computing device may also include a general-purpose personal computer, and in at least one embodiment, the general-purpose personal computer includes a personal computer and / or a laptop computer running various versions of Microsoft Apple and / or a Linux operating system.

[0139] In at least one embodiment, the client computing device may be a workstation computer running any of various commercially available or UNIX-like operating systems, including but not limited to various GNU / Linux operating systems, such as Google Chrome OS. In at least one embodiment, the client computing device may also include an electronic device capable of communicating through one or more networks 610, such as a thin client computer, an Internet-enabled gaming system (e.g., a Microsoft Xbox gaming console with or without a gesture input device), and / or a personal messaging device. Although Figure 6 the distributed system 600 in is shown as having four client computing devices, any number of client computing devices may be supported. Other devices (such as devices with sensors, etc.) may interact with the server 612.

[0140] In at least one embodiment, the network 610 in the distributed system 600 may be any type of network capable of supporting data communication using any of various available protocols, including but not limited to TCP / IP (Transmission Control Protocol / Internet Protocol), SNA (System Network Architecture), IPX (Internetwork Packet Exchange), AppleTalk and / or their variants. In at least one embodiment, the network 610 may be a Local Area Network (LAN), an Ethernet-based network, Token Ring, a Wide Area Network, the Internet, a virtual network, a Virtual Private Network (VPN), an intranet, an extranet, a Public Switched Telephone Network (PSTN), an infrared network, a wireless network (e.g., a network operating under any one of the Institute of Electrical and Electronics Engineers (IEEE) 802.11 protocol family, and / or any other wireless protocol), and / or any combination of these and / or other networks.

[0141] In at least one embodiment, server 612 may be composed of one or more general-purpose computers, dedicated server computers (in at least one embodiment, including PC (personal computer) servers, servers, midrange servers, mainframe computers, rack-mounted servers, etc.), server farms, server clusters, or any other suitable arrangement and / or combination. In at least one embodiment, server 612 may include one or more virtual machines running a virtual operating system or other computing architectures involving virtualization. In at least one embodiment, one or more flexible logical storage device pools may be virtualized to maintain virtual storage devices for the server. In at least one embodiment, a virtual network may be controlled by server 612 using software-defined networking. In at least one embodiment, server 612 may be adapted to run one or more services or software applications.

[0142] In at least one embodiment, server 612 may run any operating system, as well as any commercially available server operating system. In at least one embodiment, server 612 may also run any of a variety of additional server applications and / or middleware applications, including HTTP (Hypertext Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, servers, database servers, and / or their variants. In at least one embodiment, exemplary database servers include, but are not limited to, those commercially available from Oracle, Microsoft, Sybase, IBM (International Business Machines), and / or their variants.

[0143] In at least one embodiment, server 612 may include one or more applications for analyzing and merging data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates may include, but are not limited to, feeds received from one or more third-party information sources and continuous data streams, feeds, updates, or real-time updates, which may include real-time events related to sensor data applications, financial quote providers, network performance measurement tools (e.g., network monitoring and business management applications), clickstream analysis tools, automotive traffic monitoring, and / or their variations. In at least one embodiment, server 612 may also include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0144] In at least one embodiment, the distributed system 600 may further include one or more databases 614 and 616. In at least one embodiment, the databases may provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 may reside in various locations. In at least one embodiment, one or more of databases 614 and 616 may reside on a non-transitory storage medium local to (and / or within) server 612. In at least one embodiment, databases 614 and 616 may be remote from server 612 and communicate with server 612 via a network-based connection or a dedicated connection. In at least one embodiment, databases 614 and 616 may reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing the functions attributed to server 612 may be stored locally on server 612 and / or remotely as appropriate. In at least one embodiment, databases 614 and 616 may include relational databases, such as databases adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0145] Figure 7 An exemplary data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, but is not limited to, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0146] In at least one embodiment, as Figure 7 shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“node C.R.”) 716(1)-716(N), where “N” represents any whole positive integer. In at least one embodiment, node C.R. 716(1)-716(N) may include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (“FPGA”), graphics processors, etc.), memory devices (e.g., dynamic random access memory), storage devices (e.g., solid state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of node C.R. 716(1)-716(N) may be servers having one or more of the above computing resources.

[0147] In at least one embodiment, the grouped computing resources 714 may include separate groupings (not shown) of node C.R.s housed within one or more racks, or numerous racks (also not shown) within data centers at various geographical locations. Separate groupings of node C.R.s within the grouped computing resources 714 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0148] In at least one embodiment, the resource coordinator 712 may configure or otherwise control one or more node C.R.s 716(1)-716(N) and / or the grouped computing resources 714. In at least one embodiment, the resource coordinator 712 may include a software design infrastructure (“SDI”) management entity for the data center 700. In at least one embodiment, the resource coordinator 712 may include hardware, software, or some combination thereof.

[0149] In at least one embodiment, as Figure 7As shown, the framework layer 720 includes, but is not limited to, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework that supports software 752 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 752 or the application 742 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 738 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of the workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and the distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 is capable of managing the cluster or grouped computing resources mapped to or allocated for supporting the distributed file system 738 and the job scheduler 732. In at least one embodiment, the cluster or grouped computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0150] In at least one embodiment, the software 752 included in the software layer 730 may include software used by at least a portion of the nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0151] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of applications may include, but are not limited to, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variants thereof.

[0152] In at least one embodiment, any one of the configuration manager 734, the resource manager 736, and the resource coordinator 712 can implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions can relieve the data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilization and / or poorly performing parts of the data center.

[0153] Figure 8 A client-server network 804 formed by a plurality of interconnected network server computers 802 is shown in accordance with at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible to other network server computers 802 and to client computers 806 and networks 808 linked to the wide area network 804. In at least one embodiment, the configuration of the client-server network 804 can change over time as client computers 806 and one or more networks 808 are connected to and disconnected from the network 804, and as one or more backbone server computers 802 are added to or removed from the network 804. In at least one embodiment, the client-server network includes such client computers 806 and networks 808 when the client computers 806 and networks 808 are connected to the network server computers 802. In at least one embodiment, the term computer includes any device or machine capable of accepting data, applying a prescribed process to the data, and providing the result of the process.

[0154] In at least one embodiment, the client-server network 804 stores information accessible to the network server computer 802, the remote network 808, and the client computer 806. In at least one embodiment, the network server computer 802 is formed by a mainframe computer, a minicomputer, and / or a microcomputer each having one or more processors. In at least one embodiment, the server computers 802 are linked together by wired and / or wireless transmission media such as wires, fiber optic cables, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, the client computer 806 accesses the network server computer 802 via a similar wired or wireless transmission media. In at least one embodiment, the client computer 806 can be linked to the client-server network 804 using a modem and a standard telephone communication network. In at least one embodiment, alternative carrier systems such as cable and satellite communication systems can also be used to link to the client-server network 804. In at least one embodiment, other private or time-sharing carrier systems can be used. In at least one embodiment, the network 804 is a global information network such as the Internet. In at least one embodiment, the network is a private intranet that uses a protocol similar to the Internet but has additional security measures and restricted access controls. In at least one embodiment, the network 804 is a private or semi-private network that uses a proprietary communication protocol.

[0155] In at least one embodiment, the client computer 806 is any end-user computer and can also be a mainframe computer, a minicomputer, or a microcomputer having one or more microprocessors. In at least one embodiment, the server computer 802 can sometimes be used as a client computer accessing another server computer 802. In at least one embodiment, the remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transmission media having a fixed or time-varying configuration. In at least one embodiment, the client computer 806 can be linked to and access the network 804 independently or via the remote network 808.

[0156] Figure 9A computer network 908 that connects one or more computing machines according to at least one embodiment is shown. In at least one embodiment, network 908 can be any type of electrically connected group of computers, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, the connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Data Link Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communication protocol. In at least one embodiment, the computing devices linked to the network can be desktop computers, servers, portable, handheld, set-top boxes, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, depending on their functionality, network-connected devices can vary widely in processing power, internal memory, and other performance aspects.

[0157] In at least one embodiment, the communication within the network and the communication to or from the computing devices connected to the network can be wired or wireless. In at least one embodiment, network 908 can at least partially include the worldwide public Internet, which generally connects multiple users according to the client-server model according to the Transmission Control Protocol / Internet Protocol (TCP / IP) specification. In at least one embodiment, the client-server network is the dominant model for communication between two computers. In at least one embodiment, a client computer ("client") issues one or more commands to a server computer ("server"). In at least one embodiment, the server fulfills the client commands by accessing available network resources and returning information to the client according to the client commands. In at least one embodiment, the client computer system and the network resources residing on the network server are assigned network addresses for identification during communication between the elements of the network. In at least one embodiment, the communication from other network-connected systems to the server will include the network address of the relevant server / network resource as part of the communication, so that the appropriate destination of the data / request is identified as the recipient. In at least one embodiment, when network 908 includes the global Internet, the network address is an IP address in TCP / IP format, which can at least partially route data to an email account, a website, or other Internet tools residing on the server. In at least one embodiment, the information and services residing on the network server can be available to the web browser of the client computer through a domain name (e.g., www.site.com), which maps to the IP address of the network server.

[0158] In at least one embodiment, multiple clients 902, 904, and 906 are connected to network 908 via respective communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via a dial-up modem connection, a cable link, a Digital Subscriber Line (DSL), a wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908, such as a personal computer (PC), a workstation, a dedicated terminal, a Personal Digital Assistant (PDA), or other similar device. In at least one embodiment, clients 902, 904, and 906 may or may not be located in the same geographical area.

[0159] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients communicating with network 918. In at least one embodiment, each server is generally a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, the server includes computer-readable data storage media for storing program instructions and data, such as a hard disk drive and RAM memory. In at least one embodiment, servers 910, 912, 914 run application programs in response to client commands. In at least one embodiment, server 910 can run a web server application for responding to client requests for HTML pages and can also run a mail server application for receiving and routing email. In at least one embodiment, other application programs, such as an FTP server or a media server for streaming audio / video data to clients, can also be run on server 910. In at least one embodiment, different servers can be dedicated to performing different tasks. In at least one embodiment, server 910 can be a dedicated web server for managing website-related resources for different users, while server 912 can be dedicated to providing email management. In at least one embodiment, other servers can be dedicated to media (audio, video, etc.), File Transfer Protocol (FTP), or a combination of any two or more services typically available or provided over the network. In at least one embodiment, each server can be located at the same or a different location from other servers. In at least one embodiment, multiple servers can perform mirror tasks for users, thereby alleviating congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider in the business of maintaining and delivering third-party content over network 918.

[0160] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which may be referred to as a browser, requests content such as web pages, email messages, video clips, etc. from servers 910, 912, 914. In at least one embodiment, a second type, which may be referred to as a user, hires the web hosting provider to maintain a network resource such as a website and make it available to browsers. In at least one embodiment, the user contracts with the web hosting provider to make memory space, processor capacity, and communication bandwidth available for their desired network resource according to the amount of server resources the user desires to utilize.

[0161] In at least one embodiment, in order for the web hosting provider to serve these two clients, the application that manages the network resources hosted by the server must be appropriately configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application's response to browser requests and also at least partially define the server resources available to a particular user.

[0162] In one embodiment, an intranet server 916 communicates with a network 908 via a communication link. In at least one embodiment, the intranet server 916 communicates with a server manager 918. In at least one embodiment, the server manager 918 includes a database of application configuration parameters used in servers 910, 912, 914. In at least one embodiment, the user modifies the database 920 via the intranet 916, and the server manager 918 interacts with servers 910, 912, 914 to modify the application parameters so that they match the content of the database. In at least one embodiment, the user logs into the intranet 916 by connecting to the intranet 916 via a computer 902 and entering authentication information such as a username and password.

[0163] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that permits the user to access configuration parameters for a specific application. In at least one embodiment, a plurality of modifiable text boxes are presented to the user that describe aspects of the configuration of the user's website or other network resources. In at least one embodiment, if the user desires to increase the memory space reserved on the server for their website, a field is provided to the user in which the user specifies the desired memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards the information to the appropriate server and uses the new parameters during application operation. In at least one embodiment, the intranet server 916 is configured to provide the user with access to the configuration parameters of the hosted network resources (e.g., web pages, email, FTP sites, media sites, etc.) that the user has contracted with a web hosting service provider for.

[0164] Figure 10A A networked computer system 1000A is shown in accordance with at least one embodiment. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computer or node 1002 includes a processor 1014, a memory 1016, a camera 1004, a microphone 1006, a mouse 1008, speakers 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 may each run one or more desktop servers, such as an internal network within a given company, or may be servers of a general network not limited to a specific environment. In at least one embodiment, each PC node of the network has a server such that each PC node of the network represents a specific network server with a specific network URL address. In at least one embodiment, each server defaults to the default web page for the users of that server, which default web page itself may contain embedded URLs that point to further sub-pages for that user on that server, or to other servers on the network or pages on other servers.

[0165] In at least one embodiment, nodes 1002, 1018, 1020 and other nodes of the network are interconnected via medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as Integrated Services Digital Network (“ISDN”). In at least one embodiment, the various nodes of the networked computer system can be connected via various communication media, including local area network (“LAN”), plain old telephone service (“POTS”) (sometimes referred to as the Public Switched Telephone Network (“PSTN”)), and / or variants thereof. In at least one embodiment, the various nodes of the network can also constitute users of computer systems interconnected via a network such as the Internet. In at least one embodiment, each server on the network (operating from a particular node of the network at a given instance) has a unique address or identification within the network, and the unique address or identification can be specified according to a URL.

[0166] In at least one embodiment, multiple Multipoint Control Units (“MCUs”) can thus be used to transmit data to and from the various nodes or “endpoints” of the conferencing system. In at least one embodiment, in addition to various other communication media (such as nodes connected via the Internet), the nodes and / or MCUs can be interconnected via an ISDN link or via a local area network (“LAN”). In at least one embodiment, the nodes of the conferencing system can generally be directly connected to a communication medium such as a LAN or connected via an MCU, and the conferencing system can include other nodes or elements such as routers, servers, and / or variants thereof.

[0167] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, the processors of the nodes of networked computer system 1000A can also be dedicated video processors. In at least one embodiment, the different peripheral devices and components of the nodes (such as those of node 1002) can be different from those of other nodes. In at least one embodiment, node 1018 and node 1020 can be configured to be the same as or different from node 1002. In at least one embodiment, in addition to PC systems, the nodes can also be implemented on any suitable computer system.

[0168] Figure 10BShows a networked computer system 1000B according to at least one embodiment. In at least one embodiment, system 1000B shows a network (such as LAN 1024) that can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a plurality of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, the nodes can also be connected to the LAN via a network server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, and for at least one embodiment, it includes routers, servers, and nodes.

[0169] Figure 10C Shows a networked computer system 1000C according to at least one embodiment. In at least one embodiment, system 1000C shows a WWW system having communication across a backbone communication network (such as Internet 1032), and the backbone communication network can be used to interconnect various nodes of the network. In at least one embodiment, the WWW is a set of protocols operating on top of the Internet, and allows a graphical interface system to operate thereon to access information via the Internet. In at least one embodiment, attached to Internet 1032 in the WWW are a plurality of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, the nodes dock with other nodes of the WWW via WWW HTTP servers (such as servers 1034, 1036). In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although for illustrative purposes Figure 10C PC 1044 and server 1036 are shown separately in

[0170] In at least one embodiment, the WWW is a distributed type of application, characterized by the WWW HTTP, the protocol of the WWW, which runs on top of the Transmission Control Protocol / Internet Protocol (“TCP / IP”) of the Internet. In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) running on the Internet as its “backbone”.

[0171] In at least one embodiment, a web browser is an application that runs on a node of a network in a network system compatible with the WWW type, which allows users of a particular server or node to view such information and thus allows users to search for graphical and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understands HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document may have different hypertext links embedded therein and a local copy of the page created locally by the user is retrieved. In at least one embodiment, when a user clicks on a hypertext link, the locally stored information associated with the selected hypertext link is generally sufficient to allow the user's machine to open a connection over the Internet to the server indicated by the hypertext link.

[0172] In at least one embodiment, more than one user may be coupled to each HTTP server via a LAN (such as LAN 1038, as shown with respect to WWW HTTP server 1034). In at least one embodiment, system 1000C may also include other types of nodes or elements. In at least one embodiment, the WWW HTTP server is an application that runs on a machine such as a PC. In at least one embodiment, each user may be considered to have a unique "server", as shown with respect to PC 1044. In at least one embodiment, a server may be considered to be a server such as WWW HTTP server 1034 that provides access to the network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each having a desktop PC or a node of the network, and each desktop PC potentially establishing a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that, when accessed, provides the default web page for that user. In at least one embodiment, a web page may contain further links (embedded URLs) that point to further sub-pages of that user on that server, or to other servers on the network or to pages on other servers on the network.

[0173] Cloud computing and services

[0174] The following figures illustrate, but are not limited to, exemplary cloud-based systems that may be used to implement at least one embodiment.

[0175] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge of, expertise in, or control over the technical infrastructure that supports them, which can be referred to as "in the cloud". In at least one embodiment, cloud computing incorporates infrastructure as a service, platform as a service, software as a service, and other variants with a common theme of relying on the Internet to meet the computing needs of users. In at least one embodiment, a typical cloud deployment (such as in a private cloud (e.g., an enterprise network) or a public cloud (e.g., the Internet)) data center (DC) can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel, or Ethernet Fibre Channel (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, the cloud can also consist of network service infrastructure, such as an IPsec VPN hub, firewall, load balancer, wide area network (WAN) optimizer, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services through a connection via a VPN tunnel (such as an IPsec VPN tunnel).

[0176] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage devices, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0177] In at least one embodiment, cloud computing is characterized by on-demand self-service, where consumers can automatically and unilaterally provision computing capabilities, such as server time and network storage, as needed without human interaction with each service provider. In at least one embodiment, cloud computing is characterized by broad network access, where the capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, where the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge of the exact location of the resources provided, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0178] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, where capabilities can be rapidly and elastically provisioned (automatically in some cases) to quickly scale down and quickly release to quickly scale up. In at least one embodiment, to the consumer, the capabilities available for provisioning generally appear unlimited and can be purchased in any quantity at any time. In at least one embodiment, cloud computing is characterized by measured service, where the cloud system automatically controls and optimizes resource use by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource use can be monitored, controlled, and reported, providing transparency for both the provider and consumer of the utilized services.

[0179] In at least one embodiment, cloud computing can be associated with various services. In at least one embodiment, cloud software as a service (SaaS) can refer to a service where the capabilities provided to the consumer are to use the provider's applications running on the cloud infrastructure. In at least one embodiment, the applications can be accessed from different client devices through a thin client interface such as a web browser (e.g., web-based email). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including the network, servers, operating systems, storage, or even the individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0180] In at least one embodiment, cloud platform as a service (PaaS) can refer to a service where the capabilities provided to the consumer are to deploy the application programs created or acquired by the consumer onto the cloud infrastructure, and these application programs are created using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including the network, servers, operating systems, or storage, but has control over the deployed application programs and possibly the application hosting environment configuration.

[0181] In at least one embodiment, cloud infrastructure as a service (IaaS) can refer to a service where the capabilities provided to the consumer are to provide processing, storage, network, and other basic computing resources that the consumer can deploy and run any software that may include operating systems and applications. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed application programs, and possibly limited control over selected networking components (e.g., host firewall).

[0182] In at least one embodiment, cloud computing can be deployed in different ways. In at least one embodiment, a private cloud may refer to a cloud infrastructure that is operated only for an organization. In at least one embodiment, a private cloud may be managed by an organization or a third party and may exist on-premises or off-premises. In at least one embodiment, a community cloud may refer to a cloud infrastructure that is shared by several organizations and supports a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). In at least one embodiment, a community cloud may be managed by an organization or a third party and may exist on-premises or off-premises. In at least one embodiment, a public cloud may refer to a cloud infrastructure that is available to the general public or large industrial groups and is owned by an organization that provides cloud services. In at least one embodiment, a hybrid cloud may refer to a cloud infrastructure that is a composition of two or more clouds (private, community, or public), which remain as distinct entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds). In at least one embodiment, a cloud computing environment is service-oriented, with an emphasis on statelessness, low coupling, modularity, and semantic interoperability.

[0183] Figure 11 Illustrates one or more components of a system environment 1100 according to at least one embodiment, where services may be provided as third-party network services. In at least one embodiment, a third-party network may be referred to as a cloud, cloud network, cloud computing network, and / or variants thereof. In at least one embodiment, the system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which may be used by a user to interact with a third-party network infrastructure system 1102 that provides third-party network services (which may be referred to as cloud computing services). In at least one embodiment, the third-party network infrastructure system 1102 may include one or more computers and / or servers.

[0184] It should be understood that Figure 11 the third-party network infrastructure system 1102 depicted in Figure 11 may have other components in addition to those depicted. Further, Figure 11 an embodiment of the third-party network infrastructure system is depicted. In at least one embodiment, the third-party network infrastructure system 1102 may have more or fewer components than Figure 11 depicted, may combine two or more components, or may have a different component configuration or arrangement.

[0185] In at least one embodiment, client computing devices 1104, 1106, and 1108 may be configured to operate client applications, such as a web browser, a proprietary client application, or some other application that can be used by a user of the client computing device to interact with the third-party network infrastructure system 1102 to use services provided by the third-party network infrastructure system 1102. Although the exemplary system environment 1100 is shown as having three client computing devices, any number of client computing devices may be supported. In at least one embodiment, other devices, such as devices having sensors, etc., may interact with the third-party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 may facilitate communication and data exchange between the client computing devices 1104, 1106, and 1108 and the third-party network infrastructure system 1102.

[0186] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include hosting of services that are available on demand to users of the third-party network infrastructure system. In at least one embodiment, various services may also be provided, including but not limited to online data storage and backup solutions, web-based email services, hosted office suites and document collaboration services, database management and processing, managed technical support services, and / or variants thereof. In at least one embodiment, the services provided by the third-party network infrastructure system may be dynamically scaled to meet the needs of its users.

[0187] In at least one embodiment, a particular instantiation of a service provided by the third-party network infrastructure system 1102 may be referred to as a "service instance". In at least one embodiment, generally, any service that is available to a user from a third-party network service provider system via a communication network (such as the Internet) is referred to as a "third-party network service". In at least one embodiment, in a common third-party network environment, the servers and systems that make up the third-party network service provider system are different from the customer's own on-premises servers and systems. In at least one embodiment, the third-party network service provider system may host applications, and users may order and use the applications on demand via a communication network (such as the Internet).

[0188] In at least one embodiment, services in a third-party network infrastructure of a computer network can include protected computer network access to storage, hosting databases, hosting web servers, software applications, or other services provided by a third-party network provider to users. In at least one embodiment, the services can include password-protected access over the Internet to remote storage devices on a third-party network. In at least one embodiment, the services can include a hosted relational database and a scripting language middleware engine based on a web service for private use by networked developers. In at least one embodiment, the services can include access to an email software application hosted on a website of a third-party network provider.

[0189] In at least one embodiment, the third-party network infrastructure system 1102 can include a set of application, middleware, and database service offerings delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, the third-party network infrastructure system 1102 can also provide "big data"-related computing and analysis services. In at least one embodiment, the term "big data" is generally used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by the infrastructure system at many levels and in different scales. In at least one embodiment, dozens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate external forces on the data or what it represents. In at least one embodiment, these data sets can involve structured data (such as structured data stored in a database or otherwise organized according to a structured model) and / or unstructured data (e.g., email, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging the capabilities of the embodiments to relatively quickly focus more (or less) computing resources on a target, the third-party network infrastructure system can be better available to perform tasks on large data sets based on the needs from enterprises, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0190] In at least one embodiment, the third-party network infrastructure system 1102 can be adapted to automatically provide, manage, and track a customer's subscription to services provided by the third-party network infrastructure system 1102. In at least one embodiment, the third-party network infrastructure system 1102 can provide third-party network services via different deployment models. In at least one embodiment, services can be provided under a public third-party network model, where the third-party network infrastructure system 1102 is owned by an organization that sells third-party network services and makes the services available to the general public or different industry enterprises. In at least one embodiment, services can be provided under a private third-party network model, in which the third-party network infrastructure system 1102 operates only for a single organization and can provide services for one or more entities within the organization. In at least one embodiment, third-party network services can also be provided under a community third-party network model, where the third-party network infrastructure system 1102 and the services provided by the third-party network infrastructure system 1102 are shared by several organizations in the relevant community. In at least one embodiment, third-party network services can also be provided under a hybrid third-party network model, which is a combination of two or more different models.

[0191] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 can include one or more services provided under the software as a service (SaaS) category, platform as a service (PaaS) category, infrastructure as a service (IaaS) category, or other service categories including hybrid services. In at least one embodiment, a customer can order one or more services provided by the third-party network infrastructure system 1102 via a subscription order. In at least one embodiment, the third-party network infrastructure system 1102 then performs processing to provide the services in the customer's subscription order.

[0192] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include, but are not limited to, application services, platform services, and infrastructure services. In at least one embodiment, the application services may be provided by the third-party network infrastructure system via a SaaS platform. In at least one embodiment, the SaaS platform may be configured to provide third-party network services belonging to the SaaS category. In at least one embodiment, the SaaS platform may provide the ability to build and deliver a set of on-demand applications on an integrated development and deployment platform. In at least one embodiment, the SaaS platform may manage and control the underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by leveraging the services provided by the SaaS platform, customers may utilize applications executed on the third-party network infrastructure system. In at least one embodiment, customers may obtain application services without the need for customers to purchase separate licenses and support. In at least one embodiment, various different SaaS services may be provided. In at least one embodiment, this may include, but is not limited to, services that provide solutions for sales performance management, enterprise integration, and business agility for large organizations.

[0193] In at least one embodiment, the platform services may be provided by the third-party network infrastructure system 1102 via a PaaS platform. In at least one embodiment, the PaaS platform may be configured to provide third-party network services belonging to the PaaS category. In at least one embodiment, the platform services may include, but are not limited to, services that enable an organization to consolidate existing applications on a shared common architecture, and the ability to build new applications that utilize the shared services provided by the platform. In at least one embodiment, the PaaS platform may manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers may obtain the PaaS services provided by the third-party network infrastructure system 1102 without the need for customers to purchase separate licenses and support.

[0194] In at least one embodiment, by leveraging the services provided by the PaaS platform, customers may adopt programming languages and tools supported by the third-party network infrastructure system and also control the deployed services. In at least one embodiment, the platform services provided by the third-party network infrastructure system may include database third-party network services, middleware third-party network services, and third-party network services. In at least one embodiment, the database third-party network services may support a shared service deployment model that enables an organization to pool database resources and provide database as a service to customers in the form of a database third-party network. In at least one embodiment, in the third-party network infrastructure system, the middleware third-party network services may provide a platform for customers to develop and deploy different business applications, and the third-party network services may provide a platform for customers to deploy applications.

[0195] In at least one embodiment, various different infrastructure services may be provided by an IaaS platform in a third-party network infrastructure system. In at least one embodiment, the infrastructure services facilitate the management and control by customers who utilize services provided by SaaS platforms and PaaS platforms of underlying computing resources such as storage, networking, and other basic computing resources.

[0196] In at least one embodiment, the third-party network infrastructure system 1102 may also include infrastructure resources 1130 for providing resources for delivering various services to customers of the third-party network infrastructure system. In at least one embodiment, the infrastructure resources 1130 may include a pre-integrated and optimized combination of hardware such as servers, storage, and networking resources for performing services and other resources provided by PaaS platforms and SaaS platforms.

[0197] In at least one embodiment, the resources in the third-party network infrastructure system 1102 may be shared by multiple users and dynamically reallocated on demand. In at least one embodiment, resources may be allocated to users in different time zones. In at least one embodiment, the third-party network infrastructure system 1102 may enable a first group of users in a first time zone to utilize the resources of the third-party network infrastructure system for a specified number of hours and then enable the same resources to be reallocated to another group of users located in a different time zone, thereby maximizing resource utilization.

[0198] In at least one embodiment, a plurality of internal shared services 1132 shared by different components or modules of the third-party network infrastructure system 1102 may be provided for implementing services provided by the third-party network infrastructure system 1102. In at least one embodiment, these internal shared services may include but are not limited to security and identity services, integration services, enterprise library services, enterprise manager services, virus scanning and whitelisting services, high availability, backup and recovery services, services for enabling third-party network support, email services, notification services, file transfer services, and / or variants thereof.

[0199] In at least one embodiment, the third-party network infrastructure system 1102 may provide comprehensive management of third-party network services (e.g., SaaS, PaaS, and IaaS services) in the third-party network infrastructure system. In at least one embodiment, the third-party network management function may include the ability to provision, manage, and track subscriptions of customers received by the third-party network infrastructure system 1102 and / or variants thereof.

[0200] In at least one embodiment, as Figure 11As shown, the third-party network management function can be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provision module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules may include one or more computers and / or servers or use one or more computers and / or servers to provide, and the one or more computers and / or servers may be general-purpose computers, dedicated server computers, server farms, server clusters, or any other suitable arrangement and / or combination.

[0201] In at least one embodiment, at step 1134, a customer using a client device (such as client computing devices 1104, 1106, or 1108) can interact with the third-party network infrastructure system 1102 by requesting one or more services provided by the third-party network infrastructure system 1102 and placing an order for a subscription to one or more services provided by the third-party network infrastructure system 1102. In at least one embodiment, the customer can access a third-party network user interface (UI), such as third-party network UI 1112, third-party network UI 1114, and / or third-party network UI 1116, and place an order via these UIs. In at least one embodiment, the order information received by the third-party network infrastructure system 1102 in response to the customer placing an order may include information identifying the customer and one or more services provided by the third-party network infrastructure system 1102 that the customer wishes to subscribe to.

[0202] In at least one embodiment, at step 1136, the order information received from the customer can be stored in the order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, the order database 1118 can be one of several databases operated by the third-party network infrastructure system 1118 and operating in conjunction with other system elements.

[0203] In at least one embodiment, at step 1138, the order information can be forwarded to the order management module 1120, which can be configured to perform billing and accounting functions related to the order, such as verifying the order and, after verification, reserving an order.

[0204] In at least one embodiment, at step 1140, information about an order can be transmitted to an order coordination module 1122, which is configured to coordinate the provision of services and resources for an order placed by a customer. In at least one embodiment, the order coordination module 1122 may use the services of an order provisioning module 1124 for provisioning. In at least one embodiment, the order coordination module 1122 enables the management of business processes associated with each order and applies business logic to determine whether an order should continue to be provisioned.

[0205] In at least one embodiment, at step 1142, when a new subscription order is received, the order coordination module 1122 sends a request to the order provisioning module 1124 to allocate resources and configure the resources required to fulfill the subscription order. In at least one embodiment, the order provisioning module 1124 implements resource allocation for the services ordered by the customer. In at least one embodiment, the order provisioning module 1124 provides an abstraction level between the third-party network services provided by a third-party network infrastructure system 1100 and the physical implementation layer for provisioning the resources used to provide the requested services. In at least one embodiment, this enables the order coordination module 1122 to be isolated from implementation details, such as whether the services and resources are actually provisioned in real time or pre-provisioned and only allocated / assigned upon request.

[0206] In at least one embodiment, at step 1144, once the services and resources are provisioned, a notification indicating that the requested service is now ready for use can be sent to the subscribing customer. In at least one embodiment, information (e.g., a link) can be sent to the customer, which enables the customer to start using the requested service.

[0207] In at least one embodiment, at step 1146, the order subscribed by the customer can be managed and tracked by an order management and monitoring module 1126. In at least one embodiment, the order management and monitoring module 1126 can be configured to collect usage statistics regarding the use of the subscribed service by the customer. In at least one embodiment, statistics can be collected for the amount of storage used, the amount of data transmitted, the number of users, and the amount and / or variation of system power-on time and system power-off time.

[0208] In at least one embodiment, the third-party network infrastructure system 1100 may include an identity management module 1128 configured to provide identity services, such as access management and authorization services in the third-party network infrastructure system 1100. In at least one embodiment, the identity management module 1128 may control information about customers who wish to utilize services provided by the third-party network infrastructure system 1102. In at least one embodiment, such information may include information for authenticating the identities of such customers and information describing what actions those customers are authorized to perform relative to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, the identity management module 1128 may also include managing descriptive information about each customer and about how such descriptive information can be accessed and modified and by whom.

[0209] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, the cloud computing environment 1202 includes one or more computer systems / servers 1204, and computing devices such as personal digital assistants (PDAs) or cellular phones 1206A, desktop computers 1206B, laptop computers 1206C, and / or automotive computer systems 1206N communicate with the one or more computer systems / servers 1204. In at least one embodiment, this allows infrastructure, platform, and / or software as a service to be provided from the cloud computing environment 1202 so that each client does not need to separately maintain such resources. It should be understood that Figure 12 the types of computing devices 1206A-N shown are intended to be illustrative only, and the cloud computing environment 1202 may communicate with any type of computerized device via any type of network and / or network / addressable connection (e.g., using a web browser).

[0210] In at least one embodiment, the computer system / server 1204, which may be represented as a cloud computing node, may operate with many other general-purpose or special-purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations suitable for use with the computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, and / or variations thereof.

[0211] In at least one embodiment, the computer system / server 1204 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. In at least one embodiment, the exemplary computer system / server 1204 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0212] Figure 13 illustrates a set of functional abstraction layers provided by a cloud computing environment 1202 ( Figure 12 ) as per at least one embodiment. It should be understood in advance that Figure 13 the components, layers, and functions shown in

[0213] In at least one embodiment, the hardware and software layer 1302 includes hardware and software components. In at least one embodiment, the hardware components include mainframes, servers based on various RISC (Reduced Instruction Set Computer) architectures, various computing systems, supercomputing systems, storage devices, networks, networking components, and / or their variants. In at least one embodiment, the software components include web application server software, various application server software, various database software, and / or their variants.

[0214] In at least one embodiment, the virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities may be provided: virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications, virtual clients, and / or their variants.

[0215] In at least one embodiment, the management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides for the dynamic acquisition of computing resources and other resources for performing tasks within a cloud computing environment. In at least one embodiment, metering provides usage tracking when resources are utilized within a cloud computing environment, as well as billing or invoicing for the consumption of those resources. In at least one embodiment, resources can include application software licenses. In at least one embodiment, security provides authentication for users and tasks, as well as protection for data and other resources. In at least one embodiment, the user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that the required service levels are met. In at least one embodiment, service level agreement (SLA) management provides for the pre-provisioning and acquisition of cloud computing resources, anticipating future demands for the cloud computing resources according to the SLA.

[0216] In at least one embodiment, the workload layer 1308 provides functions for leveraging the cloud computing environment. In at least one embodiment, the workloads and functions that can be provided from this layer include: maps and navigation, software development and management, educational services, data analysis and processing, transaction processing, and service delivery.

[0217] Supercomputing

[0218] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0219] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits significant parallelism and includes at least one chip, where the chips in the system are interconnected by a network and are placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a computer room with a number of racks is at least one embodiment of a supercomputer, where each rack contains a number of boards / rack modules, and each board / rack module contains a number of chips that are all interconnected by a scalable network. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and contains a number of hardware components can also be considered a supercomputer, as the number of hardware components that can be incorporated in a single chip may increase as the feature size may decrease.

[0220] Figure 14Shows a chip - level supercomputer according to at least one embodiment. In at least one embodiment, inside an FPGA or ASIC chip, the main computation is executed within a finite - state machine (1404) called a thread unit. In at least one embodiment, a task and synchronization network (1402) connects the finite - state machines and is used to dispatch threads and execute operations in the correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi - level partitioned on - chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and an off - chip memory network (1414) are used to access off - chip memory. In at least one embodiment, when the design is not suitable for a single logic chip, an I / O controller (1418) is used for cross - chip communication.

[0221] Figure 15 Shows a supercomputer at the rack - module level according to at least one embodiment. In at least one embodiment, within a rack - module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that form the main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its adjacent FPGA / ASIC chips using wide buses on the board with differential high - speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high - speed serial communication cable.

[0222] Figure 16 Shows a rack - level supercomputer according to at least one embodiment. Figure 17 Shows a supercomputer at the entire - system level according to at least one embodiment. In at least one embodiment, see Figure 16 and Figure 17, between rack modules in a rack and across the racks of an entire system, a scalable, possibly incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of the accelerator is connected to the host system (1704) via a PCI-Express connection. In at least one embodiment, the host system includes a host microprocessor (1708) on which the software part of the application runs and a memory consisting of one or more host memory DRAM units (1706) that are consistent with the memory on the accelerator. In at least one embodiment, the host system can be a separate module on one of the racks or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cube-connected cyclic topology provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, the group includes chips A, B, C, and D on a rack module that has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables connecting the rack module to the outside world. In at least one embodiment, chip A on the rack module is connected to serial communication cables 0, 1, and 2. In at least one embodiment, chip B is connected to cables 3, 4, and 5. In at least one embodiment, chip C is connected to 6, 7, and 8. In at least one embodiment, chip D is connected to 9, 10, and 11. In at least one embodiment, the entire group {A, B, C, D} that makes up the rack module can form a hypercube node within a supercomputer system, where there are up to 2^12 = 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B using the on-board differential wide bus connection. In at least one embodiment, a message arriving at the group {A, B, C, D} (i.e., arriving at B) on link 4 destined for chip A must also first be routed to the correct destination chip (A) within the group {A, B, C, D}. In at least one embodiment, parallel supercomputer systems of other sizes can also be implemented.

[0223] Artificial Intelligence

[0224] The following figures illustrate, but are not limited to, exemplary artificial intelligence-based systems that can be used to implement at least one embodiment.

[0225] Figure 18AShown is inference and / or training logic 1815 for performing inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are provided below in conjunction with Figure 18A and / or Figure 18B inference and / or training logic 1815.

[0226] In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, code and / or data storage 1801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 1815 may include or be coupled to code and / or data storage 1801 for storing graph code or other software to control timing and / or sequencing, where weight and / or other parameter information will be loaded to configure the logic, including integer and / or floating point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, the code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of the neural network that is trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1801 may be included with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache memory or system memory.

[0227] In at least one embodiment, any portion of the code and / or data storage 1801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1801 may be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, the choice of whether the code and / or data storage 1801 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0228] In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to: code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of the neural network, which is combined with one or more embodiments during the input / output data and / or backpropagation of weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 1815 may include or be coupled to the code and / or data storage 1805 to store graph code or other software to control timing and / or sequence, where weights and / or other parameter information will be loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0229] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, any portion of the code and / or data storage 1805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash), or other storage devices. In at least one embodiment, the choice of whether the code and / or data storage 1805 is internal or external to the processor, or includes DRAM, SRAM, flash, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0230] In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be separate storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be combined storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 1801 and code and / or data store 1805 may be included with other on-chip or off-chip data stores, including the L1, L2, or L3 cache of the processor or system memory.

[0231] In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1810, including integer and / or floating-point units, for performing logical and / or mathematical operations at least in part based on training and / or inference code (e.g., graphics code) or as directed by training and / or inference code (e.g., graphics code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 1820, which is a function of input / output and / or weight parameter data stored in code and / or data store 1801 and / or code and / or data store 1805. In at least one embodiment, the activations stored in activation store 1820 are generated according to linear algebra and / or matrix-based mathematics executed by ALU 1810 in response to execution of instructions or other code, where the weight values stored in code and / or data store 1805 and / or data store 1801 are used as operands along with other values (such as bias values, gradient information, momentum values, or other parameters or hyperparameters), any or all of which other values may be stored in code and / or data store 1805 or code and / or data store 1801 or another storage on or off the chip.

[0232] In at least one embodiment, one or more ALUs 1810 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1810 may be external to the processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, the ALU 1810 may be included within the execution unit of the processor or otherwise within an ALU library accessible by the execution unit of the processor, where the execution unit of the processor is within the same processor or distributed among different types of different processors (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, the code and / or data store 1801, the code and / or data store 1805, and the activation store 1820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation store 1820 may be included with other on-chip or off-chip data stores, where the other on-chip or off-chip data stores include the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code may be stored together with other code accessible to and used by the processor or other hardware logic or circuits that utilize the fetch, decode, schedule, execute, retirement, and / or other logic circuits of the processor to fetch and / or process.

[0233] In at least one embodiment, the activation store 1820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, the activation store 1820 may be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 1820 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0234] In at least one embodiment, Figure 18A the inference and / or training logic 1815 shown may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor. In at least one embodiment, Figure 18A the inference and / or training logic 1815 shown in may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0235] Figure 18B FIG. shows inference and / or training logic 1815 according to at least one embodiment. In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise combined and used exclusively with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B the inference and / or training logic 1815 shown in may be used in conjunction with an application specific integrated circuit (ASIC) such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 18B the inference and / or training logic 1815 shown in may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 18B at least one embodiment illustrated in, each of code and / or data storage 1801 and code and / or data storage 1805 is respectively associated with dedicated computing resources (e.g., computing hardware 1802 and computing hardware 1806). In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform only mathematical functions (such as linear algebra functions) on the information stored in code and / or data storage 1801 and code and / or data storage 1805, the results of which are stored in activation storage 1820.

[0236] In at least one embodiment, each code and / or data store 1801 and 1805 and the corresponding computing hardware 1802 and 1806 respectively correspond to different layers of a neural network such that the result activation from one of the storage / computation pairs 1801 / 1802 in the code and / or data store 1801 and the computing hardware 1802 is provided as input to the next storage / computation pair 1805 / 1806 in the code and / or data store 1805 and the computing hardware 1806 in order to mirror the conceptual organization of the neural network. In at least one embodiment, each of the storage / computation pairs 1801 / 1802 and 1805 / 1806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) after or parallel to the storage / computation pairs 1801 / 1802 and 1805 / 1806 can be included in the inference and / or training logic 1815.

[0237] Figure 19 Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training data set 1902 is used to train an untrained neural network 1906. In at least one embodiment, the training framework 1904 is the PyTorch framework, while in other embodiments, the training framework 1904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j or other training frameworks. In at least one embodiment, the training framework 1904 trains the untrained neural network 1906 and enables it to be trained using the processing resources described herein to generate a trained neural network 1908. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised or unsupervised manner.

[0238] In at least one embodiment, a supervised learning is used to train an untrained neural network 1906, where the training dataset 1902 includes inputs paired with expected outputs for the inputs, or where the training dataset 1902 includes inputs with known outputs and the outputs of the neural network 1906 are manually graded. In at least one embodiment, the untrained neural network 1906 is trained in a supervised manner, and the inputs from the training dataset 1902 are processed and the resulting outputs are compared with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1906. In at least one embodiment, the training framework 1904 adjusts the weights that control the untrained neural network 1906. In at least one embodiment, the training framework 1904 includes tools for monitoring how well the untrained neural network 1906 converges towards a model (such as a trained neural network 1908) that is suitable for generating correct answers (such as results 1914) based on input data (such as a new dataset 1912). In at least one embodiment, the training framework 1904 repeatedly trains the untrained neural network 1906 while using a loss function and an adjustment algorithm (such as stochastic gradient descent) to adjust the weights to refine the output of the untrained neural network 1906. In at least one embodiment, the training framework 1904 trains the untrained neural network 1906 until the untrained neural network 1906 achieves the desired accuracy. In at least one embodiment, the trained neural network 1908 can then be deployed to perform any number of machine learning operations.

[0239] In at least one embodiment, an unsupervised learning is used to train an untrained neural network 1906, where the untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1906 can learn groupings within the training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate self-organizing maps in the trained neural network 1908 that are useful for performing operations in reducing the dimension of a new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identifying data points in the new dataset 1912 that deviate from the normal patterns of the new dataset 1912.

[0240] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training data set 1902. In at least one embodiment, the training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1908 to adapt to a new data set 1912 without forgetting the knowledge injected into the trained neural network 1408 during the initial training.

[0241] 5G network

[0242] The following figures illustrate, but are not limited to, exemplary 5G network-based systems that can be used to implement at least one embodiment.

[0243] Figure 20 The architecture of a system 2000 of a network according to at least one embodiment is shown. In at least one embodiment, system 2000 is shown to include user equipment (UE) 2002 and UE 2004. In at least one embodiment, UE 2002 and 2004 are shown as smart phones (e.g., handheld touchscreen mobile computing devices that can be connected to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a personal digital assistant (PDA), pager, laptop computer, desktop computer, wireless handheld device, or any computing device including a wireless communication interface.

[0244] In at least one embodiment, any one of UE 2002 and UE 2004 may include an Internet of Things (IoT) UE, which may include a network access layer designed for low-power IoT applications that utilize short-lived UE connections. In at least one embodiment, the IoT UE may utilize techniques such as machine-to-machine (M2M) or machine type communication (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), proximity-based services (ProSe), or device-to-device (D2D) communication, a sensor network, or an IoT network. In at least one embodiment, the M2M or MTC data exchange may be machine-initiated data exchange. In at least one embodiment, an IoT network describes interconnected IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure) having short-lived connections. In at least one embodiment, the IoT UE may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connection of the IoT network.

[0245] In at least one embodiment, UEs 2002 and 2004 may be configured to connect (e.g., communicatively couple) to a Radio Access Network (RAN) 2016. In at least one embodiment, the RAN 2016 may be an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN in at least one embodiment. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each connection including a physical communication interface or layer. In at least one embodiment, connections 2012 and 2014 are shown as air interfaces for achieving communication coupling and may be consistent with cellular communication protocols such as Global System for Mobile Communications (GSM) protocol, Code Division Multiple Access (CDMA) network protocol, Push-to-Talk (PTT) protocol, Push-to-Talk over Cellular (PoC) protocol, Universal Mobile Telecommunications System (UMTS) protocol, 3GPP Long-Term Evolution (LTE) protocol, Fifth Generation (5G) protocol, New Radio (NR) protocol, and variants thereof.

[0246] In at least one embodiment, UEs 2002 and 2004 may also directly exchange communication data via the ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 may alternatively be referred to as a sidelink interface, which includes one or more logical channels, including but not limited to Physical Sidelink Control Channel (PSCCH), Physical Sidelink Shared Channel (PSSCH), Physical Sidelink Discovery Channel (PSDCH), and Physical Sidelink Broadcast Channel (PSBCH).

[0247] In at least one embodiment, UE 2004 is shown as being configured to access an Access Point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where the AP 2010 will include a Wi-Fi router. In at least one embodiment, the AP 2010 is shown as being connected to the Internet without being connected to the core network of the wireless system.

[0248] In at least one embodiment, RAN 2016 may include one or more access nodes enabling connections 2012 and 2014. In at least one embodiment, these access nodes (ANs) may be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next-generation NodeBs (gNBs), RAN nodes, etc., and may include terrestrial stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographical area (e.g., a cell). In at least one embodiment, RAN 2016 may include one or more RAN nodes for providing macro cells (e.g., macro RAN node 2018) and one or more RAN nodes for providing femto cells or pico cells (e.g., cells having a smaller coverage area, a smaller user capacity, or a higher bandwidth compared to macro cells) (e.g., low-power (LP) RAN node 2020).

[0249] In at least one embodiment, either of RAN nodes 2018 and 2020 may terminate the air interface protocol and may be the first point of contact for UEs 2002 and 2004. In at least one embodiment, either of RAN nodes 2018 and 2020 may implement various logical functions of RAN 2016, including but not limited to radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling and mobility management.

[0250] In at least one embodiment, UEs 2002 and 2004 may be configured to communicate with each other or with either of RAN node 2018 and RAN node 2020 over a multi-carrier communication channel using orthogonal frequency division multiplexing (OFDM) communication signals according to various communication technologies, such as but not limited to orthogonal frequency division multiple access (OFDMA) communication technologies (e.g., for downlink communication) or single-carrier frequency division multiple access (SC-FDMA) communication technologies (e.g., for uplink and ProSe or sidelink communication), and / or variants thereof. In at least one embodiment, the OFDM signal may include a plurality of orthogonal subcarriers.

[0251] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from either RAN node 2018 and 2020 to UEs 2002 and 2004, and uplink transmissions can utilize similar techniques. In at least one embodiment, the grid can be a time-frequency grid, referred to as a resource grid or a time-frequency resource grid, which is the physical resources in the downlink in each time slot. In at least one embodiment, such a time-frequency plane representation is a common practice in OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one time slot in a radio frame. In at least one embodiment, the smallest time-frequency unit in the resource grid is represented as a resource element. In at least one embodiment, each resource grid includes a plurality of resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a set of resource elements. In at least one embodiment, in the frequency domain, this can represent the smallest number of resources that can currently be allocated. In at least one embodiment, there are several different physical downlink channels transmitted using such resource blocks.

[0252] In at least one embodiment, the Physical Downlink Shared Channel (PDSCH) can carry user data and higher layer signaling to UEs 2002 and 2004. In at least one embodiment, the Physical Downlink Control Channel (PDCCH) can carry information such as about the transmission format and resource allocation related to the PDSCH channel. In at least one embodiment, it can also notify UEs 2002 and 2004 of the transmission format, resource allocation, and HARQ (Hybrid Automatic Repeat reQuest) information related to the uplink shared channel. In at least one embodiment, generally, downlink scheduling (allocating control and shared channel resource blocks to UE 2002 within a cell) can be performed at either RAN node 2018 and 2020 based on channel quality information fed back from either UE 2002 and 2004. In at least one embodiment, downlink resource allocation information can be sent on the PDCCH for each of UEs 2002 and 2004 (e.g., allocated to).

[0253] In at least one embodiment, the PDCCH may use control channel elements (CCEs) to transmit control information. In at least one embodiment, before being mapped to resource elements, PDCCH complex-valued symbols may first be organized into quadruples and then permuted using a sub-block interleaver for rate matching. In at least one embodiment, one or more of these CCEs may be used to transmit each PDCCH, where each CCE may correspond to nine sets of four physical resource elements referred to as resource element groups (REGs). In at least one embodiment, four quadrature phase shift keying (QPSK) symbols may be mapped to each REG. In at least one embodiment, depending on the size of the downlink control information (DCI) and the channel conditions, one or more CCEs may be used to transmit the PDCCH. In at least one embodiment, there may be four or more different PDCCH formats (e.g., aggregation levels, L = 1, 2, 4, or 8) defined in LTE with different numbers of CCEs.

[0254] In at least one embodiment, the enhanced physical downlink control channel (EPDCCH) using PDSCH resources may be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) may be used to transmit the EPDCCH. In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements referred to as enhanced resource element groups (EREGs). In at least one embodiment, the ECCE may have other numbers of EREGs in some cases.

[0255] In at least one embodiment, RAN 2016 is shown communicatively coupled to a core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, the CN 2038 may be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 2022 is divided into two parts: an S1-U interface 2026, which carries traffic data between RAN nodes 2018 and 2020 and a serving gateway (S-GW) 2030; and an S1-mobility management entity (MME) interface 2024, which is a signaling interface between RAN nodes 2018 and 2020 and the MME 2028.

[0256] In at least one embodiment, CN 2038 includes a Mobility Management Entity (MME) 2028, a Serving Gateway (S-GW) 2030, a Packet Data Network (PDN) Gateway (P-GW) 2034, and a Home Subscriber Server (HSS) 2032. In at least one embodiment, the MME 2028 can be functionally similar to the control plane of a traditional Serving General Packet Radio Service (GPRS) Support Node (SGSN). In at least one embodiment, the MME 2028 can manage aspects of mobility in access, such as gateway selection and Tracking Area List management. In at least one embodiment, the HSS 2032 can include a database for network users, which includes subscription-related information for supporting network entity processing of communication sessions. In at least one embodiment, CN 2038 can include one or more HSSs 2032, depending on the number of mobile users, the capacity of the devices, the organization of the network, etc. In at least one embodiment, the HSS 2032 can provide support for routing / roaming, authentication, authorization, name / address resolution, location dependency, etc.

[0257] In at least one embodiment, the S-GW 2030 can terminate the S1 interface 2022 towards the Radio Access Network (RAN) 2016 and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 can be a local mobility anchor for inter-RAN node handover and can also provide an anchor for inter-3GPP mobility. In at least one embodiment, other responsibilities can include lawful interception, charging, and some policy enforcement.

[0258] In at least one embodiment, the P-GW 2034 can terminate the SGi interface towards the PDN. In at least one embodiment, the P-GW 2034 can route data packets between the EPC network 2038 and an external network (such as a network including an Application Server 2040 (or referred to as Application Function (AF))) via an Internet Protocol (IP) interface 2042. In at least one embodiment, the Application Server 2040 can be an element that provides an application using IP bearer resources with a core network (e.g., UMTS Packet Service (PS) domain, LTE PS data service, etc.). In at least one embodiment, the P-GW 2034 is shown communicatively coupled to the Application Server 2040 via the IP communication interface 2042. In at least one embodiment, the Application Server 2040 can also be configured to support one or more communication services (such as Internet Protocol Voice (VoIP) sessions, Push-to-Talk (PTT) sessions, group communication sessions, social network services, etc.) for the UEs 2002 and 2004 via the CN 2038.

[0259] In at least one embodiment, the P-GW 2034 may also be a node for policy enforcement and charging data collection. In at least one embodiment, the Policy and Charging Rules Function (PCRF) 2036 is the policy and charging control element of the CN 2038. In at least one embodiment, in a non-roaming scenario, there may be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with the Internet Protocol Connectivity Access Network (IP-CAN) session of the UE. In at least one embodiment, in a roaming scenario with local traffic breakout, there may be two PCRFs associated with the IP-CAN session of the UE: a Home PCRF (H-PCRF) within the HPLMN and a Visited PCRF (V-PCRF) within the Visited Public Land Mobile Network (VPLMN). In at least one embodiment, the PCRF 2036 may be communicatively coupled to the application server 2040 via the P-GW 2034. In at least one embodiment, the application server 2040 may signal the PCRF 2036 to indicate a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, the PCRF 2036 may supply this rule to the Policy and Charging Enforcement Function (PCEF) (not shown) of a QoS class (QCI) with an appropriate Traffic Flow Template (TFT) and identifier, and the PCEF starts the QoS and charging specified by the application server 2040.

[0260] Figure 21 The architecture of a system 2100 of a network according to some embodiments is shown. In at least one embodiment, the system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a User Plane Function (shown as UPF 2104), a Data Network (DN 2106), which in at least one embodiment may be a carrier service, Internet access, or a third-party service, and a 5G Core Network (5GC) (shown as CN 2110).

[0261] In at least one embodiment, the CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, the CN 2110 may also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0262] In at least one embodiment, the UPF 2104 can act as an anchor for mobility within and between RATs, an external PDU session point interconnected to the DN 2106, and a branching point for supporting multi-homed PDU sessions. In at least one embodiment, the UPF 2104 can also perform packet routing and forwarding, packet inspection, enforce the user plane part of the policy rules, lawful intercept packets (UP collection); traffic usage reporting, perform QoS handling for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), perform uplink traffic verification (e.g., SDF to QoS flow mapping), transport-level packet marking in the uplink and downlink, and downlink packet buffering and downlink data notification triggering. In at least one embodiment, the UPF 2104 can include an uplink classifier for supporting routing traffic flows to data networks. In at least one embodiment, the DN 2106 can represent various network operator services, Internet access, or third-party services.

[0263] In at least one embodiment, the AUSF 2114 can store the data for the authentication of the UE 2102 and process the functions related to authentication. In at least one embodiment, the AUSF 2114 can facilitate a common authentication framework for various access types.

[0264] In at least one embodiment, the AMF 2112 can be responsible for registration management (e.g., for registering the UE 2102, etc.), connection management, reachability management, mobility management, and lawful intercept of AMF-related events, as well as access authentication and authorization. In at least one embodiment, the AMF 2112 can provide the transmission of SM messages for the SMF 2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF 2112 can also provide the transmission of short message service (SMS) messages between the UE 2102 and the SMS function (SMSF) ( Figure 21 (not shown). In at least one embodiment, the AMF 2112 can act as a security anchoring function (SEA), which can include interaction with the AUSF 2114 and the UE 2102 and receiving the intermediate key established as a result of the UE 2102 authentication process. In at least one embodiment, in the case of using USIM-based authentication, the AMF 2112 can retrieve the security material from the AUSF 2114. In at least one embodiment, the AMF 2112 can also include a security context management (SCM) function, which receives the key from the SEA and uses it to derive the access network-specific key. Additionally, in at least one embodiment, the AMF 2112 can be a termination point of the RAN CP interface (N2 reference point), a termination point of the NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0265] In at least one embodiment, the AMF 2112 may also support NAS signaling with the UE 2102 via the N3 Interworking Function (IWF) interface. In at least one embodiment, the N3IWF may be used to provide access to untrusted entities. In at least one embodiment, the N3IWF may be the termination point of the N2 and N3 interfaces for the control plane and the user plane respectively. Thus, it can handle N2 signaling from the SMF and the AMF for PDU sessions and QoS, encapsulate / de-encapsulate packets for IPSec and N3 tunnels, mark N3 user plane packets in the uplink, and enforce QoS corresponding to the N3 packet marking considering the QoS requirements associated with such marking received via N2. In at least one embodiment, the N3IWF may also relay uplink and downlink control plane NAS (NI) signaling between the UE 2102 and the AMF 2112, and relay uplink and downlink user plane packets between the UE 2102 and the UPF 2104. In at least one embodiment, the N3IWF also provides a mechanism for establishing an IPsec tunnel with the UE 2102.

[0266] In at least one embodiment, the SMF 2118 may be responsible for session management (e.g., session establishment, modification, and release, including tunnel maintenance between the UPF and the AN node); UE IP address allocation and management (including optional authorization); selection and control of the UPF function; configuration of traffic steering at the UPF to route traffic to the appropriate destination; termination of the interface towards the policy control function; the control part of policy enforcement and QoS; lawful interception (for SM events and the interface to the LI system); termination of the SM part of NAS messages; downlink data notification; the initiator of AN-specific SM information, which is sent to the AN via the AMF on N2; determination of the SSC mode of the session. In at least one embodiment, the SMF 2118 may include the following roaming functions: handling local implementation to apply QoS SLAB (VPLMN); charging data collection and charging interface (VPLMN); lawful interception (for SM events in the VPLMN and interface to the LI system); supporting interaction with external DNs to transmit signaling for PDU session authorization / authentication by the external DNs.

[0267] In at least one embodiment, the NEF 2116 can provide means for securely exposing services and capabilities provided by 3GPP network functions to third parties, internal exposure / re-exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle the AF. In at least one embodiment, the NEF 2116 can also transform the information exchanged with the AF 2126 and the information exchanged with internal network functions. In at least one embodiment, the NEF 2116 can transform between an AF service identifier and internal 5GC information. In at least one embodiment, the NEF 2116 can also receive information from other network functions (NFs) based on the exposed capabilities of other network functions. In at least one embodiment, this information can be stored at the NEF 2116 as structured data, or stored at a data storage NF using a standardized interface. In at least one embodiment, the stored information can then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes, such as analysis.

[0268] In at least one embodiment, the NRF 2120 can support a service discovery function, receive NF discovery requests from NF instances, and provide information about the discovered NF instances to NF instances. In at least one embodiment, the NRF 2120 also maintains information about available NF instances and the services they support.

[0269] In at least one embodiment, the PCF 2122 can provide policy rules to control plane functions to enforce them, and can also support a unified policy framework to manage network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) for accessing subscription information related to policy decisions in the UDR of the UDM 2124.

[0270] In at least one embodiment, the UDM 2124 can process subscription-related information to support network entities in handling communication sessions, and can store subscription data of the UE 2102. In at least one embodiment, the UDM 2124 can include two parts, an application FE and a user data repository (UDR). In at least one embodiment, the UDM can include a UDM FE that is responsible for handling credentials, location management, subscription management, etc. In at least one embodiment, several different front ends can serve the same user in different transactions. In at least one embodiment, the UDM-FE accesses the sub-subscription information stored in the UDR and performs authentication credential processing; user identity processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, the UDM 2124 can also support SMS management, where the SMS-FE implements similar application logic as described above.

[0271] In at least one embodiment, AF 2126 can provide application impact on service routing, access to network capability exposure (NCE), and interaction with the policy framework for policy control. In at least one embodiment, NCE can be a mechanism that allows the 5GC and AF 2126 to provide information to each other via the NEF 2116, and the NEF 2116 can be used for edge computing implementation. In at least one embodiment, network operators and third-party services can be hosted near the attachment access point of the UE 2102 to achieve efficient service delivery by reducing end-to-end latency and the load on the transport network. In at least one embodiment, for edge computing implementation, the 5GC can select a UPF 2104 close to the UE 2102 and perform service steering from the UPF 2104 to the DN 2106 via the N6 interface. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by the AF 2126. In at least one embodiment, the AF 2126 can influence UPF (re)selection and service routing. In at least one embodiment, based on operator deployment, when the AF 2126 is considered a trusted entity, the network operator can allow the AF 2126 to directly interact with relevant NFs.

[0272] In at least one embodiment, the CN 2110 can include an SMSF, which can be responsible for SMS subscription checking and verification, and relay SM messages to / from the UE 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS routers. In at least one embodiment, the SMS can also interact with the AMF 2112 and the UDM 2124 for a notification process that the UE 2102 can use for SMS transmission (e.g., set the UE unreachable flag and notify the UDM 2124 when the UE 2102 is available for SMS).

[0273] In at least one embodiment, the system 2100 can include the following service-based interfaces: Namf: The service-based interface presented by the AMF; Nsmf: The service-based interface presented by the SMF; Nnef: The service-based interface presented by the NEF; Npcf: The service-based interface presented by the PCF; Nudm: The service-based interface presented by the UDM; Naf: The service-based interface presented by the AF; Nnrf: The service-based interface presented by the NRF; and Nausf: The service-based interface presented by the AUSF.

[0274] In at least one embodiment, system 2100 may include the following reference points: N1: the reference point between the UE and the AMF; N2: the reference point between the (R)AN and the AMF; N3: the reference point between the (R)AN and the UPF; N4: the reference point between the SMF and the UPF; and N6: the reference point between the UPF and the data network. In at least one embodiment, there may be more reference points and / or service-based interfaces between the NF services in the NF. However, for clarity, these interfaces and reference points have been omitted. In at least one embodiment, the NS reference point may be between the PCF and the AF; the N7 reference point may be between the PCF and the SMF; the N11 reference point is between the AMF and the SMF, and so on. In at least one embodiment, the CN 2110 may include the Nx interface, which is the inter-CN interface between the MME and the AMF 2112 to enable interoperability between the CN 2110 and the CN7221.

[0275] In at least one embodiment, system 2100 may include multiple RAN nodes (such as the (R)AN node 2108), where an Xn interface is defined between two or more (R)AN nodes 2108 (e.g., gNB) connected to the 5GC 410, between the (R)AN node 2108 (e.g., gNB) connected to the CN 2110 and the eNB (e.g., macro RAN node), and / or between two eNBs connected to the CN 2110.

[0276] In at least one embodiment, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, the Xn-U may provide an unguaranteed delivery of user plane PDUs and support / provide data forwarding and flow control functions. In at least one embodiment, the Xn-C may provide management and error handling functions, functions for managing the Xn-C interface; mobility support for the UE 2102 in the connected mode (e.g., CM-CONNECTED), which includes functions for managing the mobility of the UE in the connected mode between one or more (R)AN nodes 2108. In at least one embodiment, the mobility support may include context transfer from the old (source) serving (R)AN node 2108 to the new (target) serving (R)AN node 2108; and control of the user plane tunnel between the old (source) serving (R)AN node 2108 and the new (target) serving (R)AN node 2108.

[0277] In at least one embodiment, the Xn-U protocol stack may include a transport network layer built on the Internet Protocol (IP) transport layer and a GTP-U layer on top of UDP and / or one or more IP layers for carrying user plane PDUs. In at least one embodiment, the Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on the SCTP layer. In at least one embodiment, the SCTP layer may be on top of the IP layer. In at least one embodiment, the SCTP layer provides guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack may be the same as or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0278] Figure 22 is an illustration of a control plane protocol stack according to some embodiments. In at least one embodiment, the control plane 2200 is shown as a communication protocol stack between the UE 2002 (or alternatively, the UE 2004), the RAN 2016, and the MME 2028.

[0279] In at least one embodiment, the PHY layer 2202 may send or receive information used by the MAC layer 2204 via one or more air interfaces. In at least one embodiment, the PHY layer 2202 may also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers (e.g., the RRC layer 2210). In at least one embodiment, the PHY layer 2202 may further perform error detection on the transport channel, forward error correction (FEC) coding / decoding of the transport channel, modulation / demodulation of the physical channel, interleaving, rate matching, mapping to the physical channel, and multi-input multi-output (MIMO) antenna processing.

[0280] In at least one embodiment, the MAC layer 2204 may perform mapping between logical channels and transport channels, multiplex MAC service data units (SDUs) from one or more logical channels onto transport blocks (TBs) to be delivered to the PHY via the transport channel, demultiplex MAC SDUs from transport blocks (TBs) delivered from the PHY via the transport channel onto one or more logical channels, multiplex MAC SDUs onto TBs, scheduling information reporting, error correction via hybrid automatic repeat request (HARD), and logical channel prioritization.

[0281] In at least one embodiment, the RLC layer 2206 can operate in multiple operation modes, including: Transparent Mode (TM), Unacknowledged Mode (UM), and Acknowledged Mode (AM). In at least one embodiment, the RLC layer 2206 can perform the transmission of upper layer protocol data units (PDUs), error correction through Automatic Repeat reQuest (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly of RLC service data units (SDUs) for UM and AM data transmission. In at least one embodiment, the RLC layer 2206 can also perform resegmentation of RLC data PDUs for AM data transmission, reordering of RLC data PDUs for UM and AM data transmission, detection of duplicate data for UM and AM data transmission, discarding of RLC SDUs for UM and AM data transmission, detection of protocol errors for AM data transmission, and perform RLC reestablishment.

[0282] In at least one embodiment, the PDCP layer 2208 can perform header compression and decompression of IP data, maintain a PDCP sequence number (SN), perform in-sequence delivery of higher layer PDUs when reconstructing lower layers, eliminate duplication of lower layer SDUs when reconstructing lower layers for radio bearers mapped on RLC AM, encrypt and decrypt control plane data, perform integrity protection and integrity verification on control plane data, discard data based on a control timer, and perform security operations (e.g., encryption, decryption, integrity protection, integrity verification, etc.).

[0283] In at least one embodiment, the main services and functions of the RRC layer 2210 can include broadcasting of system information (e.g., included in the Master Information Block (MIB) or System Information Block (SIB) related to the Non-Access Stratum (NAS)), broadcasting of system information related to the Access Stratum (AS), paging, establishment, maintenance, and release of the RRC connection between the UE and the E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance, and release of point-to-point radio bearers, security functions including key management, inter-Radio Access Technology (RAT) mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, the MIB and SIB can include one or more Information Elements (IEs), and each information element can include individual data fields or data structures.

[0284] In at least one embodiment, the UE 2002 and the RAN 2016 can utilize the Uu interface (e.g., the LTE-Uu interface) to exchange control plane data via a protocol stack including the PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208, and RRC layer 2210.

[0285] In at least one embodiment, the Non-Access Stratum (NAS) protocol (NAS protocol 2212) forms the top layer of the control plane between the UE 2002 and the MME 2028. In at least one embodiment, the NAS protocol 2212 supports the mobility and session management procedures of the UE 2002 to establish and maintain an IP connection between the UE 2002 and the P-GW 2034.

[0286] In at least one embodiment, the Signaling Radio Access Network Application Part (Si-AP) layer (Si-AP layer 2222) may support the functions of the Si interface and include Elementary Procedures (EPs). In at least one embodiment, the EPs are the interaction units between the RAN 2016 and the CN 2028. In at least one embodiment, the S1-AP layer services may include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transport, Radio Access Network Information Management (RIM), and configuration transfer.

[0287] In at least one embodiment, the Stream Control Transmission Protocol (SCTP) layer (alternatively referred to as the Stream Control Transmission Protocol / Internet Protocol (SCTP / IP) layer) (SCTP layer 2220) may ensure the reliable delivery of signaling messages between the RAN 2016 and the MME 2028, partially based on the IP protocol supported by the IP layer 2218. In at least one embodiment, the L2 layer 2216 and the L1 layer 2214 may refer to the communication links (e.g., wired or wireless) used by the RAN nodes and the MME to exchange information.

[0288] In at least one embodiment, the RAN 2016 and one or more MMEs 2028 may utilize the S1-MME interface to exchange control plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the IP layer 2218, the SCTP layer 2220, and the Si-AP layer 2222.

[0289] Figure 23 is a diagram of a user plane protocol stack according to at least one embodiment. In at least one embodiment, the user plane 2300 is shown as a communication protocol stack between the UE 2002, the RAN 2016, the S-GW 2030, and the P-GW 2034. In at least one embodiment, the user plane 2300 may utilize the same protocol layers as the control plane 2200. In at least one embodiment, the UE 2002 and the RAN 2016 may utilize the Uu interface (e.g., the LTE-Uu interface) to exchange user plane data via a protocol stack including the PHY layer 2202, the MAC layer 2204, the RLC layer 2206, and the PDCP layer 2208.

[0290] In at least one embodiment, the General Packet Radio Service (GPRS) Tunneling Protocol (GTP-U) layer (GTP-U layer 2304) for the user plane can be used to carry user data within the GPRS core network and between the radio access network and the core network. In at least one embodiment, the user data transmitted can be packets in any format of IPv4, IPv6, or PPP format. In at least one embodiment, the User Datagram Protocol and Internet Protocol Security (UDP / IP) layer (UDP / IP layer 2302) can provide a checksum for data integrity, port numbers for different functions in source and destination addressing, and encryption and authentication for selected data streams. In at least one embodiment, the RAN 2016 and the S-GW 2030 can utilize the S1-U interface to exchange user plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the UDP / IP layer 2302, and the GTP-U layer 2304. In at least one embodiment, the S-GW 2030 and the P-GW 2034 can utilize the S5 / S8a interface to exchange user plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the UDP / IP layer 2302, and the GTP-U layer 2304. In at least one embodiment, as described above with respect to Figure 22 As discussed above, the NAS protocol supports the mobility and session management procedures of the UE 2002 to establish and maintain an IP connection between the UE 2002 and the P-GW 2034.

[0291] Figure 24 Components 2400 of a core network are shown in accordance with at least one embodiment. In at least one embodiment, the components of the CN 2038 can be implemented in one physical node or separate physical nodes, the separate physical nodes including components for reading and executing instructions from a machine-readable medium or a computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, Network Function Virtualization (NFV) is used to virtualize any or all of the above network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, the logical instantiation of the CN 2038 can be referred to as a network slice 2402 (e.g., the network slice 2402 is shown as including the HSS 2032, the MME 2028, and the S-GW 2030). In at least one embodiment, the logical instantiation of a part of the CN 2038 can be referred to as a network sub-slice 2404 (e.g., the network sub-slice 2404 is shown as including the P-GW 2034 and the PCRF 2036).

[0292] In at least one embodiment, an NFV architecture and infrastructure can be used to virtualize one or more network functions onto physical resources including a combination of industry standard server hardware, storage hardware, or switches, which network functions may alternatively be performed by dedicated hardware. In at least one embodiment, an NFV system can be used to perform a virtual or reconfigurable implementation of one or more EPC components / functions.

[0293] Figure 25 FIG. 2500 is a block diagram illustrating components of a system 2500 for supporting network function virtualization (NFV) according to at least one embodiment. In at least one embodiment, system 2500 is shown to include a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), a virtualized network function (shown as VNF 2508), an element manager (shown as EM 2510), an NFV coordinator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0294] In at least one embodiment, VIM 2502 manages the resources of NFVI 2504. In at least one embodiment, NFVI 2504 may include physical or virtual resources and applications (including hypervisors) for executing system 2500. In at least one embodiment, VIM 2502 may utilize NFVI 2504 to manage the lifecycle of virtual resources (e.g., creation, maintenance, and removal of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0295] In at least one embodiment, VNFM 2506 may manage VNF 2508. In at least one embodiment, VNF 2508 may be used to perform EPC components / functions. In at least one embodiment, VNFM 2506 may manage the lifecycle of VNF 2508 and track performance, faults, and security of the virtual aspects of VNF 2508. In at least one embodiment, EM 2510 may track performance, faults, and security of the functional aspects of VNF 2508. In at least one embodiment, tracking data from VNFM 2506 and EM 2510 may include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 may scale in / out the number of VNFs of system 2500.

[0296] In at least one embodiment, the NFVO 2512 may coordinate, authorize, release, and occupy resources of the NFVI 2504 to provide the requested services (e.g., to perform EPC functions, components, or slices). In at least one embodiment, the NM 2514 may provide end-user functional packages responsible for managing a network, which may include network elements with VNFs, non-virtualized network functions, or both (the management of VNFs may occur via the EM 2510).

[0297] Computer-based system

[0298] The following figures present, but are not limited to, exemplary computer-based systems that may be used to implement at least one embodiment.

[0299] Figure 26 A processing system 2600 according to at least one embodiment is shown. In at least one embodiment, the system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2602 or processor cores 2607. In at least one embodiment, the processing system 2600 is a processing platform integrated within a system-on-chip (SoC) integrated circuit for mobile, handheld, or embedded devices.

[0300] In at least one embodiment, the processing system 2600 may be included in or incorporated into a server-based gaming platform, including a game console such as a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 2600 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2600 may also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0301] In at least one embodiment, each of one or more processors 2602 includes one or more processor cores 2607 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2607 is configured to process a particular instruction set 2609. In at least one embodiment, the instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions that help to emulate other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0302] In at least one embodiment, processor 2602 includes a cache memory 2604. In at least one embodiment, processor 2602 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share the logic among processor cores 2607 using known cache coherence techniques. In at least one embodiment, a register file 2606 is further included in processor 2602, and processor 2602 can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include general-purpose registers or other registers.

[0303] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transfer communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 can be a processor bus, such as a version of the Direct Media Interface (DMI) bus, in one embodiment. In at least one embodiment, the interface bus 2610 is not limited to the DMI bus and can include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a Platform Controller Hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between the storage device and other components of the processing system 2600, while the Platform Controller Hub (PCH) 2630 provides connections to input / output (I / O) devices via a local I / O bus.

[0304] In at least one embodiment, the memory device 2620 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a Phase Change Memory device, or have suitable performance to be used as processor memory. In at least one embodiment, the storage device 2620 can be used as the system memory of the processing system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute an application or process. In at least one embodiment, the memory controller 2616 is also coupled to an optional external graphics processor 2612, which can communicate with one or more graphics processors 2608 in the processor 2602 to perform graphics and media operations. In at least one embodiment, a display device 2611 can be connected to the processor 2602. In at least one embodiment, the display device 2611 can include one or more of an internal display device, such as in a mobile electronic device or a portable computer device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2611 can include a Head-Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

[0305] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to be connected to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2624 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware, and in at least one embodiment, it can be a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2634 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2610. In at least one embodiment, the audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 2600. In at least one embodiment, the platform controller hub 2630 can also be connected to one or more Universal Serial Bus (USB) controllers 2642, which connect input devices, such as a keyboard and mouse 2643 combination, a camera 2644, or other USB input devices.

[0306] In at least one embodiment, instances of the memory controller 2616 and the platform controller hub 2630 can be integrated into a discrete external graphics processor, such as the external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and / or the storage controller 2616 can be external to one or more processors 2602. In at least one embodiment, the processing system 2600 can include an external storage controller 2616 and a platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2602.

[0307] Figure 27FIG. 2700 shows a computer system 2700 according to at least one embodiment. In at least one embodiment, the computer system 2700 may be a system having interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 2700 is formed by a processor 2702, which may include execution units for executing instructions. In at least one embodiment, the computer system 2700 may include, but is not limited to, components such as the processor 2702, which employs execution units including logic to execute algorithms for processing data. In at least one embodiment, the computer system 2700 may include a processor, such as a processor family, XeonTM, XScaleTM, and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems may also be used, including PCs, engineering workstations, set-top boxes, etc. having other microprocessors. In at least one embodiment, the computer system 2700 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces may also be used.

[0308] In at least one embodiment, the computer system 2700 may be used in other devices, such as handheld devices and embedded applications. Some of at least one embodiment of a handheld device include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors (“DSPs”), SoCs, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may execute one or more instructions according to at least one embodiment.

[0309] In at least one embodiment, the computer system 2700 may include, but is not limited to, a processor 2702, which may include, but is not limited to, one or more execution units 2708, which may be configured to execute Compute Unified Device Architecture (“CUDA”) ( (Developed by NVIDIA Corporation, Santa Clara, California) program. In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 2700 is a single-processor desktop or server system. In at least one embodiment, the computer system 2700 can be a multi-processor system. In at least one embodiment, the processor 2702 can include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor in at least one embodiment. In at least one embodiment, the processor 2702 can be coupled to a processor bus 2710, which can transfer data signals between the processor 2702 and other components in the computer system 2700.

[0310] In at least one embodiment, the processor 2702 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 2704. In at least one embodiment, the processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside outside the processor 2702. In at least one embodiment, the processor 2702 can include a combination of internal and external caches. In at least one embodiment, the register file 2706 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0311] In at least one embodiment, an execution unit 2708, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 2702. The processor 2702 can also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode for certain macro instructions. In at least one embodiment, the execution unit 2708 can include logic for processing an encapsulated instruction set 2709. In at least one embodiment, by including the encapsulated instruction set 2709 in the instruction set of the general-purpose processor 2702, and the associated circuitry for the instructions to be executed, operations used by many multimedia applications can be performed using the encapsulated data in the general-purpose processor 2702. In at least one embodiment, operations can be performed on the encapsulated data by using the full width of the processor's data bus, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time, thereby accelerating and more efficiently executing many multimedia applications.

[0312] In at least one embodiment, execution unit 2708 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 2700 may include, but is not limited to, memory 2720. In at least one embodiment, memory 2720 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage devices. Memory 2720 may store instructions 2719 and / or data 2721 represented by data signals that may be executed by processor 2702.

[0313] In at least one embodiment, the system logic chip may be coupled to processor bus 2710 and memory 2720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 2716, and processor 2702 may communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 may provide a high-bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 may initiate data signals among processor 2702, memory 2720, and other components in computer system 2700, and may bridge data signals among processor bus 2710, memory 2720, and system I / O 2722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2716 may be coupled to memory 2720 via high-bandwidth memory path 2718, and graphics / video card 2712 may be coupled to MCH 2716 via an Accelerated Graphics Port (“AGP”) interconnect 2714.

[0314] In at least one embodiment, the computer system 2700 may use the system I / O 2722 as a proprietary hub interface bus to couple the MCH 2716 to an I / O controller hub (“ICH”) 2730. In at least one embodiment, the ICH 2730 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 2720, the chipset, and the processor 2702. Examples may include, but are not limited to, an audio controller 2729, a firmware hub (“Flash BIOS”) 2728, a wireless transceiver 2726, a data storage 2724, a legacy I / O controller 2723 that includes user input 2725 and a keyboard interface, a serial expansion port 2777 (e.g., USB), and a network controller 2734. The data storage 2724 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage devices.

[0315] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 27 An exemplary SoC may be shown. In at least one embodiment, Figure 27 The devices shown therein may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the system 2700 use a Compute Express Link (CXL) interconnect to interconnect.

[0316] Figure 28 A system 2800 according to at least one embodiment is shown. In at least one embodiment, the system 2800 is an electronic device that utilizes a processor 2810. In at least one embodiment, the system 2800 may be, in at least one embodiment but not limited to, a laptop computer, a tower server, a rack server, a blade server, a notebook computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0317] In at least one embodiment, the system 2800 may include, but is not limited to, a processor 2810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 2810 uses a bus or interface coupling, such as I 2A C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3) or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 28 A system is shown that includes interconnected hardware devices or “chips”. In at least one embodiment, Figure 28 An exemplary SoC may be shown. In at least one embodiment, Figure 28 The devices shown in may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 28 One or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0318] In at least one embodiment, Figure 28 May include a display 2824, a touch screen 2825, a touch pad 2830, a Near Field Communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, a Fast Chipset (“EC”) 2835, a Trusted Platform Module (“TPM”) 2838, a BIOS / Firmware / Flash (“BIOS, FW Flash”) 2822, a DSP 2860, a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”) 2820, a Wireless Local Area Network unit (“WLAN”) 2850, a Bluetooth unit 2852, a Wireless Wide Area Network unit (“WWAN”) 2856, a Global Positioning System (GPS) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB3.0 camera) or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented to the LPDDR3 standard in at least one embodiment. These components may each be implemented in any suitable manner.

[0319] In at least one embodiment, other components may be communicatively coupled to the processor 2810 via the components discussed above. In at least one embodiment, the accelerometer 2841, ambient light sensor ("ALS") 2842, compass 2843, and gyroscope 2844 may be communicatively coupled to the sensor hub 2840. In at least one embodiment, the thermal sensor 2839, fan 2837, keyboard 2846, and touchpad 2830 may be communicatively coupled to the EC 2835. In at least one embodiment, the speaker 2863, headset 2864, and microphone ("mic") 2865 may be communicatively coupled to the audio unit ("audio codec and class-D amplifier") 2864, which in turn may be communicatively coupled to the DSP 2860. In at least one embodiment, the audio unit 2864 may include, but is not limited to, an audio encoder / decoder ("codec") and a class-D amplifier. In at least one embodiment, the SIM card ("SIM") 2857 may be communicatively coupled to the WWAN unit 2856. In at least one embodiment, components such as the WLAN unit 2850, the Bluetooth unit 2852, and the WWAN unit 2856 may be implemented in a next-generation form factor (NGFF).

[0320] Figure 29 An exemplary integrated circuit 2900 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 2900 is a SoC that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 2900 includes peripheral or bus logic that includes a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an 2 S / I 2 C controller 2940. In at least one embodiment, the integrated circuit 2900 may include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a Mobile Industry Processor Interface (MIPI) display interface 2955. In at least one embodiment, storage may be provided by a flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970.

[0321] Figure 30FIG. 3000 shows a computing system 3000 according to at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processors 3002 and a system memory 3004 that communicate via an interconnect path that may include a memory hub 3005. In at least one embodiment, the memory hub 3005 may be a separate component within a chipset component or may be integrated within one or more processors 3002. In at least one embodiment, the memory hub 3005 is coupled to an I / O subsystem 3011 via a communication link 3006. In at least one embodiment, the I / O subsystem 3011 includes an I / O hub 3007 that enables the computing system 3000 to receive input from one or more input devices 3008. In at least one embodiment, the I / O hub 3007 enables a display controller, which is included in one or more processors 3002, to provide output to one or more display devices 3010A. In at least one embodiment, one or more display devices 3010A coupled to the I / O hub 3007 may include local, internal, or embedded display devices.

[0322] In at least one embodiment, the processing subsystem 3001 includes one or more parallel processors 3012 coupled to the memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, the communication link 3013 may be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 3012 form a parallel or vector processing system in a computing concentration that may include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 3012 form a graphics processing subsystem that can output pixels to one of the one or more display devices 3010A coupled via the I / O hub 3007. In at least one embodiment, one or more parallel processors 3012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 3010B.

[0323] In at least one embodiment, the system storage unit 3014 can be connected to the I / O hub 3007 to provide a storage mechanism for the computing system 3000. In at least one embodiment, the I / O switch 3016 can be used to provide an interface mechanism to enable connections between the I / O hub 3007 and other components, such as a network adapter 3018 and / or a wireless network adapter 3019 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 3020. In at least one embodiment, the network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0324] In at least one embodiment, the computing system 3000 can include other components not explicitly shown, including USB or other port connections, an optical storage drive, a video capture device, and / or variants thereof, which can also be connected to the I / O hub 3007. In at least one embodiment, the communication paths interconnecting the Figure 30 various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0325] In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for graphics and video processing (in at least one embodiment, including video output circuitry) and constitute a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, one or more parallel processors 3012, the memory hub 3005, the processor 3002, and the I / O hub 3007 can be integrated into a System-on-Chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 3000 can be integrated into a single package to form a System-in-Package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 3000 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I / O subsystem 3011 and the display device 3010B are omitted from the computing system 3000.

[0326] Processing system

[0327] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0328] Figure 31 An Accelerated Processing Unit (“APU”) 3100 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 3100 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 3100 includes, but is not limited to, a Core Complex 3110, a Graphics Complex 3140, a fabric 3160, an I / O interface 3170, a Memory Controller 3180, a Display Controller 3192, and a Multimedia Engine 3194. In at least one embodiment, the APU 3100 can include any combination of, but is not limited to, any number of Core Complexes 3110, any number of Graphics Complexes 3140, any number of Display Controllers 3192, and any number of Multimedia Engines 3194. For illustrative purposes, multiple instances of like objects are denoted herein by reference numerals, where the reference numeral identifies the object and the number in parentheses identifies the instance desired.

[0329] In at least one embodiment, the Core Complex 3110 is a CPU, the Graphics Complex 3140 is a GPU, and the APU 3100 is a processing unit that integrates, but is not limited to, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to the Core Complex 3110 while other tasks can be assigned to the Graphics Complex 3140. In at least one embodiment, the Core Complex 3110 is configured to execute the main control software associated with the APU 3100, such as an operating system. In at least one embodiment, the Core Complex 3110 is the main processor of the APU 3100 that controls and coordinates the operation of other processors. In at least one embodiment, the Core Complex 3110 issues commands that control the operation of the Graphics Complex 3140. In at least one embodiment, the Core Complex 3110 can be configured to execute host-executable code derived from CUDA source code, and the Graphics Complex 3140 can be configured to execute device-executable code derived from CUDA source code.

[0330] In at least one embodiment, the Core Complex 3110 includes, but is not limited to, cores 3120(1)-3120(4) and an L3 cache 3130. In at least one embodiment, the Core Complex 3110 can include any combination of, but is not limited to, any number of cores 3120 and any number and type of caches. In at least one embodiment, the cores 3120 are configured to execute instructions of a particular Instruction Set Architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0331] In at least one embodiment, each core 3120 includes, but is not limited to, a fetch / decode unit 3122, an integer execution engine 3124, a floating-point execution engine 3126, and an L2 cache 3128. In at least one embodiment, the fetch / decode unit 3122 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3124 and the floating-point execution engine 3126. In at least one embodiment, the fetch / decode unit 3122 can dispatch one micro-instruction to the integer execution engine 3124 and another micro-instruction to the floating-point execution engine 3126 simultaneously. In at least one embodiment, the integer execution engine 3124 performs operations not limited to integers and memory operations. In at least one embodiment, the floating-point engine 3126 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3122 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 3124 and the floating-point execution engine 3126.

[0332] In at least one embodiment, each core 3120(i) can access the L2 cache 3128(i) included in the core 3120(i), where i is an integer representing a specific instance of the core 3120. In at least one embodiment, each core 3120 included in the core complex 3110(j) is connected to other cores 3120 included in the core complex 3110(j) via the L3 cache 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, the cores 3120 included in the core complex 3110(j) can access all of the L3 caches 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, the L3 cache 3130 can include, but is not limited to, any number of slices.

[0333] In at least one embodiment, the graphics complex 3140 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 3140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 3140 is configured to perform operations unrelated to graphics. In at least one embodiment, the graphics complex 3140 is configured to perform operations related to graphics and operations unrelated to graphics.

[0334] In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and an L2 cache 3142. In at least one embodiment, the compute units 3150 share the L2 cache 3142. In at least one embodiment, the L2 cache 3142 is partitioned. In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of dedicated graphics hardware.

[0335] In at least one embodiment, each compute unit 3150 includes, but is not limited to, any number of SIMD units 3152 and a shared memory 3154. In at least one embodiment, each SIMD unit 3152 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 3150 can execute any number of thread blocks, but each thread block is executed on a single compute unit 3150. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3152 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can synchronize together and communicate via the shared memory 3154.

[0336] In at least one embodiment, the fabric 3160 is a system interconnect that facilitates data and control transfers across the core complex 3110, the graphics complex 3140, the I / O interface 3170, the memory controller 3180, the display controller 3192, and the multimedia engine 3194. In at least one embodiment, in addition to or instead of the fabric 3160, the APU 3100 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to the APU 3100. In at least one embodiment, the I / O interface 3170 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to the I / O interface 3170. In at least one embodiment, the peripheral devices coupled to the I / O interface 3170 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0337] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., a liquid crystal display (LCD) device). In at least one embodiment, the multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, the memory controller 3180 facilitates data transfers between the APU 3100 and the unified system memory 3190. In at least one embodiment, the core complex 3110 and the graphics complex 3140 share the unified system memory 3190.

[0338] In at least one embodiment, the APU 3100 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 3100 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which may be component-private or shared among any number of components (e.g., cores 3120, core complex 3110, SIMD units 3152, compute units 3150, and graphics complex 3140).

[0339] Figure 32Shows a CPU 3200 according to at least one embodiment. In at least one embodiment, the CPU 3200 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 3200 can be configured to execute application programs. In at least one embodiment, the CPU 3200 is configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 3200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 3200 can be configured to execute host-executable code derived from CUDA source code, and the external GPU can be configured to execute device-executable code derived from such CUDA source code. In at least one embodiment, the CPU 3200 includes, but is not limited to, any number of core complexes 3210, a structure 3260, an I / O interface 3270, and a memory controller 3280.

[0340] In at least one embodiment, the core complex 3210 includes, but is not limited to, cores 3220(1)-3220(4) and an L3 cache 3230. In at least one embodiment, the core complex 3210 can include, but is not limited to, any number of cores 3220 and any combination of any number and type of caches. In at least one embodiment, the cores 3220 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 3220 is a CPU core.

[0341] In at least one embodiment, each core 3220 includes, but is not limited to, an instruction fetch / decoding unit 3222, an integer execution engine 3224, a floating-point execution engine 3226, and an L2 cache 3228. In at least one embodiment, the instruction fetch / decoding unit 3222 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3224 and the floating-point execution engine 3226. In at least one embodiment, the instruction fetch / decoding unit 3222 can dispatch one micro-instruction to the integer execution engine 3224 and another micro-instruction to the floating-point execution engine 3226 simultaneously. In at least one embodiment, the integer execution engine 3224 executes operations not limited to integers and memory. In at least one embodiment, the floating-point engine 3226 executes operations not limited to floating-point and vector operations. In at least one embodiment, the instruction fetch / decoding unit 3222 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 3224 and the floating-point execution engine 3226.

[0342] In at least one embodiment, each core 3220(i) may access the L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a specific instance of the core 3220. In at least one embodiment, each core 3220 included in the core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via the L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, the cores 3220 included in the core complex 3210(j) may access all of the L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, the L3 cache 3230 may include, but is not limited to, any number of slices.

[0343] In at least one embodiment, the fabric 3260 is a system interconnect that facilitates data and control transfers across the core complexes 3210(1)-3210(N) (where N is an integer greater than zero), the I / O interfaces 3270, and the memory controller 3280. In at least one embodiment, in addition to or instead of the fabric 3260, the CPU 3200 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to the CPU 3200. In at least one embodiment, the I / O interface 3270 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to the I / O interface 3270. In at least one embodiment, the peripheral devices coupled to the I / O interface 3270 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0344] In at least one embodiment, the memory controller 3280 facilitates data transfer between the CPU 3200 and the system memory 3290. In at least one embodiment, the core complex 3210 and the graphics complex 3240 share the system memory 3290. In at least one embodiment, the CPU 3200 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3280 and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, the CPU 3200 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which may be private to a component or shared among any number of components (e.g., cores 3220 and core complex 3210).

[0345] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for a plurality of graphics processing engines in a plurality of graphics acceleration modules. Each graphics processing engine may include a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU having a plurality of graphics processing engines. In at least one embodiment, the graphics processing engine may be individual GPUs integrated on a common package, line card, or chip.

[0346] The application virtual address space 3382 within the system memory 3314 stores process elements 3383. In one embodiment, the process elements 3383 are stored in response to a GPU call 3381 from an application 3380 executing on the processor 3307. The process element 3383 contains the processing state of the corresponding application 3380. The work descriptor (WD) 3384 contained in the process element 3383 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 3384 is a pointer to a job request queue within the application virtual address space 3382.

[0347] The graphics acceleration module 3346 and / or individual graphics processing engines may be shared by all or part of the processes in the system. In at least one embodiment, an infrastructure may be included for establishing a processing state and sending the WD 3384 to the graphics acceleration module 3346 to start a job in a virtualized environment.

[0348] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 3346 or an individual graphics processing engine. Since the graphics acceleration module 3346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 3346 is allocated.

[0349] In operation, the WD fetch unit 3391 in the accelerator integrated slice 3390 fetches the next WD 3384, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 3346. Data from the WD 3384 can be stored in the register 3345 and used by the memory management unit (MMU) 3339, the interrupt management circuit 3347, and / or the context management circuit 3348, as shown. At least one embodiment of the MMU 3339 includes a segment / page walk circuit for accessing the segment / page table 3386 within the OS virtual address space 3385. The interrupt management circuit 3347 can process interrupt events (INT) 3392 received from the graphics acceleration module 3346. When performing a graphics operation, the effective address 3393 generated by the graphics processing engine is translated into a physical address by the MMU 3339.

[0350] In one embodiment, the same register set 3345 is replicated for each graphics processing engine and / or the graphics acceleration module 3346 and can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 3390. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0351] Table 1 – Registers Initialized by the Hypervisor

[0352] 1 Slice Control Register 2 Real Address (RA) Programmed Processing Area Pointer 3 Authorization Mask Override Register 4 Interrupt Vector Table Input Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0353] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0354] Table 2 – Operating System Initialized Registers

[0355]

[0356]

[0357] In one embodiment, each WD 3384 is specific to a particular graphics acceleration module 3346 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to do work or work, or it can be a pointer to a memory location where an application has established a command queue of work to be done.

[0358] Figures 34A - 34B An exemplary graphics processor in accordance with at least one embodiment herein is shown. In at least one embodiment, any exemplary graphics processor can be fabricated using one or more IP cores. In addition to what is illustrated, other logic and circuitry can be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general processor cores. In at least one embodiment, the exemplary graphics processor is for use within a SoC.

[0359] Figure 34A An exemplary graphics processor 3410 of a SoC integrated circuit in accordance with at least one embodiment is shown, which can be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of a SoC integrated circuit in accordance with at least one embodiment is shown, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 34A the graphics processor 3410 is a low-power graphics processor core. In at least one embodiment, Figure 34B the graphics processor 3440 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be Figure 5 a variant of the graphics processor 510.

[0360] In at least one embodiment, the graphics processor 3410 includes a vertex processor 3405 and one or more fragment processors 3415A - 3415N (e.g., 3415A, 3415B, 3415C, 3415D to 3415N - 1, and 3415N). In at least one embodiment, the graphics processor 3410 may execute different shader programs via separate logic such that the vertex processor 3405 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 3415A - 3415N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, the vertex processor 3405 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 3415A - 3415N use the primitives and vertex data generated by the vertex processor 3405 to generate a frame buffer to be displayed on a display device. In at least one embodiment, the fragment processors 3415A - 3415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0361] In at least one embodiment, the graphics processor 3410 additionally includes one or more MMUs 3420A - 3420B, caches 3425A - 3425B, and circuit interconnects 3430A - 3430B. In at least one embodiment, the one or more MMUs 3420A - 3420B provide virtual - to - physical address mapping for the graphics processor 3410, including for the vertex processor 3405 and / or the fragment processors 3415A - 3415N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3425A - 3425B. In at least one embodiment, the one or more MMUs 3420A - 3420B may be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 5 one or more application processors 505, image processors 515, and / or video processors 520 of the system, such that each processor 505 - 520 can participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnects 3430A - 3430B enable the graphics processor 3410 to connect to other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0362] In at least one embodiment, the graphics processor 3440 includes Figure 34AOne or more MMUs 3420A - 3420B, caches 3425A - 3425B, and circuit interconnects 3430A - 3430B of the graphics processor 3410. In at least one embodiment, the graphics processor 3440 includes one or more shader cores 3455A - 3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, to 3455N - 1 and 3455N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 3440 includes an inter - core task manager 3445, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A - 3455N and a tiling unit 3458 to accelerate tiling operations for tile - based rendering, where the rendering operation of the scene is subdivided in the image space, e.g., to take advantage of local spatial coherence within the scene or optimize the use of internal caches.

[0363] Figure 35A Shows a graphics core 3500 according to at least one embodiment. In at least one embodiment, the graphics core 3500 can be included within Figure 24 the graphics processor 2410. In at least one embodiment, the graphics core 3500 can be Figure 34B the unified shader cores 3455A - 3455N in. In at least one embodiment, the graphics core 3500 includes a shared instruction cache 3502, texture units 3518, and cache / shared memory 3520, which are shared by the execution resources within the graphics core 3500. In at least one embodiment, the graphics core 3500 can include multiple slices 3501A - 3501N or partitions per core, and the graphics processor can include multiple instances of the graphics core 3500. The slices 3501A - 3501N can include support logic, which includes local instruction caches 3504A - 3504N, thread schedulers 3506A - 3506N, thread dispatchers 3508A - 3508N, and a set of registers 3510A - 3510N. In at least one embodiment, the slices 3501A - 3501N can include a set of additional functional units (AFU) 3512A - 3512N, floating - point units (FPU) 3514A - 3514N, integer arithmetic logic units (ALU) 3516A - 3516N, address calculation units (ACU) 3513A - 3513N, double - precision floating - point units (DPFPU) 3515A - 3515N, and matrix processing units (MPU) 3517A - 3517N.

[0364] In one embodiment, the FPUs 3514A - 3514N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while the DPFPU 3515A - 3515N can perform double - precision (64 - bit) floating - point operations. In at least one embodiment, the ALUs 3516A - 3516N can perform variable - precision integer operations at 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, the MPUs 3517A - 3517N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, the MPUs 3517A - 3517N can perform various matrix operations to accelerate CUDA programs, including enabling accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, the AFUs 3512A - 3512N can perform additional logical operations not supported by the floating - point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0365] Figure 35B A general - purpose graphics processing unit (GPGPU) 3530 is shown in at least one embodiment. In at least one embodiment, the GPGPU 3530 is highly parallel and suitable for deployment on a multi - chip module. In at least one embodiment, the GPGPU 3530 can be configured such that highly parallel computing operations can be performed by a GPU array. In at least one embodiment, the GPGPU 3530 can be directly linked to other instances of the GPGPU 3530 to create a multi - GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, the GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, the host interface 3532 is a PCIe interface. In at least one embodiment, the host interface 3532 can be a vendor - specific communication interface or communication fabric. In at least one embodiment, the GPGPU 3530 receives commands from the host processor and uses a global scheduler 3534 to dispatch execution threads associated with those commands to a set of compute clusters 3536A - 3536H. In at least one embodiment, the compute clusters 3536A - 3536H share a cache memory 3538. In at least one embodiment, the cache memory 3538 can be used as a cache - of - caches for the cache memories within the compute clusters 3536A - 3536H.

[0366] In at least one embodiment, the GPGPU 3530 includes memories 3544A-3544B coupled to the compute clusters 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, the memories 3544A-3544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0367] In at least one embodiment, each of the compute clusters 3536A-3536H includes a set of graphics cores, such as Figure 35A the graphics core 3500, which may include various types of integer and floating-point logic units and may perform computational operations at various precisions, including computations suitable for CUDA programs. In at least one embodiment, at least one subset of the floating-point units in each of the compute clusters 3536A-3536H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0368] In at least one embodiment, multiple instances of the GPGPU 3530 may be configured to operate as compute clusters. In at least one embodiment, the compute clusters 3536A-3536H may implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of the GPGPU 3530 communicate via the host interface 3532. In at least one embodiment, the GPGPU 3530 includes an I / O hub 3539 that couples the GPGPU 3530 to the GPU link 3540, enabling direct connection to other instances of the GPGPU 3530. In at least one embodiment, the GPU link 3540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 3530. In at least one embodiment, the GPU link 3540 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 3530 are located in separate data processing systems and communicate via network devices accessible via the host interface 3532. In at least one embodiment, the GPU link 3540 may be configured to be able to connect to a host processor, in addition to or in place of the host interface 3532. In at least one embodiment, the GPGPU 3530 may be configured to execute CUDA programs.

[0369] Figure 36AFIG. 3600 shows a parallel processor 3600 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 3600 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or FPGAs.

[0370] In at least one embodiment, the parallel processor 3600 includes a parallel processing unit 3602. In at least one embodiment, the parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of the parallel processing unit 3602. In at least one embodiment, the I / O unit 3604 may be directly connected to other devices. In at least one embodiment, the I / O unit 3604 is connected to other devices using a hub or switch interface (e.g., memory hub 605). In at least one embodiment, the connection between the memory hub 605 and the I / O unit 3604 forms a communication link. In at least one embodiment, the I / O unit 3604 is connected to a host interface 3606 and a memory crossbar 3616, where the host interface 3606 receives commands for performing processing operations and the memory crossbar 3616 receives commands for performing memory operations.

[0371] In at least one embodiment, when the host interface 3606 receives a command buffer via the I / O unit 3604, the host interface 3606 may direct the work operations to execute those commands to a front end 3608. In at least one embodiment, the front end 3608 is coupled to a scheduler 3610 configured to allocate commands or other work items to a processing array 3612. In at least one embodiment, the scheduler 3610 ensures that the processing array 3612 is properly configured and in an active state before tasks are allocated to the processing array 3612 within the processing array 3612. In at least one embodiment, the scheduler 3610 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the scheduler 3610 implemented by the microcontroller is configurable to perform complex scheduling and work allocation operations at both a coarse-grained and fine-grained level, enabling fast preemption and context switching of threads executing on the processing array 3612. In at least one embodiment, host software may demonstrate a workload for scheduling on the processing array 3612 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically allocated on the processing array 3612 by scheduler 3610 logic within a microcontroller including the scheduler 3610.

[0372] In at least one embodiment, the processing array 3612 may include up to "N" processing clusters (e.g., cluster 3614A, cluster 3614B to cluster 3614N). In at least one embodiment, each of the clusters 3614A - 3614N of the processing array 3612 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 3610 may use various scheduling and / or work assignment algorithms to assign work to the clusters 3614A - 3614N of the processing array 3612, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 3610, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing array 3612. In at least one embodiment, different clusters 3614A - 3614N of the processing array 3612 may be assigned to process different types of programs or to perform different types of computations.

[0373] In at least one embodiment, the processing array 3612 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 3612 is configured to perform general - purpose parallel computing operations. In at least one embodiment, the processing array 3612 may include logic for performing processing tasks, which include filtering of video and / or audio data, performing modeling operations, including physical operations, and performing data transformation.

[0374] In at least one embodiment, the processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 3612 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 3612 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 3602 may transfer data from the system memory via the I / O unit 3604 for processing. In at least one embodiment, during processing, the transferred data may be stored in on - chip memory (e.g., parallel processor memory 3622) during processing and then written back to the system memory.

[0375] In at least one embodiment, when the parallel processing unit 3602 is used to perform graphics processing, the scheduler 3610 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to the multiple clusters 3614A - 3614N of the processing array 3612. In at least one embodiment, portions of the processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen - space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 3614A - 3614N can be stored in a buffer to allow the transfer of the intermediate data between the clusters 3614A - 3614N for further processing.

[0376] In at least one embodiment, the processing array 3612 can receive processing tasks to be executed via the scheduler 3610, which receives commands defining the processing tasks from the front - end 3608. In at least one embodiment, the processing tasks can include indices of the data to be processed, such as can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 3610 can be configured to obtain the index corresponding to the task, or can receive the index from the front - end 3608. In at least one embodiment, the front - end 3608 can be configured to ensure that the processing array 3612 is configured to an effective state before starting the workload specified by the incoming command buffer (e.g., batch - buffer, push - buffer, etc.).

[0377] In at least one embodiment, each of one or more instances of parallel processing unit 3602 may be coupled to parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 may be accessed via memory crossbar 3616, which may receive memory requests from processing array 3612 as well as I / O unit 3604. In at least one embodiment, memory crossbar 3616 may access parallel processor memory 3622 via memory interface 3618. In at least one embodiment, memory interface 3618 may include a plurality of partitioning units (e.g., partitioning unit 3620A, partitioning unit 3620B through partitioning unit 3620N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 3622. In at least one embodiment, the plurality of partitioning units 3620A - 3620N are configured to be equal to the number of memory units such that first partitioning unit 3620A has a corresponding first memory unit 3624A, second partitioning unit 3620B has a corresponding memory unit 3624B, and Nth partitioning unit 3620N has a corresponding Nth memory unit 3624N. In at least one embodiment, the number of partitioning units 3620A - 3620N may not be equal to the number of memory devices.

[0378] In at least one embodiment, memory units 3624A - 3624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A - 3624N may further include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 3624A - 3624N, allowing partitioning units 3620A - 3620N to write portions of each render target in parallel to effectively utilize the available bandwidth of parallel processor memory 3622. In at least one embodiment, a local instance of parallel processor memory 3622 may be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0379] In at least one embodiment, any one of clusters 3614A - 3614N of processing array 3612 can process data to be written into any of memory cells 3624A - 3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transfer the output of each of clusters 3614A - 3614N to any of partitioning units 3620A - 3620N or to another cluster 3614A - 3614N, where the cluster 3614A - 3614N can perform additional processing operations on the output. In at least one embodiment, each of clusters 3614A - 3614N can communicate with memory interface 3618 through memory crossbar 3616 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 3616 has a connection to memory interface 3618 to communicate with I / O unit 3604 and a connection to a local instance of parallel processor memory 3622, enabling processing units within different processing clusters 3614A - 3614N to communicate with system memory or other memories that are not local to parallel processing unit 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate the traffic flow between clusters 3614A - 3614N and partitioning units 3620A - 3620N.

[0380] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single insertion card, or multiple insertion cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate with each other, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. In at least one embodiment, some instances of parallel processing unit 3602 can include floating - point units with higher precision relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 3602 or parallel processor 3600 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0381] Figure 36B Processing cluster 3694 is shown in accordance with at least one embodiment. In at least one embodiment, processing cluster 3694 is included within a parallel processing unit. In at least one embodiment, processing cluster 3694 is Figure 36AAn instance of one of the processing clusters 3614A - 3614N. In at least one embodiment, the processing cluster 3694 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 3694.

[0382] In at least one embodiment, the operation of the processing cluster 3694 can be controlled by assigning processing tasks to the pipeline manager 3632 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 3632 receives instructions from Figure 36A the scheduler 3610, and manages the execution of these instructions through the graphics multiprocessor 3634 and / or the texture unit 3636. In at least one embodiment, the graphics multiprocessor 3634 is an exemplary instance of the SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 3694. In at least one embodiment, one or more instances of the graphics multiprocessor 3634 can be included within the processing cluster 3694. In at least one embodiment, the graphics multiprocessor 3634 can process data, and the data crossbar 3640 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 3632 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 3640.

[0383] In at least one embodiment, each graphics multiprocessor 3634 within the processing cluster 3694 can include the same set of functional execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the functional execution logic can be configured in a pipeline manner, where new instructions can be issued before the previous instructions are completed. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0384] In at least one embodiment, the instructions transmitted to processing cluster 3694 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 3634. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 3634. In at least one embodiment, when the number of threads included in a thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 3634. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 3634, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 3634.

[0385] In at least one embodiment, graphics multiprocessor 3634 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 3634 can forgo the internal cache and use the cache memory within processing cluster 3694 (e.g., L1 cache 3648). In at least one embodiment, each graphics multiprocessor 3634 can also access the L2 cache within the partition units (e.g., Figure 36A partition units 3620A - 3620N) of the partition unit, which are shared among all processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634, which can share common instructions and data that can be stored in L1 cache 3648.

[0386] In at least one embodiment, each processing cluster 3694 can include an MMU 3645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 3645 can reside in Figure 36Awithin the memory interface 3618. In at least one embodiment, the MMU 3645 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more information about tiles is discussed) and optionally to cache line indices. In at least one embodiment, the MMU 3645 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 3634 or the L1 cache 3648 or the processing cluster 3694. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving among partition units. In at least one embodiment, cache line indices can be used to determine whether a request to a cache line is a hit or a miss.

[0387] In at least one embodiment, the processing cluster 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 3634 as needed and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 3634 outputs the processed tasks to the data crossbar 3640 to provide the processed tasks to another processing cluster 3694 for further processing or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 3616. In at least one embodiment, the raster operation unit (preROP) 3642 is configured to receive data from the graphics multiprocessor 3634 and direct the data to the ROP unit, which may be located together with the partition units (e.g., Figure 36A the partition units 3620A - 3620N) described herein. In at least one embodiment, the PreROP 3642 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0388] Figure 36C illustrates a graphics multiprocessor 3696 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 3696 is Figure 36BGraphics multiprocessor 3634. In at least one embodiment, graphics multiprocessor 3696 is coupled to pipeline manager 3632 of processing cluster 3694. In at least one embodiment, graphics multiprocessor 3696 has an execution pipeline that includes, but is not limited to, instructio...

Claims

1. A data center cooling system, comprising: A cold plate, comprising: An evaporator for removing heat from at least one computing device using a two-phase fluid, the evaporator being associated with a buffer for performing flow stabilization represented by different volumes or different flow rates of the two-phase fluid, the two-phase fluid being enabled to flow between the evaporator and a condensation or compressor unit located outside the cold plate; A first microchannel, which serves as a heat exchange tube for conducting the two-phase fluid; and A second microchannel formed by raised fins from the cold plate for conducting an auxiliary coolant in an auxiliary cooling circuit.

2. The data center cooling system according to claim 1, further comprising: At least one processor for determining the temperature associated with the at least one computing device and for enabling a flow controller to provide a two-phase fluid circuit between the evaporator, the buffer, and the condensation or compressor unit.

3. The data center cooling system according to claim 1, further comprising: At least one flow controller associated with the buffer or the cold plate, the at least one flow controller for causing the different volumes or different flow rates using at least partially the two-phase fluid from the buffer, based at least in part on the cooling requirements of the at least one computing device.

4. The data center cooling system according to claim 1, further comprising: The condensation or compressor unit, associated with a rack, for discharging at least a portion of the heat to a hot aisle of the data center.

5. The data center cooling system according to claim 1, further comprising: At least one processor for receiving sensor input from a sensor associated with the at least one computing device, the at least one processor for enabling a two-phase fluid circuit to provide cooling for the at least one computing device and for providing the flow stabilization using the buffer.

6. The data center cooling system according to claim 5, further comprising: One or more neural networks for receiving the sensor input and for inferring the cooling requirements of the two-phase fluid circuit.

7. The data center cooling system according to claim 1, further comprising: At least one processor for enabling at least one flow controller to cause the two-phase fluid of the different volumes or different flow rates to pass through the evaporator and for preventing the auxiliary coolant from flowing into the auxiliary cooling circuit.

8. The data center cooling system according to claim 1, wherein the two-phase fluid is a refrigerant or an engineered fluid.

9. The data center cooling system according to claim 1, further comprising: At least one flow controller associated with an R2A heat exchanger, the buffer, and the auxiliary cooling circuit, the at least one flow controller for supporting the two-phase fluid of the different volumes or different flow rates through the R2A heat exchanger and the buffer and for preventing the auxiliary coolant from flowing into the auxiliary cooling circuit.

10. The data center cooling system according to claim 1, further comprising: At least one processor for enabling a first mode of a data center cooling system to provide cooling using a first volume or flow rate of the different volumes or flow rates, and for enabling a second mode of the data center cooling system to provide cooling using a second volume or flow rate of the different volumes or flow rates.

11. A processor includes one or more circuits for sensing a cooling requirement of at least one computing device. The processor is configured to cause a cold plate to provide cooling for the at least one computing device using an evaporator within the cold plate to remove heat from the at least one computing device via a two-phase fluid. The evaporator is associated with a buffer for performing flow stabilization represented by different volumes or different flow rates of the two-phase fluid. The two-phase fluid is enabled to flow between the evaporator and a condensation or compressor unit located outside the cold plate, wherein, The cold plate includes: a first microchannel, which serves as a heat exchange tube for conducting the two-phase fluid; and a second microchannel, which is formed by raised fins from the cold plate for conducting an auxiliary coolant in an auxiliary cooling circuit.

12. The processor according to claim 11, further comprising: An output for providing a signal to at least one flow controller to enable the two-phase fluid to flow through the R2A heat exchanger and the buffer, and to prevent the auxiliary coolant from flowing into the auxiliary cooling circuit.

13. The processor according to claim 11, further comprising: An input for receiving sensor input from a sensor associated with the at least one computing device, the processor for determining a first cooling requirement associated with a two-phase fluid circuit and a second cooling requirement associated with the auxiliary cooling circuit, the auxiliary cooling circuit being associated with a main cooling circuit.

14. The processor according to claim 13, further comprising: One or more neural networks for receiving the sensor input and for inferring the first cooling requirement and the second cooling requirement.

15. The processor according to claim 11, further comprising: One or more neural networks for inferring a fault in the auxiliary cooling circuit, the one or more circuits for causing at least one flow controller to activate the two-phase fluid circuit using the buffer, the cold plate, and the condensation or compressor unit.

16. A processor includes one or more circuits for training one or more neural networks to infer a cooling requirement from sensor inputs of sensors associated with a computing device, the processor for causing a cold plate to provide cooling for the computing device using an evaporator within the cold plate to remove heat from the computing device by a two-phase fluid, the evaporator being associated with a buffer for performing flow stabilization represented by different volumes or different flow rates of the two-phase fluid, the two-phase fluid being enabled to flow between the evaporator and a condensation or compressor unit located outside the cold plate, wherein, The cold plate includes: a first microchannel, which serves as a heat exchange tube for conducting the two-phase fluid; and a second microchannel, which is formed by raised fins from the cold plate for conducting an auxiliary coolant in an auxiliary cooling circuit.

17. The processor according to claim 16, further comprising: An output for providing a signal to at least one flow controller to enable the two-phase fluid to flow through the R2A heat exchanger and the buffer, and to prevent the auxiliary coolant from flowing into the auxiliary cooling circuit.

18. The processor according to claim 16, further comprising: The one or more neural networks for receiving the sensor input and being trained to infer a first cooling requirement associated with a two-phase fluid circuit and a second cooling requirement associated with the auxiliary cooling circuit, the auxiliary cooling circuit being associated with a main cooling circuit.

19. The processor according to claim 16, further comprising: An output for providing a signal to adjust one or more of the two-phase fluid circuit or the auxiliary cooling circuit to address different cooling requirements.

20. The processor according to claim 16, further comprising: Input for receiving the sensor input associated with temperature from the at least one computing device, the auxiliary coolant, or the two-phase fluid, where one or more neural networks are trained to reason about a change in coolant state having occurred, at least in part, based on the temperature and a previous temperature, and one or more circuits for enabling or disabling a two-phase fluid loop using the buffer, the cold plate, and the condensation or compressor unit.

21. A processor, comprising one or more circuits, the one or more circuits including one or more neural networks, the one or more neural networks for inferring a cooling requirement from sensor inputs of sensors associated with a computing device, the processor for causing a cold plate to provide cooling for the computing device using an evaporator within the cold plate to remove heat from the computing device by a two-phase fluid, the evaporator being associated with a buffer for performing flow stabilization represented by different volumes or different flow rates of the two-phase fluid, the two-phase fluid being enabled to flow between the evaporator and a condensation or compressor unit located outside the cold plate, wherein, The cold plate includes: a first microchannel, serving as a heat exchange tube, for conducting the two-phase fluid; and a second microchannel, formed by raised fins from the cold plate, for conducting an auxiliary coolant in an auxiliary cooling loop.

22. The processor of claim 21, further comprising: Output for providing a signal to at least one flow controller to enable the two-phase fluid to flow through an R2A heat exchanger and the buffer, and to prevent the auxiliary coolant from flowing into the auxiliary cooling loop.

23. The processor of claim 21, further comprising: The one or more neural networks for receiving the sensor input and reasoning about a first cooling requirement associated with the two-phase fluid loop and a second cooling requirement associated with the auxiliary cooling loop, the auxiliary cooling loop being associated with a main cooling loop.

24. The processor of claim 21, further comprising: Output for providing a signal to adjust one or more of the two-phase fluid loop or the auxiliary cooling loop to address different cooling requirements.

25. The processor of claim 21, further comprising: Input for receiving the sensor input associated with temperature from the at least one computing device, the auxiliary coolant, or the two-phase fluid, the one or more neural networks for reasoning about a change in coolant state having occurred, at least in part, based on the temperature and a previous temperature, and one or more circuits for enabling or disabling a two-phase fluid loop using the buffer, the cold plate, and the condensation or compressor unit.

26. A method for a data center cooling system, comprising: Providing a cold plate including an evaporator for removing heat from at least one computing device using a two-phase fluid, where the cold plate further includes: a first microchannel, serving as a heat exchange tube, for conducting the two-phase fluid; and a second microchannel, formed by raised fins from the cold plate, for conducting an auxiliary coolant in an auxiliary cooling loop; Determining a cooling requirement of at least one computing device of a rack; Enabling the cold plate to absorb heat from the at least one computing device using the two-phase fluid; and Enabling a buffer to perform flow stabilization represented by different volumes or different flow rates of the two-phase fluid, the two-phase fluid being enabled to flow between the evaporator and a condensation or compressor unit located external to the cold plate.

27. The method of claim 26, further comprising: Determining, using at least one processor, a temperature associated with the at least one computing device in the rack; Determining a first cooling requirement or a second cooling requirement using the temperature; And Causing, at least in part based on the first cooling requirement or the second cooling requirement, a two-phase fluid loop or the auxiliary cooling loop, the auxiliary cooling loop being associated with a main cooling loop.

28. The method of claim 27, further comprising: Receiving, in the at least one processor, sensor input from sensors associated with the at least one computing device, the rack, the auxiliary coolant, or the two-phase fluid; And Using the at least one processor to determine the first cooling requirement and the second cooling requirement at least in part based on the sensor input.

29. The method of claim 26, further comprising: Enabling an R2A heat exchanger to dissipate heat to a hot aisle within the data center.

30. The method of claim 26, further comprising: Receiving, by at least one processor, sensor input from sensors associated with the at least one computing device; Determining, by the at least one processor, a change in coolant state at least in part based on the sensor input; And Causing, at least in part based on the change in the coolant state, the two-phase fluid loop to be enabled using the buffer, the cold plate, and the condensing or compressor unit.

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