Chip verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the application discloses a chip verification method and device, electronic equipment and a storage medium, relates to the field of integrated circuit verification, and can effectively improve chip verification efficiency and simplify circuit error positioning. The method comprises the following steps: in dynamic simulation of a chip, according to a preset signal acquisition rule, a signal level of a preset bit point in the chip is acquired, wherein the chip comprises a plurality of power domains, and the signal acquisition rule comprises an acquisition rule of a signal related to power domain transformation in the chip; according to a signal comparison rule corresponding to the signal level of the preset bit point, a comparison operation is performed on the signal level; and according to a comparison result, whether the preset bit point in the chip has a circuit error related to power domain transformation is determined. The application can be used for verifying power management work of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit verification, and in particular to a chip verification method and device, an electronic device, and a storage medium. BACKGROUND

[0002] In the field of integrated circuits, a chip design needs to be verified on a verification platform before being taped out to ensure the correctness of the chip design. However, traditional chip verification can only verify the functions of the chip, and cannot perform power management and low-power verification on the chip. Specifically, the implementation of a low-power SOC (system on chip) design is mainly achieved by providing different voltages for different functional areas on the chip and performing corresponding power management. In traditional functional verification, the excitation signal cannot reflect the influence of voltage input of different power domains on the circuit design.

[0003] In order to be able to verify the power management and power consumption of the chip, a technology is proposed to include the influence of the power network and voltage drive on the design into functional simulation. A report file including multi-power domain checks can be output during the compilation process, including reports related to power network connection and power control, so as to be checked by design verification personnel. However, this technology can only output the corresponding simulation waveform in dynamic simulation, and the specific checking of the chip behavior still needs the verification personnel to further judge according to the output simulation waveform, resulting in low chip verification efficiency and difficulty in error positioning. SUMMARY

[0004] Therefore, the embodiments of the present application provide a chip verification method and device, an electronic device, and a storage medium, which can effectively improve the chip verification efficiency and simplify the positioning of circuit errors.

[0005] In a first aspect, the embodiments of the present application provide a chip verification method, comprising: in dynamic simulation of a chip, acquiring a signal level of a preset site in the chip according to a preset signal acquisition rule, wherein the chip comprises a plurality of power domains, and the signal acquisition rule comprises an acquisition rule of a signal related to power domain transformation in the chip; performing a comparison operation on the signal level according to a signal comparison rule corresponding to the signal level; and determining whether the preset site in the chip has a circuit error related to power domain transformation according to a comparison result.

[0006] In an embodiment, the acquisition rule of the signal related to power domain transformation comprises at least one of the following:

[0007] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, an on-power signal and / or a reset signal of a corresponding site of the circuit module is acquired to form a corresponding first power-on sequence and / or a first reset sequence;

[0008] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, preset behavior information of the chip is acquired, and the behavior information includes at least one of the following: self-checking information of a read-only memory, clock establishment information;

[0009] When the power domain transformation occurs, a signal level of each cross-power-domain signal is acquired according to a signal list of the cross-power-domain signals in the chip;

[0010] When the power domain transformation causes the power of at least one circuit module in the chip to be turned off, a clamping level maintained by a blocking unit corresponding to a cross-power-domain signal in the at least one circuit module is acquired;

[0011] When the power domain transformation causes a reset of a cross-power-domain signal, a reset level of the cross-power-domain signal is acquired, and when the power domain transformation causes the power of the cross-power-domain signal to be turned off, a clamping level maintained by a blocking unit corresponding to the cross-power-domain signal is acquired;

[0012] When the power domain of at least one circuit module in the chip is switched, power domain switching information of the at least one circuit module is acquired to obtain a power domain switching sequence of the at least one circuit module;

[0013] When the power domain transformation causes the power of at least one circuit module in the chip to be turned off, the temporarily stored data in a register and / or a memory unit performing a data retention operation in the at least one circuit module is acquired, and when the at least one circuit module is powered on again, a signal level of a site corresponding to the register and / or the memory unit is acquired.

[0014] In an embodiment, the comparison operation on the signal level according to the signal comparison rule of the preset site corresponding signal level includes at least one of the following:

[0015] Whether the first power-on sequence is consistent with a preset second power-on sequence is compared, and / or whether the first reset sequence is consistent with a preset second reset sequence is compared;

[0016] Whether the behavior information of the chip is consistent with preset reference information is compared;

[0017] The relationship between the signal level of each cross-power-domain signal and a preset level is compared to determine whether the signal level of each cross-power-domain signal is an indeterminate state level;

[0018] comparing whether the clamping level maintained by the blocking unit is consistent with a preset clamping level;

[0019] comparing whether the reset level when the cross-power-domain signal occurs reset is consistent with the clamping level when the cross-power-domain signal occurs power-off;

[0020] comparing whether the power domain switching sequence of the circuit module is consistent with a preset power domain switching sequence;

[0021] comparing whether the signal level corresponding to the temporary storage data is consistent with the signal level of the bit point corresponding to the register and / or the memory unit.

[0022] In an embodiment, the first power-on sequence includes a power-on voltage size and a power-on timing of the preset bit point; and the first reset sequence includes a reset level and a reset timing of the preset bit point.

[0023] In an embodiment, after determining whether the preset bit point in the chip has a circuit error related to power domain transformation according to the comparison result, the method further includes: outputting relevant information of the bit point having the circuit error in a verification report, wherein the relevant information includes at least one of the following: bit point position, error type, and error cause.

[0024] In an embodiment, before obtaining the signal level of the preset bit point in the chip according to a preset signal acquisition rule in dynamic simulation of the chip, the method further includes: recording the signal acquisition rule and the signal comparison rule through a script file; and inputting the script file into a test platform of the chip to perform dynamic simulation on the chip according to the test platform, a register-transfer level (RTL) circuit of the chip, and a preset low-power design verification standard.

[0025] In a second aspect, embodiments of the present application further provide a verification device of a chip, including: an obtaining unit configured to obtain a signal level of a preset bit point in a chip according to a preset signal acquisition rule in dynamic simulation of the chip, wherein the chip includes a plurality of power domains, and the signal acquisition rule includes an acquisition rule of a signal related to power domain transformation in the chip; a comparing unit configured to perform a comparison operation on the signal level according to a signal comparison rule corresponding to the signal level of the preset bit point; and a determining unit configured to determine whether the preset bit point in the chip has a circuit error related to power domain transformation according to a comparison result.

[0026] In an embodiment, the acquisition rule of the signal related to power domain transformation includes at least one of the following:

[0027] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, an on-power signal and / or a reset signal of a corresponding site of the circuit module is acquired to form a corresponding first power-on sequence and / or a first reset sequence;

[0028] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, preset behavior information of the chip is acquired, and the behavior information includes at least one of the following: self-checking information of a read-only memory, clock establishment information;

[0029] When the power domain transformation occurs, a signal level of each cross-power-domain signal is acquired according to a signal list of the cross-power-domain signals in the chip;

[0030] When the power domain transformation causes power-off of at least one circuit module in the chip, a clamping level maintained by a blocking unit corresponding to a cross-power-domain signal in the at least one circuit module is acquired;

[0031] When the power domain transformation causes a reset of a cross-power-domain signal, a reset level of the cross-power-domain signal is acquired, and when the power domain transformation causes power-off of the cross-power-domain signal, a clamping level maintained by a blocking unit corresponding to the cross-power-domain signal is acquired;

[0032] When a power domain of at least one circuit module in the chip is switched, power domain switching information of the at least one circuit module is acquired to obtain a power domain switching sequence of the at least one circuit module;

[0033] When the power domain transformation causes power-off of at least one circuit module in the chip, temporary data in a register and / or a memory unit performing a data retention operation in the at least one circuit module is acquired, and when the at least one circuit module is powered on again, a signal level of a site corresponding to the register and / or the memory unit is acquired.

[0034] In an embodiment, the comparison unit is specifically configured to perform at least one of the following:

[0035] The first power-on sequence is compared with a preset second power-on sequence, and / or the first reset sequence is compared with a preset second reset sequence;

[0036] The behavior information of the chip is compared with preset reference information;

[0037] The signal levels of the cross-power-domain signals are compared with preset levels to determine whether the signal levels of the cross-power-domain signals are indeterminate state levels;

[0038] The clamping level maintained by the blocking unit is compared with a preset clamping level.

[0039] comparing whether the reset level of the cross-power-domain signal when the reset occurs is consistent with the clamping level of the cross-power-domain signal when the power-off occurs;

[0040] comparing whether the power domain switching sequence of the circuit module is consistent with the preset power domain switching sequence;

[0041] comparing whether the signal level corresponding to the temporary storage data is consistent with the signal level of the bit point corresponding to the register and / or the memory unit.

[0042] In an implementation, the first power-on sequence includes a power-on voltage size and a power-on timing of the preset bit point; and the first reset sequence includes a reset level and a reset timing of the preset bit point.

[0043] In an implementation, the apparatus further includes an output unit configured to output, in a verification report, relevant information of the bit point with the circuit error after determining whether the preset bit point in the chip has the circuit error related to the power domain transformation according to the comparison result, wherein the relevant information includes at least one of the following: a bit point position, an error type, and an error cause.

[0044] In an implementation, the apparatus further includes a recording unit configured to record, before acquiring the signal level of the preset bit point in the chip according to a preset signal acquisition rule in dynamic simulation of the chip, the signal acquisition rule and the signal comparison rule through a script file; and an input unit configured to input the script file to a test platform of the chip, so as to perform dynamic simulation on the chip according to the test platform, a register transfer level circuit of the chip, and a preset low-power design verification standard.

[0045] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; and the processor is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute the chip verification method provided by any one of the embodiments of the present application.

[0046] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, which stores one or more programs, and the one or more programs are executable by one or more processors to implement the chip verification method provided by any one of the embodiments of the present application.

[0047] The chip verification method and device, the electronic equipment and the storage medium provided by the embodiment of the present application can acquire the signal level of a preset bit point in a chip according to a preset signal acquisition rule in dynamic simulation of the chip, and perform a comparison operation on the signal level according to a signal comparison rule corresponding to the signal level of the preset bit point. Since the chip includes multiple power domains and the signal acquisition rule includes the acquisition rule of the signal related to the power domain transformation in the chip, the signal level of the signal related to the power domain transformation at the preset bit point in the dynamic simulation of the chip can be acquired in time, and the comparison operation is performed on the signal level according to the signal comparison rule corresponding to each preset bit point, so that whether the preset bit point has a circuit error related to the power domain transformation is determined according to the comparison result. The whole process does not require a technician to perform complex simulation waveform analysis and problem finding on the circuit behavior, and therefore the chip verification efficiency is improved and the positioning of the circuit error is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0049] Figure 1 A flow chart of the chip verification method provided by the embodiment of the present application;

[0050] Figure 2 A schematic diagram of the verification environment input and output file in the chip verification method provided by the embodiment of the present application;

[0051] Figure 3 A structural schematic diagram of the chip verification device provided by the embodiment of the present application;

[0052] Figure 4 A structural schematic diagram of the electronic equipment provided by the embodiment of the present application. DETAILED DESCRIPTION

[0053] The embodiments of the present application will be described in detail below with reference to the drawings.

[0054] It should be clear that the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0055] In a first aspect, embodiments of the present application provide a chip verification method, which can effectively improve chip verification efficiency and simplify circuit error positioning.

[0056] As shown in Figure 1 embodiments of the present application provide a chip verification method, which comprises:

[0057] S11, in dynamic simulation of a chip, a signal level of a preset bit point in the chip is acquired according to a preset signal acquisition rule, wherein the chip comprises a plurality of power domains, and the signal acquisition rule comprises an acquisition rule of a signal related to power domain transformation in the chip;

[0058] In embodiments of the present application, dynamic simulation of a chip can comprise an activity of applying various verification use cases to a reference model of the chip in a verification platform to verify chip power management. Optionally, in an embodiment of the present application, verification of chip power management can also be integrated in the same verification environment as functional verification of the chip, so as to combine power management verification and functional verification.

[0059] In order to effectively reduce chip power consumption, two or even more different power supply voltages can be provided in the same chip, and different power supply voltages are provided for different functional areas of the chip, or different power supply voltages are provided for the same functional area under different conditions. Such a chip is a chip comprising a plurality of power domains. In operation of a multi-power-domain chip, transformation of various circuit module power domains in the chip can cause changes in signal levels of related bit points in the circuit. Part or all of these related bit points can be defined as preset bit points. Optionally, the corresponding preset bit points when each power domain is transformed can be one or multiple, which is not limited in embodiments of the present application.

[0060] In order to verify whether the power domain transformation of the chip meets the design requirements of the chip, in this step, the signal level of the corresponding preset bit point when each power domain is transformed can be acquired according to a preset signal acquisition rule, so as to determine whether the power domain transformation meets the design requirements of the chip by using the signal level in the subsequent step. Optionally, the signal acquisition rule can stipulate which bit point signal level to collect when the power domain is transformed. The signal acquisition rule can be pre-written into a corresponding file for calling in chip verification.

[0061] S12, the signal level is compared according to a signal comparison rule corresponding to the signal level of the preset bit point;

[0062] After the signal levels of the preset sites are acquired, in this step, comparison operations can be performed on the signal levels of the corresponding sites according to the signal comparison rules corresponding to different sites. Optionally, the comparison operations can include mutual comparison between the acquired signal levels, or comparison between the acquired signal levels and other preset level values. Moreover, different preset sites can correspond to different signal comparison rules, and different comparison operations can be performed based on the different signal comparison rules. In an embodiment of the present application, the signal comparison rules can also be pre-written into corresponding files, so as to be called in chip verification.

[0063] In S13, whether the preset sites in the chip have circuit errors related to power domain transformation is determined according to the comparison results.

[0064] After the comparison operations on the signal levels of different preset sites in S12 are performed, corresponding comparison results can be obtained. In this step, whether the preset sites in the chip have circuit errors related to power domain transformation can be determined according to the comparison results. For example, in an embodiment of the present application, if the comparison result of the signal level corresponding to the preset site A and the preset level value is inconsistent, it can be determined that the preset site A has a circuit error related to power domain transformation.

[0065] The chip verification method provided by the embodiments of the present application can acquire the signal levels of the preset sites in the chip according to the preset signal acquisition rules in the dynamic simulation of the chip, and perform comparison operations on the signal levels according to the signal comparison rules corresponding to the preset sites. Since the chip includes multiple power domains, and the signal acquisition rules include the acquisition rules of the signals related to power domain transformation in the chip, the signal levels of the signals related to power domain transformation at the preset sites in the dynamic simulation of the chip can be acquired in time, and the comparison operations are performed on the signal levels according to the signal comparison rules corresponding to each preset site. Whether the preset sites have circuit errors related to power domain transformation is determined according to the comparison results. The whole process does not need technicians to perform complex simulation waveform analysis and problem finding on the circuit behavior, and therefore the chip verification efficiency can be improved, and the positioning of circuit errors is simplified.

[0066] Specifically, different functional areas in the chip can adopt different power domain conversion strategies at different time according to the running status of the circuit, and for each functional area, power domain conversion can cause signal level of some circuit sites to be impacted or fluctuated, which can affect the circuit function or stability. Therefore, the verification method of the chip provided by the embodiment of the present application can find out these circuit sites that can be affected by power domain conversion in chip verification, and specifically verify whether the signal level at each site is affected, whether it maintains its due level or whether it is set to a preset level.

[0067] In order to perform the above chip verification, in an embodiment of the present application, the acquisition rule of the signal related to the power domain conversion can be defined for the chip in advance, and the signal level of the corresponding site can be acquired according to the acquisition rule.

[0068] For example, in an embodiment of the present application, the acquisition rule of the signal related to the power domain conversion can include one or more of the following:

[0069] Optionally, in an embodiment, the acquisition rule of the signal related to the power domain conversion can include: when the power domain conversion causes at least one circuit module in the chip to perform power-on reset, acquiring the power-on signal and / or the reset signal of the corresponding site of each circuit module to form a corresponding first power-on sequence and / or a first reset sequence; for example, in an embodiment of the present application, the chip design requirement is that the power domain conversion of domain1 causes circuit module1, circuit module2 and circuit module3 to perform power-on reset in turn, and accordingly, the acquisition rule of the signal related to the power domain conversion can be, for example: when the power domain domain1 is converted, the power-on signal and / or the reset signal of circuit module1, circuit module2 and circuit module3 are acquired respectively, so as to perform the corresponding signal comparison operation in step S12.

[0070] Optionally, in an embodiment, the acquisition rule of the signal related to the power domain conversion can include: when the power domain conversion causes at least one circuit module in the chip to perform power-on reset, acquiring preset behavior information of the chip, the behavior information including at least one of the following: self-checking information of a read-only memory, clock establishment information, etc.; for example, in an embodiment of the present application, the design requirement of the chip is that the power domain conversion of domain2 causes circuit module4 to perform power-on reset, and accordingly, the acquisition rule of the signal related to the power domain conversion can be, for example: when the power domain domain2 is converted, acquiring the relevant behavior information of the chip power-on reset, such as the self-checking information of the read-only memory, the clock establishment information, etc., so as to perform the corresponding signal comparison operation in step S12.

[0071] Optionally, in an embodiment, the signal acquisition rule related to the power domain transition can comprise: when the power domain is transitioned, the signal levels of each cross-power-domain signal are acquired according to the signal list of the cross-power-domain signals in the chip; for example, in an embodiment, the design requirement of the chip is that when the power domain domain3 is transitioned, the corresponding signals signal1 and signal2 will be transmitted across the power domains, for example, the signals signal1 and signal2 are transmitted from the power domain domain3 to the power domain domain4, and the signal acquisition rule related to the power domain transition can be, for example, that when the power domain domain3 is transitioned, the signal levels of signal1 and signal2 in domain3 and the signal levels of signal1 and signal2 in domain4 are acquired, so as to perform the corresponding signal comparison operation in step S12.

[0072] Optionally, in an embodiment, the signal acquisition rule related to the power domain transition can comprise: when the power domain transition causes the power of at least one circuit module in the chip to be turned off, the clamp level maintained by the isolation cell corresponding to the cross-power-domain signal in the at least one circuit module is acquired; in the design of multiple power domains, the signal transmission of the power-off power domain can be blocked by inserting an isolation cell. In this way, when the power is turned off, the isolation cell will maintain the power-off signal at a specific value, which can be referred to as a clamp level, so as to prevent the signal from becoming an indeterminate value (i.e., the level is in an indeterminate state X) due to power-off and propagating the indeterminate value. In chip verification, in order to determine whether the clamp level is correctly set to the preset value, an embodiment of the present application can comprise, for example, that when the power domain domain4 is transitioned to cause the circuit module module5 to be powered off, the clamp level maintained by the isolation cell corresponding to the cross-power-domain signal signal3 in module5 is acquired.

[0073] Optionally, in an embodiment, the acquisition rule of the signal related to the power domain transition can include: when the power domain transition causes a reset of a cross-power-domain signal, acquiring a reset level of the cross-power-domain signal; when the power domain transition causes a power-off of the cross-power-domain signal, acquiring a clamping level maintained by an isolation cell corresponding to the cross-power-domain signal. In some cases, some circuits of the chip can be designed such that when the cross-power-domain signal is reset, the reset level of the cross-power-domain signal should be consistent with the clamping level maintained by the isolation cell corresponding to the cross-power-domain signal, and if the consistency is not maintained, it is considered as a circuit error. In an embodiment of the present application, in order to determine whether the consistency is correct, the acquisition rule of the signal related to the power domain transition can be, for example: when the power domain domain5 transition causes a power-off of the cross-power-domain signal signal4, acquiring the clamping level clamp4 maintained by the isolation cell corresponding to the cross-power-domain signal signal4; when the power domain domain5 transition causes a reset of the cross-power-domain signal signal4, acquiring the reset level signal4-reset of the cross-power-domain signal signal4.

[0074] Optionally, in an embodiment, the acquisition rule of the signal related to the power domain transition can include: when the power domain of at least one circuit module in the chip is switched, acquiring power domain switching information of the at least one circuit module to obtain a power domain switching sequence of the at least one circuit module. For example, if the circuit module module6 in the chip has four power domains that can be powered, the acquisition rule of the signal related to the power domain transition can be, for example: whenever the power domain of the circuit module module6 is switched, acquiring which power domain the circuit module module6 is switched from and which power domain the circuit module module6 is switched to, thereby obtaining the power domain switching sequence of the circuit module module6. For example, in an embodiment of the present application, the power domain switching sequence of the circuit module module6 is domain6-domain4-domain3-domain5, and the like.

[0075] Optionally, in one embodiment, the signal acquisition rule related to the power domain transition can include: when the power domain transition causes the power of at least one circuit module in the chip to be turned off, acquiring the temporary data in the register and / or memory cell in the at least one circuit module that performs a data retention operation; and when the at least one circuit module is powered on again, acquiring the signal level of the bit position corresponding to the register and / or memory cell. Specifically, the register and / or memory cell that performs the data retention operation can be referred to as a retention cell, which is a circuit cell that can maintain the internal state in the case of power off. For example, for a retention cell implemented by a register, the retention cell can be composed of a flip-flop. Normally, the flip-flop of the retention cell has the same function as a normal flip-flop, but the output data is latched. When the power is turned off, the latch can be powered by a backup power supply, so the latch can also maintain the original state. When the power is restored, the latch can output the latched data, thereby restoring the state at power off. In one embodiment of the present application, in order to verify whether the data retention function will be erroneous due to the power domain transition, the signal acquisition rule related to the power domain transition can be, for example: when the power domain transition causes the power of the circuit module module7 in the chip to be turned off, acquiring the temporary data in the register and / or memory cell in the circuit module module7 that performs a data retention operation; and when the circuit module module7 is powered on again, acquiring the signal level of the bit position corresponding to the register and / or memory cell, so as to perform a corresponding signal comparison operation in the subsequent step.

[0076] After the signal level of the preset bit position is acquired in step S11, the signal level can be compared according to the signal comparison rule corresponding to the signal level of the preset bit position in step S12. Due to the complexity of the circuit, the power domain transition can affect multiple signals, and each signal can have its own signal acquisition rule and signal comparison rule.

[0077] In order to verify the chip by using the signal acquisition rule and the signal comparison rule, before the signal level of the preset bit point in the chip is acquired according to the preset signal acquisition rule in step S11 in the dynamic simulation of the chip, the verification method of the chip provided by the embodiment of the application further comprises the following steps: recording the signal acquisition rule and the signal comparison rule through a script file; inputting the script file into a test platform (testbench) of the chip, so as to dynamically simulate the chip according to the test platform, the register transfer level circuit of the chip and a preset low-power design verification standard. Optionally, the signal acquisition rule and the signal comparison rule can be recorded in the same script file or in different script files. The preset low-power design verification standard can be, for example, the IEEE 1801 standard, namely, the UPF (Unified Power Format).

[0078] For example, a schematic diagram of file input and output relationship in chip verification can be as shown in Figure 2 As shown in Figure 2 In the embodiment of the application, the signal acquisition rule and the signal comparison rule can be input into the test platform, and the voltage excitation can be input into the test platform according to the power supply voltage and the power supply sequence of the circuit power supply network. Then, the low-power design verification standard file, the register transfer level circuit of the chip and the test platform are input into a verification environment simulation tool. The verification environment simulation tool can complete dynamic simulation of power management according to the verification scene of the test platform, output a static power network inspection report (for example, which can include a power network report, a power port report, a power supply range, a power consumption state report, a blocking unit report, a circuit error report related to power domain conversion and the like), and generate a low-power verification coverage report according to the test scene.

[0079] The following describes the corresponding signal comparison rule according to different signal acquisition rules. Optionally, in the embodiment of the application, the comparison operation on the signal level according to the signal comparison rule of the signal level corresponding to the preset bit point can comprise one or more of the following:

[0080] comparing whether the first power-on sequence is consistent with a preset second power-on sequence, and / or comparing whether the first reset sequence is consistent with a preset second reset sequence;

[0081] comparing whether the behavior information of the chip is consistent with preset reference information;

[0082] comparing the relationship between the signal level of each of the cross-power-domain signals and a preset level, so as to determine whether the signal level of each of the cross-power-domain signals is an indeterminate state level;

[0083] comparing whether the clamping level maintained by the blocking unit is consistent with a preset clamping level;

[0084] comparing whether the reset level when the cross-power-domain signal occurs reset is consistent with the clamping level when the cross-power-domain signal occurs power-off;

[0085] comparing whether the power domain switching sequence of the circuit module is consistent with a preset power domain switching sequence;

[0086] comparing whether the signal level corresponding to the temporary storage data is consistent with the signal level of the bit point corresponding to the register and / or the memory unit.

[0087] Specifically, in an embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is that, when the power domain transformation causes at least one circuit module in the chip to perform power-on reset, the power-on signal and / or the reset signal of the bit point corresponding to each of the circuit modules is acquired to form a corresponding first power-on sequence and / or a first reset sequence. Based on this, the signal comparison rule of the signal level corresponding to the preset bit point in step S12 can specifically include: comparing whether the first power-on sequence is consistent with a preset second power-on sequence, and / or comparing whether the first reset sequence is consistent with a preset second reset sequence. Optionally, the first power-on sequence can include the power-on voltage size and the power-on timing of the preset bit point, for example, the power-on voltage is 1.2V and the power-on timing is the 200 nanosecond of the simulation time, and the first reset sequence can include the reset level and the reset timing of the preset bit point, for example, the reset level is high level and the reset timing is the 350 nanosecond of the simulation time, etc. That is to say, in the embodiment, the acquired power-on sequence can be compared with the preset power-on sequence, the acquired reset sequence can be compared with the preset reset sequence, and whether they are consistent is verified.

[0088] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is that, when the power domain transformation causes at least one circuit module in the chip to perform power-on reset, preset behavior information of the chip is acquired, and the behavior information includes at least one of the following: self-detection information of the read-only memory, clock establishment information. Then, based on this, the signal comparison rule of the signal level corresponding to the preset bit point in step S12 can specifically include: comparing whether the behavior information of the chip is consistent with preset reference information. That is to say, in the embodiment, the acquired behavior information can be compared with the preset reference information, and whether they are consistent is verified.

[0089] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is: when the power domain transformation occurs, the signal levels of the cross-power-domain signals are acquired according to the signal list of the cross-power-domain signals in the chip; then, based on this, the signal comparison rule of the signal level corresponding to the preset bit point in step S12 can specifically include: comparing the signal level of each cross-power-domain signal with the preset level to determine whether the signal level of each cross-power-domain signal is an indeterminate state level. For example, if the signal level of a certain cross-power-domain signal is neither a high level, nor a low level, nor a high impedance state, then the signal level is an indeterminate state level.

[0090] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is: when the power domain transformation causes the power of at least one circuit module in the chip to be turned off, the clamping level maintained by the blocking unit corresponding to the cross-power-domain signal in the at least one circuit module is acquired; based on this, the signal comparison rule of the signal level corresponding to the preset bit point in step S12 can specifically include: comparing whether the clamping level maintained by the blocking unit is consistent with the preset clamping level. That is to say, in this embodiment, the acquired clamping level can be compared with the preset clamping level to verify whether they are consistent.

[0091] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is: when the power domain transformation causes the cross-power-domain signal to reset, the reset level of the cross-power-domain signal is acquired; when the power domain transformation causes the power of the cross-power-domain signal to be turned off, the clamping level maintained by the blocking unit corresponding to the cross-power-domain signal is acquired; based on this, the signal comparison rule of the signal level corresponding to the preset bit point in step S12 can specifically include: comparing whether the reset level when the cross-power-domain signal resets is consistent with the clamping level when the power of the cross-power-domain signal is turned off. That is to say, in this embodiment, the two different levels acquired are compared with each other to verify whether they are consistent.

[0092] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is: when the power domain of at least one circuit module in the chip is switched, the power domain switching information of the at least one circuit module is acquired to obtain the power domain switching sequence of the at least one circuit module. Based on this, the signal comparison rule according to the signal level of the preset bit point in step S12 can specifically include: comparing whether the power domain switching sequence of the circuit module is consistent with the preset power domain switching sequence. That is, in the present embodiment, the acquired power domain switching sequence can be compared with the preset power domain switching sequence to verify whether they are consistent.

[0093] Optionally, in another embodiment, the acquisition rule of the signal related to the power domain transformation in step S11 is: when the power domain transformation causes the power of at least one circuit module in the chip to be turned off, the temporary data in the register and / or memory unit performing the data retention operation in the at least one circuit module is acquired, and when the at least one circuit module is powered on again, the signal level of the bit point corresponding to the register and / or the memory unit is acquired. Based on this, the signal comparison rule according to the signal level of the preset bit point in step S12 can specifically include: comparing whether the signal level corresponding to the temporary data is consistent with the signal level of the bit point corresponding to the register and / or the memory unit. It can be understood that the temporary data in the register and / or the memory unit can be stored in the form of digital signals "0" or "1", and the digital signals "0" and "1" also represent different signal levels in the circuit. For example, in a positive logic circuit, "1" represents a high level and "0" represents a low level. When comparing, for example, in an embodiment of the present application, when the power is turned off, the temporary data in the register and / or the memory unit is 0110, and the corresponding signal level is low-high-high-low. When the power is restored, if the signal level of the bit point corresponding to the register and / or the memory unit is also low-high-high-low, the verification result is that they are consistent, otherwise, the verification result is that they are inconsistent. That is, in the present embodiment, the signal level corresponding to the temporary data acquired from the register and / or the memory unit when the power is turned off is compared with the signal level on the corresponding bit point when the power is restored to verify whether they are consistent.

[0094] After the comparison operation on the signal levels according to the signal comparison rule corresponding to the signal levels of the preset sites, it can be determined in step S13 whether the preset sites in the chip have the circuit error related to the power domain transformation according to the comparison result. Specifically, whether the preset sites in the chip have the circuit error related to the power domain transformation can be determined according to whether the comparison results are consistent. For example, in the above various comparison operations, if the corresponding comparison result is that the comparison results are consistent, it can be determined that the signal levels of the preset sites in the chip meet the design requirements of the circuit, and thus there is no circuit error related to the power domain transformation. If the corresponding comparison result is that the comparison results are inconsistent, it can be determined that the signal levels of the preset sites in the chip do not meet the design requirements of the circuit, and thus there is a circuit error related to the power domain transformation.

[0095] Further, in order to enable the technician to master the chip verification result as soon as possible, to know what kind of error or problem exists in the chip, and where the error or problem occurs, in an embodiment of the present application, after the step S13 of determining whether the preset sites in the chip have the circuit error related to the power domain transformation according to the comparison result, the verification method of the chip provided by the embodiment of the present application can further include: outputting the related information of the sites having the circuit error in the verification report, wherein the related information can include one or more of the following: site position, error type, error cause, etc. The site position can include the position distribution of the site having the circuit error in the circuit, which can be shown by the identification of the circuit module, the port identification, etc. The error type can refer to what type of circuit error occurs, for example, the error types can be classified according to the acquisition conditions and / or acquisition time of each signal in the signal acquisition rule, for example, the power-on sequence error is error type I, the data retention error is error type II, etc., and the specific error type is shown in the verification report. The error cause can refer to giving a corresponding prompt to the cause or source of the error.

[0096] In a second aspect, the embodiment of the present application further provides a chip verification device, which can effectively improve the chip verification efficiency and simplify the positioning of the circuit error.

[0097] As shown in Figure 3 The chip verification device provided by the embodiment of the present application can include:

[0098] The acquisition unit 31 is configured to acquire, in the dynamic simulation of the chip, the signal levels of the preset sites in the chip according to a preset signal acquisition rule, wherein the chip includes a plurality of power domains, and the signal acquisition rule includes an acquisition rule of a signal related to the power domain transformation in the chip.

[0099] The comparison unit 32 is configured to compare the signal levels according to a signal comparison rule corresponding to the signal level of the preset site;

[0100] The determination unit 33 is configured to determine whether the preset site in the chip has a circuit error related to the power domain transformation according to the comparison result.

[0101] The verification device for the chip provided by the embodiment of the present application can obtain the signal level of the preset site in the chip according to a preset signal acquisition rule in the dynamic simulation of the chip, compare the signal level according to a signal comparison rule corresponding to the signal level of the preset site, and determine whether the preset site has a circuit error related to the power domain transformation according to the comparison result. Since the chip includes multiple power domains and the signal acquisition rule includes the acquisition rule of the signal related to the power domain transformation in the chip, the signal level of the signal related to the power domain transformation at the preset site in the dynamic simulation of the chip can be obtained in time, and the signal level is compared according to the signal comparison rule corresponding to each preset site, so that whether the preset site has a circuit error related to the power domain transformation is determined according to the comparison result. The whole process does not require the technical personnel to perform complex simulation waveform analysis and problem finding on the circuit behavior, and therefore the chip verification efficiency can be improved and the positioning of the circuit error is simplified.

[0102] In an embodiment, the acquisition rule of the signal related to the power domain transformation includes at least one of the following:

[0103] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, the power-on signal and / or the reset signal of the corresponding site of each circuit module is acquired to form a corresponding first power-on sequence and / or a first reset sequence;

[0104] When the power domain transformation causes at least one circuit module in the chip to perform power-on reset, preset behavior information of the chip is acquired, and the behavior information includes at least one of the following: self-detection information of a read-only memory, clock establishment information;

[0105] When the power domain transformation occurs, the signal level of each cross-power-domain signal is acquired according to a signal list of the cross-power-domain signal in the chip;

[0106] When the power domain transformation causes the power of at least one circuit module in the chip to be turned off, the clamping level maintained by a blocking unit corresponding to the cross-power-domain signal in the at least one circuit module is acquired;

[0107] When the power domain transformation causes the cross-power-domain signal to be reset, the reset level of the cross-power-domain signal is acquired, and when the power domain transformation causes the power of the cross-power-domain signal to be turned off, the clamping level maintained by a blocking unit corresponding to the cross-power-domain signal is acquired;

[0108] obtaining power domain switching information of at least one circuit module in the chip when a power domain of the at least one circuit module switches, and obtaining a power domain switching sequence of the at least one circuit module;

[0109] obtaining temporarily stored data in a register and / or a memory unit of the at least one circuit module performing a data retention operation when a power domain transition causes power-off of the at least one circuit module in the chip, and obtaining a signal level of a bit corresponding to the register and / or the memory unit when the at least one circuit module is powered on again.

[0110] In an embodiment, the comparison unit 32 can be configured to perform at least one of the following:

[0111] comparing whether the first power-on sequence is consistent with a preset second power-on sequence, and / or comparing whether the first reset sequence is consistent with a preset second reset sequence;

[0112] comparing whether the behavior information of the chip is consistent with preset reference information;

[0113] comparing a relationship between a signal level of each of the cross-power-domain signals and a preset level to determine whether the signal level of each of the cross-power-domain signals is an indeterminate state level;

[0114] comparing whether the clamping level maintained by the blocking unit is consistent with a preset clamping level;

[0115] comparing whether a reset level when the cross-power-domain signal occurs reset is consistent with a clamping level when the cross-power-domain signal occurs power-off;

[0116] comparing whether the power domain switching sequence of the circuit module is consistent with a preset power domain switching sequence;

[0117] comparing whether a signal level corresponding to the temporarily stored data is consistent with a signal level of a bit corresponding to the register and / or the memory unit.

[0118] In an embodiment, the first power-on sequence includes a power-on voltage size and a power-on timing of the preset bit, and the first reset sequence includes a reset level and a reset timing of the preset bit.

[0119] In an embodiment, the apparatus can further include:

[0120] The output unit is configured to output, in the verification report, relevant information of the site with the circuit error after determining, according to the comparison result, whether the preset site in the chip has the circuit error related to the power domain transformation, wherein the relevant information comprises at least one of the following: site position, error type, and error cause.

[0121] In an implementation, the apparatus can further comprise:

[0122] The recording unit is configured to record, before obtaining the signal level of the preset site in the chip according to the preset signal acquisition rule in the dynamic simulation of the chip, the signal acquisition rule and the signal comparison rule through the script file.

[0123] The input unit is configured to input the script file into a test platform of the chip, so as to perform dynamic simulation on the chip according to the test platform, a register transfer level circuit of the chip, and a preset low-power design verification standard.

[0124] In a third aspect, embodiments of the present application further provide an electronic device, which can effectively improve chip verification efficiency and simplify positioning of circuit errors.

[0125] As shown in Figure 4 The electronic device provided by the embodiments of the present application can comprise a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is arranged inside a space enclosed by the housing 51, the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is configured to supply power to each circuit or device of the electronic device; the memory 53 is configured to store executable program codes; and the processor 52 is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory 53, and execute the chip verification method provided by any of the foregoing embodiments.

[0126] The specific execution process of the processor 52 on the foregoing steps and the steps further executed by the processor 52 by running the executable program codes can refer to the description of the foregoing embodiments, and will not be described here again.

[0127] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip verification method provided by any of the foregoing embodiments, thus achieving the corresponding technical effects. The foregoing has been described in detail, and will not be described here again.

[0128] It is to be noted that the terms such as first and second, etc., are used herein merely to differentiate one entity or action from another, and do not necessarily require or imply any such actual relationship or order between such entities or actions. Also, the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0129] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments.

[0130] Especially, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0131] For the convenience of description, the above device is described in various units / modules respectively according to functions. Of course, in the implementation of the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0132] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), etc.

[0133] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip verification method, characterized in that, include: In the dynamic simulation of the chip, the signal level of a preset point in the chip is obtained according to the preset signal acquisition rules. The chip includes multiple power domains, and the signal acquisition rules include the acquisition rules of signals related to power domain transformation in the chip. The signal levels are compared according to the signal comparison rules corresponding to the signal levels of the preset locations. Based on the comparison results, determine whether there are any circuit errors related to power domain transformation at the preset sites in the chip; The acquisition rules for the signals related to power domain transformation include at least one of the following: When a power domain transformation causes at least one circuit module in the chip to undergo a power-on reset, the power-on signal and / or reset signal of the corresponding point of each circuit module are acquired to form a corresponding first power-on sequence and / or first reset sequence. When a power domain change causes at least one circuit module in the chip to undergo a power-on reset, preset behavior information of the chip is obtained. The behavior information includes at least one of the following: self-test information of the read-only memory and clock setup information. When the power domain changes, the signal level of each cross-power domain signal is obtained according to the signal list of cross-power domain signals in the chip. When a power domain transition causes the power to be turned off in at least one circuit module in the chip, the clamping level maintained by the isolation unit corresponding to the cross-power domain signal in the at least one circuit module is obtained. When a power domain transition causes a cross-power domain signal to be reset, the reset level of the cross-power domain signal is obtained. When a power domain transition causes the cross-power domain signal to be powered off, the clamping level held by the isolation unit corresponding to the cross-power domain signal is obtained. When the power domain of at least one circuit module in the chip is switched, the power domain switching information of the at least one circuit module is obtained, and the power domain switching sequence of the at least one circuit module is obtained. When a power domain transition causes the power to be turned off at least one circuit module in the chip, temporary data in the registers and / or memory units that perform data retention operations in the at least one circuit module is acquired. When the at least one circuit module is powered on again, the signal level of the point corresponding to the register and / or the memory unit is acquired.

2. The method according to claim 1, characterized in that, The signal level comparison operation based on the signal level comparison rule corresponding to the preset position includes at least one of the following: Compare whether the first power-on sequence is consistent with the preset second power-on sequence, and / or compare whether the first reset sequence is consistent with the preset second reset sequence; Compare whether the behavior information of the chip is consistent with the preset reference information; Compare the signal level of each cross-power domain signal with a preset level to determine whether the signal level of each cross-power domain signal is an undefined level. Compare whether the clamping level maintained by the isolation unit is consistent with the preset clamping level; Compare whether the reset level when the cross-power domain signal is reset is consistent with the clamping level when the cross-power domain signal is powered off. Compare whether the power domain switching sequence of the circuit module is consistent with the preset power domain switching sequence; Compare whether the signal level corresponding to the temporary data is consistent with the signal level of the corresponding point in the register and / or the memory unit.

3. The method according to claim 1, characterized in that, The first power-on sequence includes the power-on voltage magnitude and power-on timing of the preset point; the first reset sequence includes the reset level and reset timing of the preset point.

4. The method according to claim 1, characterized in that, After determining whether a circuit error related to power domain transformation exists at the preset location in the chip based on the comparison result, the method further includes: The relevant information of the location where the circuit error exists will be output in the verification report, wherein the relevant information includes at least one of the following: location of the location, error type, and error cause.

5. The method according to any one of claims 1 to 4, characterized in that, Before acquiring the signal level of a preset location in the chip according to a preset signal acquisition rule during the dynamic simulation of the chip, the method further includes: The signal acquisition rules and the signal comparison rules are recorded in a script file; The script file is input into the chip's test platform to perform dynamic simulation of the chip based on the test platform, the chip's register transfer stage circuit, and preset low-power design verification standards.

6. A chip verification device, characterized in that, include: The acquisition unit is used to acquire the signal level of a preset point in the chip according to a preset signal acquisition rule during the dynamic simulation of the chip. The chip includes multiple power domains, and the signal acquisition rule includes the acquisition rule of the signal related to the power domain transformation in the chip. The comparison unit is used to perform a comparison operation on the signal level according to the signal comparison rules corresponding to the signal level of the preset position; The determining unit is used to determine, based on the comparison result, whether there is a circuit error related to power domain transformation at the preset position in the chip; The acquisition rules for the signals related to power domain transformation include at least one of the following: When a power domain transformation causes at least one circuit module in the chip to undergo a power-on reset, the power-on signal and / or reset signal of the corresponding point of each circuit module are acquired to form a corresponding first power-on sequence and / or first reset sequence. When a power domain change causes at least one circuit module in the chip to undergo a power-on reset, preset behavior information of the chip is obtained. The behavior information includes at least one of the following: self-test information of the read-only memory and clock setup information. When the power domain changes, the signal level of each cross-power domain signal is obtained according to the signal list of cross-power domain signals in the chip. When a power domain transition causes the power to be turned off in at least one circuit module in the chip, the clamping level maintained by the isolation unit corresponding to the cross-power domain signal in the at least one circuit module is obtained. When a power domain transition causes a cross-power domain signal to be reset, the reset level of the cross-power domain signal is obtained. When a power domain transition causes the cross-power domain signal to be powered off, the clamping level held by the isolation unit corresponding to the cross-power domain signal is obtained. When the power domain of at least one circuit module in the chip is switched, the power domain switching information of the at least one circuit module is obtained, and the power domain switching sequence of the at least one circuit module is obtained. When a power domain transition causes the power to be turned off at least one circuit module in the chip, temporary data in the registers and / or memory units that perform data retention operations in the at least one circuit module is acquired. When the at least one circuit module is powered on again, the signal level of the point corresponding to the register and / or the memory unit is acquired.

7. The apparatus according to claim 6, characterized in that, The comparison unit is specifically used for at least one of the following: Compare whether the first power-on sequence is consistent with the preset second power-on sequence, and / or compare whether the first reset sequence is consistent with the preset second reset sequence; Compare whether the behavior information of the chip is consistent with the preset reference information; Compare the signal level of each cross-power domain signal with a preset level to determine whether the signal level of each cross-power domain signal is an undefined level. Compare whether the clamping level maintained by the isolation unit is consistent with the preset clamping level; Compare whether the reset level when the cross-power domain signal is reset is consistent with the clamping level when the cross-power domain signal is powered off. Compare whether the power domain switching sequence of the circuit module is consistent with the preset power domain switching sequence; Compare whether the signal level corresponding to the temporary data is consistent with the signal level of the corresponding point in the register and / or the memory unit.

8. The apparatus according to claim 6, characterized in that, The first power-on sequence includes the power-on voltage magnitude and power-on timing of the preset point; the first reset sequence includes the reset level and reset timing of the preset point.

9. The apparatus according to claim 6, characterized in that, Also includes: The output unit is used to output relevant information about the sites with circuit errors in the verification report after determining whether there are circuit errors related to power domain transformation at the preset sites in the chip based on the comparison results. The relevant information includes at least one of the following: site location, error type, and error cause.

10. The apparatus according to any one of claims 6 to 9, characterized in that, Also includes: The recording unit is used to record the signal acquisition rules and the signal comparison rules in a script file before acquiring the signal level of a preset point in the chip according to the preset signal acquisition rules during the dynamic simulation of the chip. The input unit is used to input the script file into the chip's test platform to perform dynamic simulation of the chip based on the test platform, the chip's register transfer stage circuit, and preset low-power design verification standards.

11. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip verification method of any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip verification method according to any one of claims 1 to 5.

Images