Readout circuit structure

Abstract

An embodiment of the present application provides a readout circuit structure, disposed in a gap of a memory array, comprising: a structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; a first sensing amplifier structure, a second sensing amplifier structure, and an equalization structure disposed in the structural layer; wherein one of a first bit line or a first complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; wherein one of a second bit line or a second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; and wherein the equalization structure directly connects the first complementary bit line and the second bit line; wherein the equalization structure is disposed between the first sensing amplifier structure and the second sensing amplifier structure and directly connected to the first complementary bit line and the second bit line in the first interconnect layer, thereby solving the problem of slow precharging speed and reducing the layout area of ​​the readout circuit structure.

Description

Technical Field

[0001] The present application relates to the field of memory layout design, and in particular to a readout circuit structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] DRAM can be categorized as Double Data Rate (DDR), Graphics Double Data Rate (GDDR), and Low Power Double Data Rate (LPDDR). As DRAM is increasingly used in a wide range of fields, such as the mobile sector, users are increasingly demanding higher power consumption metrics.

[0004] However, current DRAM performance still needs to be improved. Summary of the Invention

[0005] An embodiment of the present application provides a readout circuit structure, which solves the problem of slow pre-charging speed of the memory and provides a layout structure and wiring method to reduce the layout area of ​​the readout circuit structure.

[0006] To solve the above technical problems, an embodiment of the present application provides a readout circuit structure, which is arranged in the gap of the memory array, including: a structural layer, a first interconnection layer and a second interconnection layer stacked on top of the structural layer; a first sensing amplifier structure, a second sensing amplifier structure and a balance structure are arranged in the structural layer; the first sensing amplifier structure is connected to one memory array in the adjacent memory array through a first bit line, the first sensing amplifier structure is connected to another memory array in the adjacent memory array through a first complementary bit line, the second sensing amplifier structure is connected to one memory array in the adjacent memory array through a second bit line, and the second sensing amplifier structure is connected to the other memory array in the adjacent memory array through a second complementary bit line. A memory array; wherein one of the first bit line or the first complementary bit line is arranged in a first interconnect layer, and at least a portion of the other is arranged in a second interconnect layer; wherein one of the second bit line or the second complementary bit line is arranged in the first interconnect layer, and at least a portion of the other is arranged in the second interconnect layer; an equalization structure directly connects the first complementary bit line and the second bit line, and is used to precharge the first bit line, the first complementary bit line, the first sensing amplifier structure, the second bit line, the second complementary bit line, and the second sensing amplifier structure; wherein the equalization structure is arranged between the first sensing amplifier structure and the second sensing amplifier structure, and is directly connected to the first complementary bit line and the second bit line in the first interconnect layer.

[0007] Compared with the related art, the equalization structure is directly connected to the first bit line or the first complementary bit line for precharging the first bit line and the first complementary bit line, and the equalization structure is directly connected to the second bit line or the second complementary bit line for precharging the second bit line and the second complementary bit line. By directly connecting the bit lines through the equalization structure and directly precharging the bit lines, it is avoided that the precharging process requires the switching transistor to be turned on to precharge the bit lines, thereby speeding up the charging speed of the bit lines; further, at least a portion of one of the first bit line or the first complementary bit line is arranged in the second interconnection layer, and the other is arranged in the first interconnection layer; at least a portion of one of the second bit line or the second complementary bit line is arranged in the second interconnection layer, and the other is arranged in the first interconnection layer. By stacking the first and second interconnection layers, the structure required to be laid out in each layer of the layout is reduced, thereby reducing the layout area of ​​the readout circuit structure.

[0008] In addition, a first bit line is disposed in a first interconnect layer, and at least a portion of a first complementary bit line is disposed in a second interconnect layer. The first complementary bit line passes through a region where the second sensing amplifier structure is located in the second interconnect layer and is coupled to the first sensing amplifier structure. At least a portion of a second bit line is disposed in the second interconnect layer, and the second bit line passes through a region where the first sensing amplifier structure is located in the first interconnect layer and is coupled to the second sensing amplifier structure. The second complementary bit line is disposed in the first interconnect layer. The first complementary bit line passes through a region where the second sensing amplifier structure is located and is coupled to the first sensing amplifier structure. This means that the first complementary bit line does not require additional layout area for routing, thereby reducing the layout area of ​​the readout circuit structure. The second bit line passes through a region where the first sensing amplifier structure is located and is coupled to the second sensing amplifier structure. This means that the second bit line does not require additional layout area for routing, thereby reducing the layout area of ​​the readout circuit structure.

[0009] In addition, the balancing structure includes: a first balancing transistor, having a gate for receiving a first balancing signal, one of a source or a drain connected to a first complementary bit line, and the other for receiving a first precharge voltage, for precharging the first bit line, the first complementary bit line, and the first sensing amplifier structure to the first precharge voltage based on the first balancing signal; and a second balancing transistor, having a gate for receiving a second balancing signal, one of a source or a drain connected to a second bit line, and the other for receiving a second precharge voltage, for precharging the second bit line, the second complementary bit line, and the second sensing amplifier structure to the second precharge voltage based on the second balancing signal.

[0010] In addition, the first equalization signal and the second equalization signal are the same equalization signal, and the first precharge voltage and the second precharge voltage are the same precharge voltage.

[0011] In addition, the drain of the first balancing tube is connected to the drain of the second balancing tube for receiving the same pre-charging voltage.

[0012] In addition, a third sensing amplifier structure and a fourth sensing amplifier structure are also provided in the structural layer; the third sensing amplifier structure is connected to one of the adjacent memory arrays via a third bit line, the third sensing amplifier structure is connected to the other of the adjacent memory arrays via a third complementary bit line, the fourth sensing amplifier structure is connected to one of the adjacent memory arrays via a fourth bit line, and the fourth sensing amplifier structure is connected to the other of the adjacent memory arrays via a fourth complementary bit line; wherein one of the third bit line or the third complementary bit line is provided in the first interconnect layer, and the other is at least partially provided in the second interconnect layer; wherein one of the fourth bit line or the fourth complementary bit line is provided in the first interconnect layer, and the other is at least partially provided in the second interconnect layer; an equalization structure is directly connected to the third complementary bit line and the fourth bit line, and is used to precharge the third bit line, the third complementary bit line, the third sensing amplifier structure, the fourth bit line, the fourth complementary bit line, and the fourth sensing amplifier structure; wherein the equalization structure is directly connected to the third complementary bit line and the fourth bit line in the first interconnect layer.

[0013] In addition, the equalization structure further includes: a third equalization transistor, disposed on a side of the first equalization transistor in the word line extending direction, sharing a common gate with the first equalization transistor, having one of its source or drain connected to the third complementary bit line, and the other for receiving a first precharge voltage, for precharging the third bit line, the third complementary bit line, and the third sensing amplifier structure to the first precharge voltage based on the first equalization signal; and a fourth equalization transistor, disposed on a side of the second equalization transistor in the word line extending direction, sharing a common gate with the second equalization transistor, having one of its source or drain connected to the fourth bit line, and the other for receiving a second precharge voltage, for precharging the fourth bit line, the fourth complementary bit line, and the fourth sensing amplifier structure to the second precharge voltage based on the second equalization signal.

[0014] In addition, a first data readout module and a second data readout module are also provided in the structural layer; the first data readout module includes: a first input / output tube, a third input / output tube, a fifth input / output tube and a seventh input / output tube; the source of the first input / output tube is connected to the first input / output line, and the drain is connected to the first bit line, the source of the third input / output tube is connected to the third input / output line, and the drain is connected to the second bit line, the source of the fifth input / output tube is connected to the fifth input / output line, and the drain is connected to the third bit line, the source of the seventh input / output tube is connected to the seventh input / output line, and the drain is connected to the fourth bit line; the first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; the gates of the first input / output tube, the gates of the third input / output tube, the gates of the fifth input / output tube and the gates of the seventh input / output tube are connected together to receive a column selection signal and turn on the first input / output tube, the third input / output tube, the fifth input / output tube and the seventh input / output tube based on the column selection signal. Seven input / output tubes; the second data readout module includes a second input / output tube, a fourth input / output tube, a sixth input / output tube, and an eighth input / output tube; the source of the second input / output tube is connected to the second input / output line, and the drain is connected to the first complementary bit line; the source of the fourth input / output tube is connected to the fourth input / output line, and the drain is connected to the second complementary bit line; the source of the sixth input / output tube is connected to the sixth input / output line, and the drain is connected to the third complementary bit line; the source of the eighth input / output tube is connected to the eighth input / output line, and the drain is connected to the fourth complementary bit line; the first complementary bit line, the second complementary bit line, the third complementary bit line, and the fourth complementary bit line are four adjacent bit lines in the same memory array; the gates of the second input / output tube, the gates of the fourth input / output tube, the gates of the sixth input / output tube, and the gates of the eighth input / output tube are connected together, and are used to receive a column select signal and turn on the second input / output tube, the fourth input / output tube, the sixth input / output tube, and the eighth input / output tube based on the column select signal.

[0015] In addition, the first sensing amplifier structure includes: a sensing amplifier module, connected to the first bit line via a sense bit line and connected to the first complementary bit line via a complementary sense bit line, for sensing the voltage of a memory cell in the memory array and outputting a logic 1 or 0 corresponding to the voltage; an isolation module, connected between the complementary sense bit line and the first complementary bit line, and between the sense bit line and the first bit line, for isolating the signal interaction between the first bit line, the first complementary bit line and the sense bit line, and between the complementary sense bit line according to an isolation signal; and an offset cancellation module, connected between the sense bit line and the first complementary bit line, and between the complementary sense bit line and the first bit line, for adjusting the source-drain conduction difference between NMOS transistors or between PMOS transistors in the sensing amplifier module according to the offset cancellation signal.

[0016] In addition, the sensing amplifier module includes: a first sensing amplifier N-type transistor, having a gate connected to the first bit line, a drain connected to the complementary read bit line, and a source connected to the second signal terminal. When the sensing amplifier module is in the amplification stage, the second signal terminal is electrically connected to a voltage corresponding to a logic 0; a second sensing amplifier N-type transistor, having a gate connected to the first complementary bit line, a drain connected to the read bit line, and a source connected to the second signal terminal; a first sensing amplifier P-type transistor, having a gate connected to the read bit line, a drain connected to the complementary read bit line, and a source connected to the first signal terminal. When the sensing amplifier module is in the amplification stage, the first signal terminal is electrically connected to a voltage corresponding to a logic 1; and a second sensing amplifier P-type transistor, having a gate connected to the complementary read bit line, a drain connected to the read bit line, and a source connected to the first signal terminal.

[0017] In addition, the gate structure of the first sensing amplifier N-type transistor, the gate structure of the second sensing amplifier N-type transistor, the gate structure of the first sensing amplifier P-type transistor, and the gate structure of the second sensing amplifier P-type transistor extend in the same direction. The gate structure of the MOS transistor in the isolation module and the gate structure of the MOS transistor in the offset cancellation module extend in the same direction, and the gate structure of the first sensing amplifier N-type transistor and the gate structure of the MOS transistor in the isolation module extend in directions perpendicular to each other.

[0018] In addition, the first sensing amplifier P transistor, the second sensing amplifier P transistor, the isolation module and the offset elimination module are arranged between the first sensing amplifier N transistor and the second sensing amplifier N transistor.

[0019] In addition, the isolation module includes: a first isolation transistor, whose gate is used to receive the isolation signal, whose source is connected to the first bit line, and whose drain is connected to the readout bit line; a second isolation transistor, whose gate is used to receive the isolation signal, whose source is connected to the first complementary bit line, and whose drain is connected to the complementary readout bit line.

[0020] In addition, the offset cancellation module includes: a first offset cancellation tube, whose gate is used to receive the offset cancellation signal, whose source is connected to the first bit line, and whose drain is connected to the complementary readout bit line; a second offset cancellation tube, whose gate is used to receive the offset cancellation signal, whose source is connected to the first complementary bit line, and whose drain is connected to the readout bit line.

[0021] In addition, the source of the first isolation transistor is connected to the source of the first offset cancellation transistor and connected to the first bit line; the source of the second isolation transistor is connected to the source of the second offset cancellation transistor and connected to the first complementary bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 and Figure 2 A circuit diagram of a readout circuit structure provided in an embodiment of the present application;

[0023] Figure 3 and Figure 4 A layout of the readout circuit structure provided in an embodiment of the present application;

[0024] Figure 5 A layout of a balanced structure provided in an embodiment of the present application;

[0025] Figure 6 This is a structural layer layout of another balanced structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] As can be seen from the background technology, the performance of DRAM in the prior art still needs to be improved.

[0027] The applicant has discovered that existing sense amplifiers with offset compensation function include the conduction process of the switching transistor during the pre-charging process of the bit line and the complementary bit line, resulting in the charging speed of the bit line and the complementary bit line being insufficient. As the size of the transistor is further reduced, the saturation current of the switching transistor decreases, and this situation becomes more serious, which is not conducive to improving the read and write performance of the memory.

[0028] To solve the above technical problems, an embodiment of the present application provides a readout circuit structure, which is arranged in the gap of the memory array, including: a structural layer, a first interconnection layer and a second interconnection layer stacked on top of the structural layer; a first sensing amplifier structure, a second sensing amplifier structure and a balance structure are arranged in the structural layer; the first sensing amplifier structure is connected to one memory array in the adjacent memory array through a first bit line, the first sensing amplifier structure is connected to another memory array in the adjacent memory array through a first complementary bit line, the second sensing amplifier structure is connected to one memory array in the adjacent memory array through a second bit line, and the second sensing amplifier structure is connected to the other memory array in the adjacent memory array through a second complementary bit line. A memory array; wherein one of the first bit line or the first complementary bit line is arranged in a first interconnect layer, and at least a portion of the other is arranged in a second interconnect layer; wherein one of the second bit line or the second complementary bit line is arranged in the first interconnect layer, and at least a portion of the other is arranged in the second interconnect layer; an equalization structure directly connects the first complementary bit line and the second bit line, and is used to precharge the first bit line, the first complementary bit line, the first sensing amplifier structure, the second bit line, the second complementary bit line, and the second sensing amplifier structure; wherein the equalization structure is arranged between the first sensing amplifier structure and the second sensing amplifier structure, and is directly connected to the first complementary bit line and the second bit line in the first interconnect layer.

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0030] Figure 1 and Figure 2 A circuit diagram of the readout circuit structure provided in this embodiment, Figure 3 and Figure 4 Layout of the readout circuit structure provided for this embodiment Figure 5 A layout of a balanced structure provided in this embodiment, Figure 6 This is a structural layer layout diagram of another equalization structure provided by this embodiment. The readout circuit structure provided by this embodiment is further described in detail below with reference to the accompanying drawings:

[0031] It should be noted that since the circuit diagram and layout of the readout circuit structure are relatively large, in order to clearly reflect the readout circuit structure to be protected by this embodiment, the circuit diagram and layout are split when drawing, that is, Figure 1 and Figure 2 The circuit diagram of the readout circuit structure provided in this embodiment is combined in the following manner: Figure 1 The bottom and Figure 2 The top merge of Figure 3 and Figure 4 The layout of the readout circuit structure provided in this embodiment is combined in the following manner: Figure 3 The bottom and Figure 4 The top of the merge.

[0032] refer to Figures 1 to 4 , a readout circuit structure, arranged in a gap between adjacent memory arrays, comprising:

[0033] The memory array 101 has n rows and m columns of memory cells. Each memory cell is used to store 1 bit of data. That is, a memory array 101 can store n×m bits of data. During data reading, data stored in the memory cell is read out or data is written into the memory cell by selecting a specific memory cell.

[0034] The structural layer, the first interconnection layer and the second interconnection layer stacked on top of the structural layer, specifically, Figure 3 and Figure 4The structural layer is the layout on the right side of the figure, the first interconnection layer is the layout in the middle part of the figure, and the second interconnection layer is the layout on the left side of the figure.

[0035] Among them, the structural layer is used to form a specific device structure in the readout circuit structure. In this embodiment, the structural layer is provided with a first sensing amplifier structure, a second sensing amplifier structure, a first equalization structure, and a second equalization structure; the first interconnection layer is used to set the internal electrical connection of the sensing amplifier structure and connect the bit line or complementary bit line of the closer one between adjacent storage arrays; the second interconnection layer is used for the sensing amplifier structure to connect the bit line or complementary bit line of the farther one between adjacent storage arrays.

[0036] refer to Figure 1 and Figure 2 and combined Figure 3 and Figure 4 It can be seen that in the direction of bit line extension, the first sensing amplifier structure and the second sensing amplifier structure are arranged adjacent to each other, and are used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage; wherein the first sensing amplifier structure is connected to one memory array of the adjacent memory array through the first bit line BL1, the first sensing amplifier structure is connected to the other memory array of the adjacent memory array through the first complementary bit line BLB1, the second sensing amplifier structure is connected to one memory array of the adjacent memory array through the second bit line BL2, and the second sensing amplifier structure is connected to the other memory array of the adjacent memory array through the second complementary bit line BLB2.

[0037] For the first bit line BL1, the second bit line BL2, the first complementary bit line BLB1 and the second complementary bit line BLB2, one of the first bit line BL1 or the first complementary bit line BLB1 is set in the first interconnection layer, and at least part of the other is set in the second interconnection layer; one of the second bit line BL2 or the second complementary bit line BLB2 is set in the first interconnection layer, and at least part of the other is set in the second interconnection layer.

[0038] Specifically, in this embodiment, the first bit line BL1 is arranged in the first interconnection layer, at least a portion of the first complementary bit line BLB1 is arranged in the second interconnection layer, the first complementary bit line BLB1 passes through the area where the second sensing amplification structure is located in the second interconnection layer and is coupled to the first sensing amplification structure, the second bit line BL2 is at least partially arranged in the second interconnection layer, the second bit line BL2 passes through the area where the first sensing amplification structure is located in the second interconnection layer and is coupled to the second sensing amplification structure, and the second complementary bit line BLB2 is arranged in the first interconnection layer.

[0039] The first complementary bit line BLB1 passes through the area where the second sensing amplifier structure is located and is coupled to the first sensing amplifier structure. That is, the first complementary bit line BLB1 does not need to occupy additional layout area to complete wiring, thereby reducing the layout area of ​​the readout circuit structure. The second bit line BL2 passes through the area where the first sensing amplifier structure is located and is coupled to the second sensing amplifier structure. That is, the second bit line BL2 does not need to occupy additional layout area to complete wiring, thereby reducing the layout area of ​​the readout circuit structure.

[0040] The equalization structure is directly connected to the first complementary bit line BLB1 and the second bit line BL2 for precharging the first bit line BL1, the first complementary bit line BLB1, the first sensing amplifier structure, the second bit line BL2, the second complementary bit line BLB2 and the second sensing amplifier structure.

[0041] In this embodiment, the equalizer structure is disposed between the first sense amplifier structure and the second sense amplifier structure, and is directly connected to the first complementary bit line BLB1 and the second bit line BL2 in the first interconnection layer.

[0042] The balancing structure includes a first balancing tube <n1>and the second equalizing tube <n2>.

[0043] First equalizing tube <n1>The gate of the first equalization transistor is used to receive the first equalization signal EQ1, one of the source or the drain is connected to the first complementary bit line BLB1, and the other is used to receive the first pre-charge voltage V1, and is used to pre-charge the first bit line BL1, the first complementary bit line BLB1 and the first sensing amplifier structure to the first pre-charge voltage V1 based on the first equalization signal EQ1; in this embodiment, the first equalization transistor <n1>The source is connected to the first complementary bit line BLB1, and the drain is used to receive the first precharge voltage V1, and is used to precharge the first bit line BL1, the first complementary bit line BLB1 and the first sensing amplifier structure to the first precharge voltage V1 based on the first equalization signal EQ1.

[0044] Second equalizing tube <n2>The gate of the second equalization transistor is used to receive the second equalization signal EQ2, one of the source or the drain is connected to the second bit line BL2, and the other is used to receive the second pre-charge voltage V2, and is used to pre-charge the second bit line BL2, the second complementary bit line BLB2, and the second sensing amplifier structure to the second pre-charge voltage V2 based on the second equalization signal EQ2; in this embodiment, the second equalization transistor <n2>The source is connected to the second bit line BL2, the drain is used to receive the second precharge voltage V2, and is used to precharge the second bit line BL2, the second complementary bit line BLB2 and the second sensing amplifier structure to the second precharge voltage V2 based on the second equalization signal EQ2.

[0045] It should be noted that in the above description, the specific connection method of the "source" and "drain" does not constitute a limitation of this embodiment. In other embodiments, the connection method of "drain" can be used to replace the "source", and similarly, the connection method of "source" can be used to replace the "drain".

[0046] The bit line / complementary bit line is directly connected through the equalizing tube to directly charge the bit line and the complementary bit line, thereby avoiding the need for the switching transistor to be turned on in the pre-charging process to pre-charge the bit line / complementary bit line, thereby speeding up the charging speed of the bit line and the complementary bit line.

[0047] It should be noted that the "first pre-charge voltage V1" and "second pre-charge voltage V2" mentioned above are the voltages required for pre-charging the memory bit lines and complementary bit lines during the pre-charging stage. The specific voltage sizes are set according to the pre-charge voltages required for normal operation of the memory. This embodiment does not constitute a limitation on the values ​​of the "first pre-charge voltage V1" and "second pre-charge voltage V2".

[0048] In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, that is, the same control signal is used to precharge the bit line and the complementary bit line. The first precharge voltage V1 and the second precharge voltage V2 are the same precharge voltage V BLP In this embodiment, the precharge voltage V BLP =1 / 2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the precharge voltage V BLP It can be set according to the specific application scenario.

[0049] Furthermore, in this embodiment, the first equalizing tube <n1>The drain and the second equalizer <n2>The drain of the BLP , through the first equalizing tube <n1>The drain and the second equalizer <n2>The drain of the first balancing tube is connected to <n1>and the second equalizing tube <n2>The spacing is set to reduce the layout area of ​​the readout circuit structure.

[0050] In this embodiment, to clearly distinguish the one memory array from the other memory array, in the subsequent description, the memory array to which the first sensing amplifier structure is connected via the first bit line BL1 is referred to as the "first memory array," and the memory array to which the second sensing amplifier structure is connected via the second complementary bit line BLB2 is referred to as the "second memory array."

[0051] In addition, in the word line extension direction, there is more than one set of sensing amplifier structures between adjacent memory arrays. This embodiment uses a 2x2 layout structure as an example to explain in detail, as follows:

[0052] In this embodiment, a third sensing amplification structure, a fourth sensing amplification structure, a third equalization structure, and a fourth equalization structure are further provided in the structural layer.

[0053] In the direction of bit line extension, the third sensing amplifier structure and the fourth sensing amplifier structure are arranged adjacent to each other, and are used to sense the voltage of the storage cell and output a logic 1 or 0 corresponding to the voltage; in the direction of word line extension, the third sensing amplifier structure and the first sensing amplifier structure are arranged adjacent to each other, and the fourth sensing amplifier structure and the second sensing amplifier structure are arranged adjacent to each other.

[0054] Among them, the third sensing amplifier structure is connected to the "first storage array" through the third bit line BL3 and to the "second storage array" through the third complementary bit line BLB3. The fourth sensing amplifier structure is connected to the "first storage array" through the fourth bit line BL4 and to the "second storage array" through the fourth complementary bit line BLB4.

[0055] For the third bit line BL3, the fourth bit line BL4, the third complementary bit line BLB3 and the fourth complementary bit line BLB4, one of the third bit line BL3 or the third complementary bit line BLB3 is set in the first interconnection layer, and at least part of the other is set in the second interconnection layer; one of the fourth bit line BL4 or the fourth complementary bit line BLB4 is set in the first interconnection layer, and at least part of the other is set in the second interconnection layer.

[0056] It should be noted that the first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL4 are four adjacent bit lines in the same storage array; the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3 and the fourth complementary bit line BLB4 are four adjacent bit lines in the same storage array.

[0057] Specifically, in this embodiment, the third bit line BL3 is arranged in the first interconnection layer, at least a portion of the third complementary bit line BLB3 is arranged in the second interconnection layer, the third complementary bit line BLB3 passes through the region where the fourth sensing amplification structure is located in the second interconnection layer and is coupled to the third sensing amplification structure, the fourth bit line BL4 is at least partially arranged in the second interconnection layer, the fourth bit line BL4 passes through the region where the third sensing amplification structure is located in the second interconnection layer and is coupled to the fourth sensing amplification structure, and the fourth complementary bit line BLB4 is arranged in the first interconnection layer.

[0058] The third complementary bit line BLB3 passes through the area where the second sensing amplifier structure is located and is coupled to the first sensing amplifier structure. That is, the third complementary bit line BLB3 does not need to occupy additional layout area to complete wiring, thereby reducing the layout area of ​​the readout circuit structure. The fourth bit line BL4 passes through the area where the first sensing amplifier structure is located and is coupled to the second sensing amplifier structure. That is, the fourth bit line BL4 does not need to occupy additional layout area to complete wiring, thereby reducing the layout area of ​​the readout circuit structure.

[0059] The equalization structure is also directly connected to the third complementary bit line BLB3 and the fourth bit line BL4 for precharging the third bit line BL3, the third complementary bit line BLB3, the third sensing amplifier structure, the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sensing amplifier structure.

[0060] In this embodiment, the equalization structure is also directly connected to the third complementary bit line BLB3 and the fourth bit line BL4 in the first interconnection layer.

[0061] Specifically, the balancing structure further includes a third balancing tube <n3>and the fourth equalizer <n4>, in the direction of word line extension, the third equalizer <n3>Set in the first equalizing tube <n1>One side, with the first equalizing tube <n1>Share the same grid, the fourth equalizer <n4>Set in the second equalizing tube <n2>One side, with the second equalizing tube <n2>share the same gate.

[0062] The third equalizing tube <n3>The gate of the third equalizer transistor is used to receive the first equalization signal EQ1, one of the source or the drain is connected to the third complementary bit line BLB3, and the other is used to receive the first pre-charge voltage V1, and is used to pre-charge the third bit line BL3, the third complementary bit line BLB3 and the third sensing amplifier structure to the first pre-charge voltage V1 based on the first equalization signal EQ1; in this embodiment, the third equalizer transistor <n3>The source is connected to the third complementary bit line BLB3, and the drain is used to receive the first precharge voltage V1, and is used to precharge the third bit line BL3, the third complementary bit line BLB3 and the third sensing amplifier structure to the first precharge voltage V1 based on the first equalization signal EQ1.

[0063] Fourth equalizing tube <n4>The gate of the fourth equalizer transistor is used to receive the second equalization signal EQ2, one of the source or the drain is connected to the fourth bit line BL4, and the other is used to receive the second pre-charge voltage V2, and is used to pre-charge the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sense amplifier structure to the second pre-charge voltage V2 based on the second equalization signal EQ2; in this embodiment, the fourth equalizer transistor <n4>The source is connected to the fourth bit line BL4, and the drain is used to receive the second precharge voltage V2, and is used to precharge the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sensing amplifier structure to the second precharge voltage V2 based on the second equalization signal EQ2.

[0064] It should be noted that in the above description, the specific connection method of the "source" and "drain" does not constitute a limitation of this embodiment. In other embodiments, the connection method of "drain" can be used to replace the "source", and similarly, the connection method of "source" can be used to replace the "drain".

[0065] The bit line / complementary bit line is directly connected through the equalizing tube to directly charge the bit line and the complementary bit line, thereby avoiding the need for the switching transistor to be turned on in the pre-charging process to pre-charge the bit line / complementary bit line, thereby speeding up the charging speed of the bit line and the complementary bit line.

[0066] It should be noted that the "first pre-charge voltage V1" and "second pre-charge voltage V2" mentioned above are the voltages required for pre-charging the memory bit lines and complementary bit lines during the pre-charging stage. The specific voltage sizes are set according to the pre-charge voltages required for normal operation of the memory. This embodiment does not constitute a limitation on the values ​​of the "first pre-charge voltage V1" and "second pre-charge voltage V2".

[0067] In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, that is, the same control signal is used to precharge the bit line and the complementary bit line. The first precharge voltage V1 and the second precharge voltage V2 are the same precharge voltage V BLP In this embodiment, the precharge voltage V BLP =1 / 2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the precharge voltage V BLP It can be set according to the specific application scenario.

[0068] Furthermore, in this embodiment, the third equalizing tube <n3>The drain and the fourth equalizer <n4>The drain of the BLP , through the third equalizing tube <n3>The drain and the fourth equalizer <n4>The drain of the third balancing tube is connected to <n3>and the fourth equalizer <n4>The spacing is set to reduce the layout area of ​​the readout circuit structure.

[0069] Continue to refer Figure 1 and Figure 2 The readout circuit structure further includes a first data readout module, which includes: a first input / output tube, a third input / output tube, a fifth input / output tube and a seventh input / output tube.

[0070] Among them, one of the source or drain of the first input / output tube is directly connected to the first input / output line, and the other is connected to the first bit line. The gate of the first input / output tube is used to receive a column selection signal and turn on the first input / output tube based on the column selection signal, so that the first input / output line is electrically connected to the first bit line, thereby outputting the electrical signal carried by the first bit line through the first input / output line. In this embodiment, the source of the first input / output tube is connected to the first input / output line, and the drain is connected to the first bit line.

[0071] One of the source or drain of the third input / output tube is directly connected to the third input / output line, and the other is connected to the second bit line. The gate of the third input / output tube is used to receive a column selection signal and turn on the third input / output tube based on the column selection signal, so that the third input / output line is electrically connected to the second bit line, thereby outputting the electrical signal carried by the second bit line through the third input / output line. In this embodiment, the source of the third input / output tube is connected to the third input / output line, and the drain is connected to the second bit line.

[0072] One of the source or drain of the fifth input / output tube is directly connected to the fifth input / output line, and the other is connected to the third bit line. The gate of the fifth input / output tube is used to receive a column selection signal and turn on the fifth input / output tube based on the column selection signal, so that the fifth input / output line is electrically connected to the third bit line, thereby outputting the electrical signal carried by the third bit line through the fifth input / output line. In this embodiment, the source of the fifth input / output tube is connected to the fifth input / output line, and the drain is connected to the third bit line.

[0073] One of the source or drain of the seventh input / output tube is directly connected to the seventh input / output line, and the other is connected to the fourth bit line. The gate of the seventh input / output tube is used to receive a column selection signal and turn on the seventh input / output tube based on the column selection signal, so that the seventh input / output line is electrically connected to the fourth bit line, thereby outputting the electrical signal carried by the fourth bit line through the seventh input / output line. In this embodiment, the source of the seventh input / output tube is connected to the seventh input / output line, and the drain is connected to the fourth bit line.

[0074] It should be noted that in the above description, the specific connection method of the "source" and "drain" does not constitute a limitation of this embodiment. In other embodiments, the connection method of "drain" can be used to replace the "source", and similarly, the connection method of "source" can be used to replace the "drain".

[0075] The second data readout module includes: a second input / output tube, a fourth input / output tube, a sixth input / output tube and an eighth input / output tube.

[0076] In which, one of the source or drain of the second input / output tube is directly connected to the second input / output line, and the other is connected to the first complementary bit line. The gate of the second input / output tube is used to receive a column selection signal and turn on the second input / output tube based on the column selection signal, so that the second input / output line is electrically connected to the first complementary bit line, thereby outputting the electrical signal carried by the first complementary bit line through the second input / output line. In this embodiment, the source of the second input / output tube is connected to the second input / output line, and the drain is connected to the first complementary bit line.

[0077] One of the source or the drain of the fourth input / output tube is directly connected to the fourth input / output line, and the other is connected to the second complementary bit line. The gate of the fourth input / output tube is used to receive a column selection signal and turn on the fourth input / output tube based on the column selection signal, so that the fourth input / output line is electrically connected to the second complementary bit line, thereby outputting the electrical signal carried by the second complementary bit line through the fourth input / output line. In this embodiment, the source of the fourth input / output tube is connected to the fourth input / output line, and the drain is connected to the second complementary bit line.

[0078] One of the source or drain of the sixth input / output tube is directly connected to the sixth input / output line, and the other is connected to the third complementary bit line. The gate of the sixth input / output tube is used to receive a column selection signal and turn on the sixth input / output tube based on the column selection signal, so that the sixth input / output line is electrically connected to the third complementary bit line, thereby outputting the electrical signal carried by the third complementary bit line through the sixth input / output line. In this embodiment, the source of the sixth input / output tube is connected to the sixth input / output line, and the drain is connected to the third complementary bit line.

[0079] One of the source or drain of the eighth input / output tube is directly connected to the eighth input / output line, and the other is connected to the fourth complementary bit line. The gate of the eighth input / output tube is used to receive a column selection signal and turn on the eighth input / output tube based on the column selection signal, so that the eighth input / output line is electrically connected to the fourth complementary bit line, thereby outputting the electrical signal carried by the fourth complementary bit line through the eighth input / output line. In this embodiment, the source of the eighth input / output tube is connected to the eighth input / output line, and the drain is connected to the fourth complementary bit line.

[0080] It should be noted that in the above description, the specific connection method of the "source" and "drain" does not constitute a limitation of this embodiment. In other embodiments, the connection method of "drain" can be used to replace the "source", and similarly, the connection method of "source" can be used to replace the "drain".

[0081] refer to Figure 1 The first sensing amplification structure and the third sensing amplification structure are described in detail below by taking the first sensing amplification structure as an example. The first sensing amplification structure includes:

[0082] The sensing amplifier module is connected to the first bit line BL1 through the read bit line SABL and to the first complementary bit line BLB1 through the complementary read bit line SABLB, and is used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage.

[0083] Specifically, the sensing amplifier module includes: a first sensing amplifier N-type transistor <n1400>The gate is connected to the first bit line BL1, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS. When the sensing amplifier module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; the second sensing amplifier N transistor <n1405>The gate is connected to the first complementary bit line BLB1, the drain is connected to the read bit line SABL, and the source is connected to the second signal terminal NCS; the first sense amplifier P tube <p1401>The gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, and the source is connected to the first signal terminal PCS. When the sensing amplifier module is in the amplification stage, the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1; the second sensing amplifier P tube <p1400>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, and the source is connected to the first signal terminal PCS.

[0084] The isolation module is connected between the complementary read bit line SABLB and the first complementary bit line BLB1, and between the read bit line SABL and the first bit line BL1, and is used to isolate the signal interaction between the first bit line BL1, the first complementary bit line BLB1 and the read bit line SABL and the complementary read bit line SABLB according to the isolation signal ISO.

[0085] Specifically, the isolation module includes: a first isolation tube <n1402>The gate is used to receive the isolation signal ISO, the source is connected to the first bit line BL1, the drain is connected to the read bit line SABL, and the second isolation transistor <n1403>The gate is used to receive the isolation signal ISO, the source is connected to the first complementary bit line BLB1, and the drain is connected to the complementary readout bit line SABLB.

[0086] The offset cancellation module is connected between the read bit line SABL and the first complementary bit line BLB1, and between the complementary read bit line SABLB and the first bit line BL1, and is used to adjust the source-drain conduction difference between NMOS or PMOS tubes in the sense amplifier module according to the offset cancellation signal OC.

[0087] It should be noted that the "source-drain conduction difference" mentioned above refers to the following: due to changes in manufacturing process, temperature, etc., the first sensing amplifier N-type transistor <n1400>and the second sensing amplifier N tube <n1405>And the first sensing amplifier P tube <p1401>and the second sensing amplifier P tube <p1400>They may have different threshold voltages. In this case, the sensing amplifier module may be <p1401>and the second sensing amplifier P tube <p1400>and the first sensing amplifier N tube <n1400>and the second sensing amplifier N tube <n1405>The difference between the threshold voltages causes offset noise.

[0088] Specifically, the offset elimination module includes: a first offset elimination tube <n1401>The gate is used to receive the offset cancellation signal OC, the source is connected to the first bit line BL1, and the drain is connected to the complementary readout bit line SABLB; the second offset cancellation transistor <n1404>The gate is used to receive the offset cancellation signal OC, the source is connected to the first complementary bit line BLB1, and the drain is connected to the readout bit line SABL.

[0089] Those skilled in the art will appreciate that the structure of the third sensing amplifier structure is the same as that of the first sensing amplifier structure, and the above description is also applicable after replacing the features of the corresponding structures. Specifically, the corresponding structures include: the first bit line BL1 corresponds to BL3, the first complementary bit line BLB1 corresponds to BLB3, the first equalizer transistor <n1>Corresponding to <n5>, the third equalizing tube <n3>Corresponding to <n7>, the first sensing amplifier N tube <n1400>Corresponding to <n1410>, the second sensing amplifier N tube <n1405>Corresponding to <n1415>, the first sensing amplifier P tube <p1401>Corresponding to <p1411>, the second sensing amplifier P tube <p1400>Corresponding to <p1410>, first isolation tube <n1402>Corresponding to <n1412>, Second isolation tube <n1403>Corresponding to <n1413>, the first offset elimination tube <n1401>Corresponding to <n1411>, the second offset elimination tube <n1404>Corresponding to <n1414>.

[0090] For the first data read-out module, the source of the first input / output tube is connected to the first input / output line I / O1, the drain is directly connected to the first bit line BL1, and the gate is used to receive the column selection signal CY. The source of the third input / output tube is connected to the third input / output line I / O3, the drain is directly connected to the second bit line BL2, and the gate is used to receive the column selection signal CY. The source of the fifth input / output tube is connected to the fifth input / output line I / O5, the drain is directly connected to the third bit line BL3, and the gate is used to receive the column selection signal CY. The source of the seventh input / output tube is connected to the seventh input / output line I / O7, the drain is directly connected to the fourth bit line BL4, and the gate is used to receive the column selection signal CY.

[0091] Through the same column selection signal CY, the first input / output tube, the third input / output tube, the fifth input / output tube and the seventh input / output tube are turned on, so that the level signal transmitted in the first bit line BL1 is derived through the first input / output line I / O1, the level signal transmitted in the second bit line BL2 is derived through the third input / output line I / O3, the level signal transmitted in the third bit line BL3 is derived through the fifth input / output line I / O5, and the level signal transmitted in the fourth bit line BL4 is derived through the seventh input / output line I / O7.

[0092] refer to Figure 2 The second sensing amplification structure and the fourth sensing amplification structure are described in detail below using the second sensing amplification structure as an example. The second sensing amplification structure includes:

[0093] The sensing amplifier module is connected to the second bit line BL2 through the read bit line SABL and connected to the second complementary bit line BLB2 through the complementary read bit line SABLB, and is used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage.

[0094] Specifically, the sensing amplifier module includes: a third sensing amplifier N-type transistor <n1425>, the gate is connected to the second bit line BL2, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS. When the sensing amplifier module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; the fourth sensing amplifier N transistor <n1420>The gate is connected to the second complementary bit line BLB2, the drain is connected to the read bit line SABL, and the source is connected to the second signal terminal NCS; the third sense amplifier P tube <p1421>, the gate is connected to the read bit line SABL, the drain is connected to the complementary read bit line SABLB, and the source is connected to the first signal terminal PCS. When the sense amplifier module is in the amplification stage, the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1; the fourth sense amplifier P transistor <p1420>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, and the source is connected to the first signal terminal PCS.

[0095] The isolation module is connected between the complementary read bit line SABLB and the second complementary bit line BLB2, and is connected between the read bit line SABL and the second bit line BL2, and is used to isolate the signal interaction between the second bit line BL2, the second complementary bit line BLB2 and the read bit line SABL and the complementary read bit line SABLB according to the isolation signal ISO.

[0096] Specifically, the isolation module includes: a first isolation tube <n1423>The gate is used to receive the isolation signal ISO, the source is connected to the second bit line BL2, the drain is connected to the read bit line SABL, and the second isolation transistor <n1422>The gate is used to receive the isolation signal ISO, the source is connected to the second complementary bit line BLB2, and the drain is connected to the complementary readout bit line SABLB.

[0097] The offset cancellation module is connected between the read bit line SABL and the second complementary bit line BLB2, and is also connected between the complementary read bit line SABLB and the second bit line BL2, and is used to adjust the source-drain conduction difference between NMOS transistors or PMOS transistors in the sense amplifier module according to the offset cancellation signal OC.

[0098] It should be noted that the "source-drain conduction difference" mentioned above refers to the following: due to changes in manufacturing process, temperature, etc., the third sense amplifier N transistor <n1425>and the fourth sense amplifier N tube <n1420>And the third sensing amplifier P tube <p1421>and the fourth sensing amplifier P tube <p1420>Each other may have different threshold voltages. In this case, the sense amplifier module may be due to the third sense amplifier P transistor <p1421>and the fourth sensing amplifier P tube <p1420>And the third sensing amplifier N tube <n1445>and the fourth sense amplifier N tube <n1420>The difference between the threshold voltages causes offset noise.

[0099] Specifically, the offset elimination module includes: a third offset elimination tube <n1424>The gate is used to receive the offset cancellation signal OC, the source is connected to the second bit line BL2, and the drain is connected to the complementary readout bit line SABLB; the fourth offset cancellation transistor <n1421>The gate is used to receive the offset cancellation signal OC, the source is connected to the second complementary bit line BLB2, and the drain is connected to the readout bit line SABL.

[0100] Those skilled in the art will appreciate that the structure of the fourth sensing amplifier structure is the same as that of the second sensing amplifier structure, and the above description is also applicable after replacing the features of the corresponding structures. Specifically, the corresponding structures include: the second bit line BL2 corresponds to BL4, the second complementary bit line BLB2 corresponds to BLB4, and the second equalizer transistor <n2>Corresponding to <n6>, the fourth equalizing tube <n4>Corresponding to <n8>, the third sensing amplifier N tube <n1425>Corresponding to <n1435>, the fourth sensing amplifier N tube <n1420>Corresponding to <n1430>, the third sensing amplifier P tube <p1421>Corresponding to <p1431>, the fourth sensing amplifier P tube <p1420>Corresponding to <p1430>, the third isolation tube <n1423>Corresponding to <n1433>, the fourth isolation tube <n1422>Corresponding to <n1432>, the third offset elimination tube <n1424>Corresponding to <n1434>, the fourth offset elimination tube <n1421>Corresponding to <n1431>.

[0101] For the second data read-out module, the source of the second input / output tube is connected to the second input / output line I / O2, the drain is directly connected to the first complementary bit line BLB1, and the gate is used to receive the column selection signal CY. The source of the fourth input / output tube is connected to the fourth input / output line I / O4, the drain is directly connected to the second complementary bit line BLB2, and the gate is used to receive the column selection signal CY. The source of the sixth input / output tube is connected to the sixth input / output line I / O6, the drain is directly connected to the third complementary bit line BLB3, and the gate is used to receive the column selection signal CY. The source of the eighth input / output tube is connected to the eighth input / output line I / O8, the drain is directly connected to the fourth complementary bit line BLB4, and the gate is used to receive the column selection signal CY.

[0102] Through the same column selection signal CY, the second input / output tube, the fourth input / output tube, the sixth input / output tube and the eighth input / output tube are turned on, so that the level signal transmitted in the first complementary bit line BLB1 is derived through the second input / output line I / O2, the level signal transmitted in the second complementary bit line BLB2 is derived through the fourth input / output line I / O4, the level signal transmitted in the third complementary bit line BLB3 is derived through the sixth input / output line I / O6, and the level signal transmitted in the fourth complementary bit line BLB4 is derived through the eighth input / output line I / O8.

[0103] refer to Figure 3 The left side is the layout of the second interconnect layer, the middle is the layout of the first interconnect layer, and the right side is the layout of the structural layer. The areas with the same number represent the layouts of different layers that require electrical connection. Among them, the oblique frame area is the layout of the active layer, the white frame area is the layout of the gate layer, and the shaded area is the layout of the contact layer.

[0104] The following description will be made using the first sensing amplifier structure as an example. For the third sensing amplifier structure, analogy can be made based on the accompanying drawings, and this embodiment will not be described in detail. For the structural layer layout, from top to bottom, it is as follows:

[0105] First data readout module, first sensing amplifier N-type transistor <n1425>, the first isolation and offset elimination integrated module, the second sense amplifier P tube <p1400>, the first sensing amplifier P tube <p1401>, the second isolation and offset elimination integrated module, the second sensing amplifier N tube <n1405>and partially balanced structures.

[0106] For the first data readout module, the first input / output tube <n1001>The gate of the third input / output tube <n1003>The gate of the fifth input / output tube <n1005>The gate and seventh input / output tube <n1007>The gates of the memory cells are connected together to receive the same column select signal CY. Specifically, they are connected to the first interconnect layer via contact region 109, and in the first interconnect layer, they are connected to the second interconnect layer via contact 201 to receive the column select signal CY. That is, the readout circuit structure of this embodiment can read the data stored in four consecutive memory cells through four consecutive bit lines arranged in parallel according to the same column select signal. It should be noted that in specific applications, the number of input / output transistors controlled by the same column select signal can also be set according to actual needs, that is, the amount of data to be read by the same column select signal.

[0107] In addition, it can be seen from the figure that the first input / output tube <n1001>, the third input / output tube <n1003>, the fifth input / output tube <n1005>and the seventh input / output tube <n1007>The staggered arrangement includes contact regions 105, 106, 107, and 108 between the "H"-shaped gates for connecting to the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4, respectively. Contact regions 101, 102, 103, and 104 outside the "H"-shaped gates for connecting to I / O1, I / O3, I / O5, and I / O7, respectively, on the first interconnect layer.

[0108] Furthermore, in the direction in which the word lines extend, the first bit line BL1 , the second bit line BL2 , the third bit line BL3 and the fourth bit line BL4 connected to the first data readout module 114 are spaced at equal intervals.

[0109] For the first sensing amplifier N tube <n1400>The gate is connected to the first interconnect layer through contact regions 110 and 116, and is connected to the first bit line BL1 in the first interconnect layer. The source is connected to the first interconnect layer through contact region 118, and is connected to the first complementary read bit line SABLB1 in the first interconnect layer. The drain is connected to the first interconnect layer through contact region 112, and is connected to the second interconnect layer through contact region 204 in the first interconnect layer. The second interconnect layer is used to contact the second control signal NCS, and the second control signal NCS is used to provide a low-level signal in the read phase.

[0110] For the integrated module of the first isolation and offset cancellation, including the first offset cancellation tube <n1401>and the first isolation tube <n1402>, the first offset elimination tube <n1401>and the first isolation tube <n1402>The source is connected to the first interconnect layer through the contact area 120, and the first bit line BL1 is connected to the first offset cancellation transistor. <n1401>The drain is connected to the first interconnect layer through the contact region 118, and the first complementary read bit line SABLB1 is connected to the first isolation transistor. <n1402>The drain is connected to the first interconnect layer through the contact region 122 , and the first interconnect layer is connected to the first sensing bit line SABL1 .

[0111] For the second sensing amplifier P tube <p1400>The gate is connected to the first interconnect layer through contact regions 124 and 129, and is connected to the first complementary read bit line SABLB1 in the first interconnect layer. The source is connected to the first interconnect layer through contact region 126, and is connected to the first read bit line SABL1 in the first interconnect layer. The drain is connected to the first interconnect layer through contact region 127, and is connected to the second interconnect layer through contact region 206 in the first interconnect layer. The first control signal PCS is received at the second interconnect layer. The first control signal PCS is used to provide a high-level signal in the read phase.

[0112] For the first sensing amplifier P tube <p1401>The gate is connected to the first interconnect layer through contact regions 130 and 135, and is connected to the first read bit line SABL1 at the first interconnect layer. The source is connected to the first interconnect layer through contact region 132, and is connected to the first complementary read bit line SABLB1 at the first interconnect layer. The drain is connected to the first interconnect layer through contact region 131, and is connected to the second interconnect layer through contact region 207 at the first interconnect layer, and receives the first control signal PCS at the second interconnect layer.

[0113] For integrated modules with secondary isolation and offset cancellation, including secondary isolation tubes <n1403>and the second offset cancellation tube <n1404>, the second isolation tube <n1403>and the second offset cancellation tube <n1404>The common source is connected to the first interconnect layer through the contact region 139, and the first complementary bit line BLB1 is connected to the first interconnect layer. <n1403>The drain is connected to the first interconnect layer through the contact region 137, and the first complementary readout bit line SABLB1 is connected to the first interconnect layer. <n1404>The drain is connected to the first interconnect layer through the contact region 141 , and the first interconnect layer is connected to the first sensing bit line SABL1 .

[0114] For the second sensing amplifier N tube <n1405>The gate is connected to the first interconnect layer through contact regions 143 and 148, and is connected to the first complementary bit line BLB1 in the first interconnect layer. The source is connected to the first interconnect layer through contact region 145, and is connected to the first readout bit line SABL1 in the first interconnect layer. The drain is connected to the first interconnect layer through contact region 146, and is connected to the second interconnect layer through contact region 209 in the first interconnect layer. The second control signal NCS is used to contact the second interconnect layer. The second control signal NCS is used to provide a low-level signal in the readout stage.

[0115] refer to Figure 4 The left side is the layout of the second interconnect layer, the middle is the layout of the first interconnect layer, and the right side is the layout of the structural layer. The areas with the same number represent the layouts of different layers that require electrical connection. Among them, the oblique frame area is the layout of the active layer, the white frame area is the layout of the gate layer, and the shaded area is the layout of the contact layer.

[0116] The second sensing amplifier structure is used as an example for the following description. For the fourth sensing amplifier structure, analogy can be made based on the accompanying drawings, and this embodiment will not be described in detail. For the structural layer layout, from top to bottom, it is: partial balance structure, fourth sensing amplifier N tube <n1425>, the fourth isolation and offset elimination integrated module, the third sense amplifier P tube <p1421>, the fourth sensing amplifier P tube <p1420>, the third isolation and offset elimination integrated module, the third sense amplifier N tube <n1420>The second data readout module.

[0117] For the fourth sensing amplifier N tube <n1425>, for the fourth sense amplifier N tube <n1425>The gate is connected to the first interconnect layer through contact regions 342 and 347, and is connected to the second bit line BL2 at the first interconnect layer. The source is connected to the first interconnect layer through contact region 345, and is connected to the second complementary read bit line SABLB2 at the first interconnect layer. The drain is connected to the first interconnect layer through contact region 344, and is connected to the second interconnect layer through contact region 408 at the first interconnect layer. The second control signal NCS is used to contact the second interconnect layer. The second control signal NCS is used to provide a low-level signal in the read phase.

[0118] For the fourth isolation and offset cancellation integrated module, for the second isolation and offset cancellation integrated module, including the fourth isolation tube <n1423>and the fourth offset cancellation tube <n1424>, the fourth isolation tube <n1423>and the fourth offset cancellation tube <n1424>The source is connected to the first interconnect layer through the contact region 338, and the second bit line BL2 is connected to the first interconnect layer. <n1423>The drain is connected to the first interconnect layer through the contact region 336, and the first interconnect layer is connected to the second readout bit line SABL2. <n1424>The drain is connected to the first interconnect layer through a contact region 340 , and the first interconnect layer is connected to the second complementary sense bit line SABLB2 .

[0119] For the third sensing amplifier P tube <p1421>, for the third sense amplifier P tube <p1421>The gate is connected to the first interconnect layer through the contact region 334, and is connected to the second complementary read bit line SABLB2 at the first interconnect layer. The source is connected to the first interconnect layer through the contact region 331, and is connected to the second read bit line SABL2 at the first interconnect layer. The drain is connected to the first interconnect layer through the contact region 332, and is connected to the second interconnect layer through the contact region 407 at the first interconnect layer, and receives the first control signal PCS at the second interconnect layer.

[0120] For the fourth sensing amplifier P tube <p1420>, for the fourth sense amplifier P tube <p1420>The gate is connected to the first interconnect layer through the contact region 323, and is connected to the second read bit line SABL2 at the first interconnect layer. The source is connected to the first interconnect layer through the contact region 326, and is connected to the second complementary read bit line SABLB2 at the first interconnect layer. The drain is connected to the first interconnect layer through the contact region 325, and is connected to the second interconnect layer through the contact region 405 at the first interconnect layer. The first control signal PCS is received at the second interconnect layer. The first control signal PCS is used to provide a high-level signal in the read phase.

[0121] For the integrated module of third isolation and offset cancellation, including the third offset cancellation tube <n1421>and the third isolation tube <n1422>, the third offset cancellation tube <n1421>and the third isolation tube <n1422>The common source is connected to the first interconnect layer through the contact region 319, and the second complementary bit line BLB2 is connected to the first interconnect layer. <n1421>The drain is connected to the first interconnect layer through the contact region 317, and the first interconnect layer is connected to the second readout bit line SABL2, the third isolation transistor <n1422>The drain is connected to the first interconnect layer through a contact region 321, and the first interconnect layer is connected to the second complementary readout bit line SABLB2.

[0122] For the third sensing amplifier N tube <n1420>The gate is connected to the first interconnect layer through contact regions 310 and 315, and is connected to the second complementary bit line BLB2 in the first interconnect layer. The source is connected to the first interconnect layer through contact region 312, and is connected to the second readout bit line SABL2 in the first interconnect layer. The drain is connected to the first interconnect layer through contact region 313, and is connected to the second interconnect layer through contact region 404 in the first interconnect layer. It is used to contact the second control signal NCS in the second interconnect layer. The second control signal NCS is used to provide a low-level signal in the readout stage.

[0123] For the second data readout module, the second input / output tube <n1002>The gate of the fourth input / output tube <n1004>The gate of the sixth input / output tube <n1006>The gate and the eighth input / output tube <n1008>The gates of the memory cells are connected together to receive the same column select signal CY. Specifically, they are connected to the first interconnect layer via contact region 309, and in the first interconnect layer, they are connected to the second interconnect layer via contact 201 to receive the column select signal CY. That is, the readout circuit structure of this embodiment can read the data stored in four consecutive memory cells through four consecutive complementary bit lines arranged in parallel according to the same column select signal. It should be noted that in specific applications, the number of input / output transistors controlled by the same column select signal can also be set according to actual needs, that is, the amount of data to be read by the same column select signal.

[0124] In addition, it can be seen from the figure that the second input / output tube <n1002>, the fourth input / output tube <n1004>, the sixth input / output tube <n1006>and the eighth input / output tube <n1008>The staggered arrangement includes contact regions between the "H"-shaped gates for connecting to the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4. Contact regions 301, 302, 303, and 304 outside the "H"-shaped gates are used to connect to I / O2, I / O4, I / O6, and I / O8, respectively, at the first interconnect layer.

[0125] Furthermore, in the direction of word line extension, the first complementary bit line BLB1 , the second complementary bit line BLB2 , the third complementary bit line BLB3 and the fourth complementary bit line BLB4 connected to the second data readout module 124 are spaced at equal intervals.

[0126] for Figure 3 and Figure 4 The partial equilibrium structure in the merged structure is referenced Figure 5 , as follows:

[0127] First equalizing tube <n1>The source is connected to the first interconnect layer through the contact region 152, and is connected to the second interconnect layer through the contact region 212 in the first interconnect layer, and receives the precharge voltage V BLP The drain is connected to the first interconnect layer through the contact region 150, and is connected to the first complementary bit line BLB1 in the first interconnect layer, that is, the first balanced structure <n1>For precharging the first complementary bit line BLB1. Figure 4 The first complementary bit line BLB1 in the first interconnect layer is connected to the second interconnect layer through contact regions 404 and 412 and is wired in the second interconnect layer, thereby reducing the layout area of ​​the readout circuit structure.

[0128] Second equalizing tube <n2>The source is connected to the first interconnect layer through the contact region 352, and is connected to the second interconnect layer through the contact region 412 in the first interconnect layer, and receives the precharge voltage V BLP The drain is connected to the first interconnect layer through the contact region 350, and is connected to the second bit line BL2 in the first interconnect layer, ie, the second equilibrium structure <n2>For precharging the second bit line BL2. Figure 3 The second bit line BL2 located in the first interconnect layer is connected to the second interconnect layer through the contact regions 204 and 212 and is wired in the second interconnect layer, thereby reducing the layout area of ​​the readout circuit structure.

[0129] Among them, the first equalizing tube <n1>and the second equalizing tube <n2>Share the same source, that is, contact area 152 and contact area 352 are the same contact area, and contact area 212 and contact area 412 located in the first interconnect layer are the same contact area. <n1>and the second equalizing tube <n2>Common source, namely the first equalizing tube <n1>and the second equalizing tube <n2>Shared active area, thus reducing the first balance tube <n1>and the second equalizing tube <n2>The spacing between the two electrodes is reduced, thereby reducing the layout area of ​​the readout circuit structure.

[0130] Furthermore, refer to Figure 6 , the first equalizing tube <n1>Grid and second equalizer <n2>The gate is connected to receive the same equalization signal to pre-charge the first sensing amplifier structure and the second sensing amplifier structure.

[0131] Compared with the related art, the equalization structure is directly connected to the first bit line or the first complementary bit line to precharge the first bit line and the first complementary bit line, the equalization structure is directly connected to the second bit line or the second complementary bit line to precharge the second bit line and the second complementary bit line, the equalization structure is directly connected to the third bit line or the third complementary bit line to precharge the third bit line and the third complementary bit line, and the equalization structure is directly connected to the fourth bit line or the fourth complementary bit line to precharge the fourth bit line and the fourth complementary bit line. By directly connecting the bit lines through the equalization structure, the bit lines are directly precharged, which avoids the need for the switching transistor to be turned on in the precharging process to precharge the bit lines, thereby accelerating the charging speed of the bit lines; further, At least a portion of one of the first bit line or the first complementary bit line is arranged in the second interconnect layer, and the other is arranged in the first interconnect layer; at least a portion of one of the second bit line or the second complementary bit line is arranged in the second interconnect layer, and the other is arranged in the first interconnect layer; at least a portion of one of the third bit line or the third complementary bit line is arranged in the second interconnect layer, and the other is arranged in the first interconnect layer; at least a portion of one of the fourth bit line or the fourth complementary bit line is arranged in the second interconnect layer, and the other is arranged in the first interconnect layer. By stacking the first and second interconnect layers, the structure required for layout in each layer is reduced, thereby reducing the layout area of ​​the readout circuit structure.

[0132] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A readout circuit structure, arranged in a gap between adjacent memory arrays, characterized in that: include: a structural layer, a first interconnection layer and a second interconnection layer stacked on top of the structural layer; The structural layer is provided with a first sensing amplification structure, a second sensing amplification structure and a balancing structure; The first sensing amplifier structure is connected to one of the adjacent memory arrays via a first bit line, the first sensing amplifier structure is connected to the other of the adjacent memory arrays via a first complementary bit line, the second sensing amplifier structure is connected to one of the adjacent memory arrays via a second bit line, and the second sensing amplifier structure is connected to the other of the adjacent memory arrays via a second complementary bit line; wherein one of the first bit line or the first complementary bit line is arranged in the first interconnect layer, and at least a portion of the other is arranged in the second interconnect layer; and one of the second bit line or the second complementary bit line is arranged in the first interconnect layer, and at least a portion of the other is arranged in the second interconnect layer; The equalization structure is directly connected to the first complementary bit line and the second bit line, and is used to precharge the first bit line, the first complementary bit line, the first sense amplifier structure, the second bit line, the second complementary bit line and the second sense amplifier structure; The equalizing structure is disposed between the first sense amplifier structure and the second sense amplifier structure, and is directly connected to the first complementary bit line and the second bit line in the first interconnect layer.

2. The readout circuit structure according to claim 1, wherein: The first bit line is arranged in the first interconnect layer, at least a portion of the first complementary bit line is arranged in the second interconnect layer, the first complementary bit line is coupled to the first sensing amplification structure after passing through the region where the second sensing amplification structure is located in the second interconnect layer, at least a portion of the second bit line is arranged in the second interconnect layer, the second bit line is coupled to the second sensing amplification structure after passing through the region where the first sensing amplification structure is located in the first interconnect layer, and the second complementary bit line is arranged in the first interconnect layer.

3. The readout circuit structure according to claim 2, wherein: The balancing structure includes: a first equalizing transistor, having a gate for receiving a first equalizing signal, one of a source or a drain connected to the first complementary bit line, and the other for receiving a first pre-charge voltage, and being configured to pre-charge the first bit line, the first complementary bit line, and the first sensing amplifier structure to the first pre-charge voltage based on the first equalizing signal; The second equalizing transistor has a gate for receiving a second equalizing signal, one of a source or a drain connected to the second bit line, and the other for receiving a second pre-charge voltage. The second equalizing transistor is used to pre-charge the second bit line, the second complementary bit line, and the second sensing amplifier structure to the second pre-charge voltage based on the second equalizing signal.

4. The readout circuit structure according to claim 3, wherein: The first equalization signal and the second equalization signal are the same equalization signal, and the first pre-charge voltage and the second pre-charge voltage are the same pre-charge voltage.

5. The readout circuit structure according to claim 4, wherein: The drain of the first equalizing tube is connected to the drain of the second equalizing tube, and is used to receive the same pre-charging voltage.

6. The readout circuit structure according to claim 3, wherein: include: The structural layer is further provided with a third sensing amplification structure and a fourth sensing amplification structure; The third sensing amplifier structure is connected to one of the adjacent memory arrays via a third bit line, the third sensing amplifier structure is connected to the other of the adjacent memory arrays via a third complementary bit line, the fourth sensing amplifier structure is connected to one of the adjacent memory arrays via a fourth bit line, and the fourth sensing amplifier structure is connected to the other of the adjacent memory arrays via a fourth complementary bit line; wherein, one of the third bit line or the third complementary bit line is arranged in the first interconnect layer, and the other is at least partially arranged in the second interconnect layer; one of the fourth bit line or the fourth complementary bit line is arranged in the first interconnect layer, and the other is at least partially arranged in the second interconnect layer; The equalization structure is directly connected to the third complementary bit line and the fourth bit line, and is used to precharge the third bit line, the third complementary bit line, the third sense amplifier structure, the fourth bit line, the fourth complementary bit line and the fourth sense amplifier structure; The equalization structure is directly connected to the third complementary bit line and the fourth bit line in the first interconnection layer.

7. The readout circuit structure according to claim 6, wherein: The balancing structure further includes: a third equalizer transistor, disposed on one side of the first equalizer transistor in the word line extending direction, sharing a common gate with the first equalizer transistor, having one of a source or a drain connected to the third complementary bit line, and the other for receiving the first pre-charge voltage, and for pre-charging the third bit line, the third complementary bit line, and the third sense amplifier structure to the first pre-charge voltage based on the first equalizer signal; A fourth equalizer transistor is disposed on one side of the second equalizer transistor in the direction in which the word line extends, shares a common gate with the second equalizer transistor, has one of its source or drain connected to the fourth bit line, and the other for receiving the second pre-charge voltage. The fourth equalizer transistor is configured to pre-charge the fourth bit line, the fourth complementary bit line, and the fourth sensing amplifier structure to the second pre-charge voltage based on the second equalizer signal.

8. The readout circuit structure according to claim 6, wherein: The structural layer is further provided with a first data reading module and a second data reading module; The first data readout module includes: a first input / output tube, a third input / output tube, a fifth input / output tube, and a seventh input / output tube; The source of the first input / output tube is connected to the first input / output line, and the drain is connected to the first bit line. The source of the third input / output tube is connected to the third input / output line, and the drain is connected to the second bit line. The source of the fifth input / output tube is connected to the fifth input / output line, and the drain is connected to the third bit line. The source of the seventh input / output tube is connected to the seventh input / output line, and the drain is connected to the fourth bit line. The first bit line, the second bit line, the third bit line and the fourth bit line are four adjacent bit lines in the same memory array; The gates of the first input / output tube, the third input / output tube, the fifth input / output tube, and the seventh input / output tube are connected together, and are used to receive a column selection signal and turn on the first input / output tube, the third input / output tube, the fifth input / output tube, and the seventh input / output tube based on the column selection signal; The second data readout module includes a second input / output tube, a fourth input / output tube, a sixth input / output tube and an eighth input / output tube; The source of the second input / output tube is connected to the second input / output line, and the drain is connected to the first complementary bit line. The source of the fourth input / output tube is connected to the fourth input / output line, and the drain is connected to the second complementary bit line. The source of the sixth input / output tube is connected to the sixth input / output line, and the drain is connected to the third complementary bit line. The source of the eighth input / output tube is connected to the eighth input / output line, and the drain is connected to the fourth complementary bit line. The first complementary bit line, the second complementary bit line, the third complementary bit line and the fourth complementary bit line are four adjacent bit lines in the same memory array; The gates of the second input / output tube, the gates of the fourth input / output tube, the gates of the sixth input / output tube, and the gates of the eighth input / output tube are connected together to receive the column selection signal and turn on the second input / output tube, the fourth input / output tube, the sixth input / output tube, and the eighth input / output tube based on the column selection signal.

9. The readout circuit structure according to claim 1, wherein: The first sensing amplification structure includes: a sense amplifier module connected to the first bit line via a sense bit line and connected to the first complementary bit line via a complementary sense bit line, for sensing a voltage of a memory cell of the memory array and outputting a logic 1 or 0 corresponding to the voltage; an isolation module, connected between the complementary read bit line and the first complementary bit line, and connected between the read bit line and the first bit line, for isolating signal interactions between the first bit line, the first complementary bit line and the read bit line, the complementary read bit line according to an isolation signal; an offset cancellation module connected between the readout bit line and the first complementary bit line, and also connected between the complementary readout bit line and the first bit line, for adjusting source-drain conduction differences between NMOS transistors or between PMOS transistors in the sensing amplifier module according to an offset cancellation signal.

10. The readout circuit structure according to claim 9, wherein: The sensing amplification module includes: a first sensing amplifier N-type transistor, having a gate connected to the first bit line, a drain connected to the complementary read bit line, and a source connected to a second signal terminal, wherein when the sensing amplifier module is in an amplification phase, the second signal terminal is electrically connected to a voltage corresponding to a logic 0; a second sensing amplifier N-type transistor, having a gate connected to the first complementary bit line, a drain connected to the readout bit line, and a source connected to the second signal terminal; a first sensing amplifier P transistor, having a gate connected to the read bit line, a drain connected to the complementary read bit line, and a source connected to a first signal terminal, wherein when the sensing amplifier module is in an amplification phase, the first signal terminal is electrically connected to a voltage corresponding to a logic 1; The second sensing amplifier P transistor has a gate connected to the complementary readout bit line, a drain connected to the readout bit line, and a source connected to the first signal terminal.

11. The readout circuit structure according to claim 10, wherein: The gate structure of the first sensing amplifier N-type transistor, the gate structure of the second sensing amplifier N-type transistor, the gate structure of the first sensing amplifier P-type transistor, and the gate structure of the second sensing amplifier P-type transistor extend in the same direction; the gate structure of the MOS transistor in the isolation module and the gate structure of the MOS transistor in the offset cancellation module extend in the same direction, and the gate structure of the first sensing amplifier N-type transistor and the gate structure of the MOS transistor in the isolation module extend in directions perpendicular to each other.

12. The readout circuit structure according to claim 10, wherein: The first sensing amplifier P transistor, the second sensing amplifier P transistor, the isolation module and the offset elimination module are arranged between the first sensing amplifier N transistor and the second sensing amplifier N transistor.

13. The readout circuit structure according to claim 9, wherein: The isolation module includes: a first isolation transistor, having a gate for receiving the isolation signal, a source connected to the first bit line, and a drain connected to the readout bit line; The second isolation transistor has a gate for receiving the isolation signal, a source connected to the first complementary bit line, and a drain connected to the complementary readout bit line.

14. The readout circuit structure according to claim 13, wherein: The offset cancellation module includes: a first offset cancellation transistor, having a gate for receiving the offset cancellation signal, a source connected to the first bit line, and a drain connected to the complementary readout bit line; The second offset cancellation transistor has a gate for receiving the offset cancellation signal, a source connected to the first complementary bit line, and a drain connected to the readout bit line.

15. The readout circuit structure according to claim 14, wherein: The source of the first isolation transistor is connected to the source of the first offset cancellation transistor and is connected to the first bit line; the source of the second isolation transistor is connected to the source of the second offset cancellation transistor and is connected to the first complementary bit line.

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