Signal calibration method, memory storage device and memory control circuit unit

Abstract

The present application provides a signal calibration method, a memory storage device and a memory control circuit unit. The method comprises: generating a clock signal and a data trigger signal according to an internal clock signal; transmitting the clock signal and the data trigger signal to a target volatile memory module in a plurality of volatile memory modules through a first signal path and a second signal path respectively; obtaining an offset between the data trigger signal at the target volatile memory module and the clock signal; and in response to the offset being greater than a threshold value, storing initial delay setting of the data trigger signal according to delay information of the data trigger signal. Thus, the problem of timing disorder between the clock signal and the data trigger signal generated when performing signal correction on the data trigger signal later can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a signal calibration technique, and more particularly, to a signal calibration method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] Dynamic random access memory (DRAM) and other volatile memories have advantages of fast access speed and small size, and thus are quite suitable for being arranged in a portable electronic device as a temporary storage medium for data. In addition, a memory controller can be used to control and access the volatile memory.

[0003] Conventionally, the clock signal and the data trigger signal (i.e., DQS signal) used for communication and / or data transmission between a memory interface and a volatile memory can be corrected by wire design and sending a preset bit string, so as to improve the correctness of subsequent data reading. However, in an architecture using multiple volatile memories, signal correction cannot be simply performed by wire design. In addition, in high-speed signal transmission, if the boundary between the clock signal and the data trigger signal to be corrected is very close, then after direct correction, timing disorder may occur between the two signals after locking (for example, the T(0)th pulse in the clock signal is locked to the T(1)th pulse in the data trigger signal), which affects the data access performance of the volatile memory. SUMMARY

[0004] The present application provides a signal calibration method, a memory storage device, and a memory control circuit unit, which can improve the above-mentioned problems.

[0005] An exemplary embodiment of the present application provides a signal calibration method for a memory storage device including a plurality of volatile memory modules, the signal calibration method comprising: generating a clock signal and a data trigger signal according to an internal clock signal; transmitting the clock signal and the data trigger signal to a target volatile memory module in the plurality of volatile memory modules through a first signal path and a second signal path, respectively; obtaining an offset between the data trigger signal at the target volatile memory module and the clock signal; and in response to the offset being greater than a threshold value, storing initial delay settings of the data trigger signal according to delay information of the data trigger signal.

[0006] In an example embodiment of the present application, the data trigger signals include a first data trigger signal and a second data trigger signal, the first data trigger signal has a first offset between the target volatile memory module end and the clock signal, the second data trigger signal has a second offset between the target volatile memory module end and the clock signal, the second offset is greater than the threshold, and the step of storing the initial delay setting of the data trigger signal according to the delay information of the data trigger signal in response to the offset being greater than the threshold includes the step of storing the initial delay setting of the data trigger signal according to the delay information of the second data trigger signal in response to the second offset being greater than the threshold.

[0007] In an example embodiment of the present application, the signal calibration method further includes the step of discarding the delay information of the first data trigger signal in response to the first offset being not greater than the threshold.

[0008] In an example embodiment of the present application, the signal calibration method further includes the step of increasing the delay of the first data trigger signal by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of a clock period of the data trigger signal, wherein m and n are positive integers.

[0009] In an example embodiment of the present application, the signal calibration method further includes the steps of generating the data trigger signal according to the internal clock signal and the initial delay setting after storing the initial delay setting, and adjusting the delay of the data trigger signal according to the clock signal to align the data trigger signal between the target volatile memory module end and the clock signal.

[0010] In an example embodiment of the present application, the step of generating the data trigger signal according to the internal clock signal and the initial delay setting includes the steps of detecting a power-on signal, and generating the data trigger signal according to the internal clock signal and the initial delay setting in response to the power-on signal.

[0011] In an example embodiment of the present application, the step of obtaining the offset between the target volatile memory module end and the clock signal of the data trigger signal includes the steps of obtaining a plurality of candidate offsets between the target volatile memory module end and the clock signal of the data trigger signal, and performing statistical operation on the plurality of candidate offsets to obtain the offset.

[0012] An exemplary embodiment of the present application further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, a plurality of volatile memory modules, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module, and the plurality of volatile memory modules. The memory control circuit unit is configured to: generate a clock signal and a data trigger signal according to an internal clock signal; transmit the clock signal and the data trigger signal to a target volatile memory module among the plurality of volatile memory modules through a first signal path and a second signal path, respectively; obtain an offset between the data trigger signal at the target volatile memory module and the clock signal; and in response to the offset being greater than a threshold value, store an initial delay setting of the data trigger signal according to delay information of the data trigger signal.

[0013] In an exemplary embodiment of the present application, the data trigger signal includes a first data trigger signal and a second data trigger signal, a first offset between the first data trigger signal at the target volatile memory module and the clock signal is not greater than the threshold value, a second offset between the second data trigger signal at the target volatile memory module and the clock signal is greater than the threshold value, and the operation of the memory control circuit unit, in response to the offset being greater than the threshold value, of storing the initial delay setting of the data trigger signal according to the delay information of the data trigger signal includes, in response to the second offset being greater than the threshold value, storing the initial delay setting of the data trigger signal according to delay information of the second data trigger signal.

[0014] In an exemplary embodiment of the present application, the memory control circuit unit is further configured to, in response to the first offset not being greater than the threshold value, discard delay information of the first data trigger signal.

[0015] In an exemplary embodiment of the present application, the memory control circuit unit is further configured to increase a delay of the first data trigger signal by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of one clock period of the data trigger signal, where m and n are positive integers.

[0016] In an exemplary embodiment of the present application, the memory control circuit unit is further configured to, after storing the initial delay setting, generate the data trigger signal according to the internal clock signal and the initial delay setting; and adjust a delay of the data trigger signal according to the clock signal to align the data trigger signal at the target volatile memory module with the clock signal.

[0017] In an example embodiment of the present disclosure, the operation of the memory control circuit unit to generate the data trigger signal according to the internal clock signal and the initial delay setting includes detecting a power-on signal, and in response to the power-on signal, generating the data trigger signal according to the internal clock signal and the initial delay setting.

[0018] In an example embodiment of the present disclosure, the operation of the memory control circuit unit to obtain the offset between the data trigger signal and the clock signal at the target volatile memory module includes obtaining a plurality of candidate offsets between the data trigger signal and the clock signal at the target volatile memory module, and performing a statistical operation on the plurality of candidate offsets to obtain the offset.

[0019] An example embodiment of the present disclosure further provides a memory control circuit unit for controlling a plurality of volatile memory modules. The memory control circuit unit includes a memory controller, a memory interface circuit, and a control circuit. The memory interface circuit is connected to the memory controller and the plurality of volatile memory modules. The control circuit is connected to the memory interface circuit. The memory interface circuit is configured to generate a clock signal and a data trigger signal according to an internal clock signal. The memory interface circuit is further configured to transmit the clock signal and the data trigger signal to a target volatile memory module of the plurality of volatile memory modules via a first signal path and a second signal path, respectively. The control circuit is configured to obtain an offset between the data trigger signal and the clock signal at the target volatile memory module. The control circuit is further configured to store an initial delay setting of the data trigger signal according to delay information of the data trigger signal in response to the offset being greater than a threshold value.

[0020] In an example embodiment of the present disclosure, the data trigger signal includes a first data trigger signal and a second data trigger signal, a first offset between the first data trigger signal and the clock signal at the target volatile memory module is not greater than the threshold value, a second offset between the second data trigger signal and the clock signal at the target volatile memory module is greater than the threshold value, and the operation of the control circuit to store the initial delay setting of the data trigger signal according to the delay information of the data trigger signal in response to the offset being greater than the threshold value includes storing the initial delay setting of the data trigger signal according to delay information of the second data trigger signal in response to the second offset being greater than the threshold value.

[0021] In an example embodiment of the present application, the control circuit is further configured to discard the delay information of the first data trigger signal in response to the first offset being not greater than the threshold value.

[0022] In an example embodiment of the present application, the memory interface circuit is further configured to increase a delay of the first data trigger signal by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of a clock period of the data trigger signal, where m and n are positive integers.

[0023] In an example embodiment of the present application, the memory interface circuit is further configured to generate the data trigger signal according to the internal clock signal and the initial delay setting after storing the initial delay setting, and adjust a delay of the data trigger signal according to the clock signal to align the data trigger signal with the clock signal at the target volatile memory module.

[0024] In an example embodiment of the present application, the operation of generating the data trigger signal according to the internal clock signal and the initial delay setting includes detecting a power-on signal, and generating the data trigger signal according to the internal clock signal and the initial delay setting in response to the power-on signal.

[0025] In an example embodiment of the present application, the operation of obtaining the offset between the data trigger signal and the clock signal at the target volatile memory module includes obtaining a plurality of candidate offsets between the data trigger signal and the clock signal at the target volatile memory module, and performing statistical operation on the plurality of candidate offsets to obtain the offset.

[0026] Based on the above, after generating the clock signal and the data trigger signal according to the internal clock signal, the clock signal and the data trigger signal can be transmitted to the target volatile memory module through a first signal path and a second signal path, respectively. After obtaining the offset between the data trigger signal and the clock signal at the target volatile memory module, if the offset is greater than a threshold value, an initial delay setting of the data trigger signal can be stored according to delay information of the data trigger signal. In this way, the problem of timing skew between the clock signal and the data trigger signal generated when performing signal correction on the data trigger signal later can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic diagram of a memory storage device according to an example embodiment of the present application;

[0028] Figure 2is a signal timing diagram of clock signals and data strobe signals at the ends of a volatile memory module according to an example embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present invention;

[0031] Figure 5 is a flowchart of a signal correction method according to an example embodiment of the present invention;

[0032] Figure 6 is a flowchart of a signal correction method according to an example embodiment of the present invention. DETAILED DESCRIPTION

[0033] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0034] A number of exemplary embodiments are presented herein to illustrate the present invention, however the present invention is not limited to the exemplary embodiments presented. Also, appropriate combinations of the exemplary embodiments are allowed. The word "connected" used throughout the present specification, including the claims, can refer to any direct or indirect connection. For example, if a first device is described as being connected to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. In addition, the word "signal" can refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

[0035] Figure 1 is a schematic diagram of a memory storage device according to an example embodiment of the present invention. Referring to Figure 1 , the memory storage device 10 includes a memory control circuit unit 11 and volatile memory modules 12(1) - 12(4). It should be noted that the total number of volatile memory modules 12(1) - 12(4) can be more or less, and the present invention is not limited thereto.

[0036] The memory control circuit unit 11 can be configured to control and access the volatile memory modules 12(1) - 12(4). For example, the memory control circuit unit 11 can include a central processing unit (CPU), or other programmable general purpose or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or a combination of such devices.

[0037] The volatile memory modules 12(1) - 12(4) can be configured to temporarily store data. For example, the volatile memory modules 12(1) - 12(4) can include Double Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate 4 (DDR4) SDRAM, Double Data Rate 5 (DDR5) SDRAM, or other types of volatile memory. The memory control circuit unit 11 can store data into or read data from the volatile memory modules 12(1) - 12(4).

[0038] The memory control circuit unit 11 can include a memory interface circuit 111 and a memory controller 112. The memory interface circuit 111 can be configured to connect to the volatile memory modules 12(1) - 12(4). For example, the memory interface circuit 111 can communicate with the volatile memory modules 12(1) - 12(4) through a Peripheral Component Interconnect Express (PCI Express) standard or other types of connection interface standards.

[0039] The memory controller 112 is connected to the memory interface circuit 111. The memory controller 112 can perform access operations to the volatile memory modules 12(1)~12(4) through the memory interface circuit 111. For example, the access operations can include data read operations and data write operations. The data read operations are used to read data from the volatile memory modules 12(1)~12(4). The data write operations are used to write (i.e., store) data into the volatile memory modules 12(1)~12(4). In an example embodiment, the memory controller 112 is also referred to as a dynamic random access memory controller (SRAM controller). In addition, the memory controller 112 can be responsible for overall or partial operations of the memory control circuit unit 11.

[0040] The memory interface circuit 111 can be connected to the volatile memory modules 12(1)~12(4) in a fly-by manner through a signal path (also referred to as a first signal path) 101. That is, signals transmitted on the signal path 101 share a channel and sequentially reach the volatile memory modules 12(1)~12(4). In addition, the memory interface circuit 111 can be connected to the volatile memory modules 12(1)~12(4) in parallel through signal paths (also referred to as second signal paths) 102(1)~102(4). That is, signals transmitted on the signal paths 102(1)~102(4) can be transmitted between the memory control circuit unit 11 and the volatile memory modules 12(1)~12(4) through respective independent channels. However, the manner in which the signal paths 101 and 102(1)~102(4) are arranged can also be adjusted according to practical needs, and the present application is not limited in this regard.

[0041] It should be noted that the signal path 101 is a unidirectional signal transmission path. That is, the memory control circuit unit 11 can transmit signals to the volatile memory modules 12(1)~12(4) through the signal path 101. The signal paths 102(1)~102(4) are all bidirectional signal transmission paths. For example, when writing data to the volatile memory module 12(i), the memory control circuit unit 11 can transmit signals to the volatile memory module 12(i) through the signal path 102(i). Alternatively, when reading data from the volatile memory module 12(i), the memory control circuit unit 11 can receive signals from the volatile memory module 12(i) through the signal path 102(i).

[0042] The signal path 101 can be used to transmit a signal (also referred to as a clock signal) CLK to the volatile memory modules 12(1) - 12(4). The signal CLK can be used to synchronize a clock (also referred to as a system clock) of the memory control circuit unit 11 to the volatile memory modules 12(1) - 12(4). In addition, the signal path 101 can also be used to transmit a signal (also referred to as a command signal) CMD and a signal (also referred to as an address signal) ADD to the volatile memory modules 12(1) - 12(4). The signal CMD can be used to transmit information of an access command desired to be executed by the memory controller 112 to the volatile memory modules 12(1) - 12(4). The signal ADD can be used to transmit information of a memory address desired to be accessed by the memory controller 112 to the volatile memory modules 12(1) - 12(4). In addition, the signal path 101 can also be used to transmit other types of signals, which are not limited by the present application.

[0043] The signal paths 102(1) - 102(4) can be used to transmit signals (also referred to as data trigger signals) DQS(1) - DQS(4) to the volatile memory modules 12(1) - 12(4), respectively. In addition, the signal paths 102(1) - 102(4) can also be used to transmit signals (also referred to as data signals) DQ(1) - DQ(4) to the volatile memory modules 12(1) - 12(4), respectively. Herein, the signals DQS(i) and DQ(i) are matched with each other. For example, the signal DQS(i) can be used to sample the signal DQ(i) to obtain data carried by the signal DQ(i).

[0044] Taking the signal path 102(i) as an example, when data is desired to be stored to the volatile memory module 12(i), the memory interface circuit 111 can transmit the signals CLK, CMD and ADD to the volatile memory module 12(i) through the signal path 101 and transmit the signals DQS(i) and DQ(i) to the volatile memory module 12(i) through the signal path 102(i). According to the signals received through the signal paths 101 and 102, the volatile memory module 12(i) can perform a corresponding data write operation. The data write operation can be used to store data desired to be stored by the memory controller 112 in the volatile memory module 12(i). In particular, in the data write operation, the volatile memory module 12(i) can use the signal DQS(i) to sample the signal DQ(i) to obtain the data desired to be stored by the memory controller 112.

[0045] On the other hand, when data is to be read from the volatile memory module 12(i), the memory interface circuit 111 can transmit the signals CLK, CMD and ADD to the volatile memory module 12(i) through the signal path 101. According to the signals received through the signal path 101, the volatile memory module 12(i) can perform a corresponding data read operation. This data read operation can be used to read out data desired to be read by the memory controller 112 from the volatile memory module 12(i). Then, the volatile memory module 12(i) can transmit the signals DQS(i) and DQ(i) to the memory interface circuit 111 through the signal path 102(i). The memory interface circuit 111 can use the signal DQS(i) to sample the signal DQ(i) to obtain the data desired to be read by the memory controller 112.

[0046] In an example embodiment, the memory interface circuit 111 can generate the signal CLK and the signal DQS(i) according to an internal signal (also referred to as an internal clock signal). The memory interface circuit 111 can transmit the signal CLK and the signal DQS(i) to the volatile memory module (also referred to as a target volatile memory module) 12(i) through the signal path 101 and the signal path 102(i), respectively.

[0047] In an example embodiment, the memory control circuit unit 11 further includes a control circuit (also referred to as an offset control circuit) 113. The control circuit 113 can be connected to the memory interface circuit 111. For example, the control circuit 113 can be disposed in the memory controller 112 (as shown), in the memory interface circuit 111, or independent of the memory interface circuit 111 and the memory controller 112. For example, the control circuit 113 can include a microprocessor, an embedded controller (EC) or other similar devices. In an example embodiment, the control circuit 113 can also be implemented by software or firmware, without limitation of the present application. Figure 1

[0048] The control circuit 113 can obtain an offset between the signal DQS(i) at the volatile memory module 12(i) and the signal CLK. For example, the offset can reflect a phase difference or a frequency difference between the signal DQS(i) at the volatile memory module 12(i) and the signal CLK. It should be noted that how to obtain the offset between the signal DQS(i) at the volatile memory module 12(i) and the signal CLK is a prior art, for example, the signal DQS(i) and / or CLK can be sampled at the volatile memory module 12(i) by a high frequency signal to obtain the respective transition point positions of the signal DQS(i) and CLK, and the like, which will not be described in more detail herein.

[0049] ​The control circuit 113 can determine whether the offset is greater than a threshold. In response to the offset being greater than the threshold, the control circuit 113 can store (e.g., update) the initial delay setting of the signal DQS(i) according to the delay information of the signal DQS(i). For example, the delay information of the signal DQS(i) can reflect the current delay status of the signal DQS(i). Thereafter, the memory interface circuit 111 can regenerate the signal DQS(i) having the same delay status according to the initial delay setting. On the other hand, in response to the offset being not greater than (e.g., less than or equal to) the threshold, the control circuit 113 can discard (i.e., not store) the delay information of the signal DQS(i).

[0050] In an example embodiment, after storing the initial delay setting, the memory interface circuit 111 can regenerate the signal DQS(i) according to the internal clock signal and the initial delay setting. It is noted that the initial delay setting is stored according to the signal DQS(i) having an offset between the volatile memory module 12(i) and the signal CLK being greater than a threshold, so the regenerated signal DQS(i) can also theoretically have an offset between the volatile memory module 12(i) and the signal CLK being greater than the threshold. The memory interface circuit 111 can adjust the delay of the signal according to the regenerated signal DQS(i) to align the signal DQS(i) with the signal CLK at the volatile memory module 12(i). For example, the alignment can refer to the rising edge of the signal DQS(i) being aligned with the rising edge of the signal CLK, the falling edge of the signal DQS(i) being aligned with the falling edge of the signal CLK, or other alignment manners, depending on practical requirements. In an example embodiment, the operation of adjusting the delay of the signal according to the regenerated signal DQS(i) to align the signal DQS(i) with the signal CLK at the volatile memory module 12(i) can also be referred to as write leveling. It is noted that write leveling is prior art in the related technical field, so it is not described in detail herein.

[0051] In an example embodiment, by using the initial delay setting to generate the signal DQS(i) performing write leveling, it can be ensured that the offset between the signal DQS(i) and the signal CLK at the volatile memory module 12(i) is greater than (or not less than) the threshold in the initial stage of write leveling. Thus, after locking the signals CLK and DQS(i) by performing write leveling, the probability of timing disorder (e.g., locking the T(0)th pulse in the signal CLK to the T(l)th pulse in the signal DQS(i)) between the locked signals CLK and DQS(i) can be reduced.

[0052] In an example embodiment, the memory interface circuit 111 can detect a power-on signal. For example, the power-on signal can be automatically generated each time the memory storage device 10 is powered on or powered up. The memory interface circuit 111 can generate the signal DQS(i) according to the initial delay setting in response to the power-on signal and the internal clock signal. Then, the memory interface circuit 111 can perform write leveling at the end of the volatile memory module 12(i) based on the signal DQS(i) generated according to the initial delay setting, so that the signal DQS(i) is aligned with the signal CLK at the end of the volatile memory module 12(i).

[0053] In an example embodiment, the control circuit 113 can obtain a plurality of offsets (also referred to as candidate offsets) between the signal DQS(i) and the signal CLK at the end of the volatile memory module 12(i). Each of the candidate offsets can be different due to noise or jitter in the channel at different time points. The memory controller 112 can perform statistical operations on the candidate offsets to obtain the offset to be finally compared with the threshold. In this way, the statistical data of the offset can be obtained for the currently used signal DQS(i) in a more objective manner and with a higher tolerance for errors, and then the statistical data is used to determine whether to store the initial delay setting according to the delay information of the signal DQS(i). Details have been described above and will not be repeated here.

[0054] Figure 2 is a signal timing diagram of the clock signal and the data trigger signal at the end of the volatile memory module according to an example embodiment of the present application. Please refer to Figure 1 and Figure 2 , it is assumed that the signal DQS(i) includes the signals DQS_SEL(1) to DQS_SEL(4). The signals CLK and DQS_SEL(1) to DQS_SEL(4) can be generated according to the internal clock signal. In particular, the phases of the signals DQS_SEL(1) to DQS_SEL(4) are different from each other. In addition, the total number of the signals DQS_SEL(1) to DQS_SEL(4) can be more or less, which is not limited by the present application.

[0055] In an example embodiment, the memory interface circuit 111 can increase the amount of delay of one of the signals DQS_SEL(l)-DQS_SEL(4) by m delay time units to generate another one of the signals DQS_SEL(l)-DQS_SEL(4). The delay time unit can correspond to 1 / n of one clock period of the signal DQS(i), where m and n are positive integers. For example, assuming n is 4, the memory interface circuit 111 can increase the amount of delay of the signal DQS_SEL(l) by 1-3 delay time units to generate the signals DQS_SEL(2)-DQS_SEL(4), respectively. The phases of the signals DQS_SEL(l)-DQS_SEL(4) can differ from each other by 90 degrees (corresponding to 1 / 4 of a clock period) or other degrees.

[0056] In an example embodiment, the memory interface circuit 111 can transmit one of the signals DQS_SEL(l)-DQS_SEL(4) to the volatile memory module 12(i). The memory controller 112 can determine whether the offset between the one of the signals DQS_SEL(l)-DQS_SEL(4) and the signal CLK at the volatile memory module 12(i) is greater than a threshold value. In response to the offset (also referred to as a first offset) between the one of the signals DQS_SEL(l)-DQS_SEL(4) (e.g., the signal DQS_SEL(j)) and the signal CLK at the volatile memory module 12(i) not being greater than the threshold value, the memory controller 112 can discard (i.e., not store) the delay information of the signal DQS_SEL(i). For example, the delay information of the signal DQS_SEL(i) can reflect the delay state of the signal DQS_SEL(i). Alternatively, in response to the offset (also referred to as a second offset) between the one of the signals DQS_SEL(l)-DQS_SEL(4) (e.g., the signal DQS_SEL(k)) and the signal CLK at the volatile memory module 12(i) being greater than the threshold value, the memory controller 112 can store the delay information of the signal DQS_SEL(k) as the initial delay setting of the signal DQS(i). For example, the delay information of the signal DQS_SEL(k) can reflect the delay state of the signal DQS_SEL(k). k is different from i.

[0057] In an example embodiment, the memory interface circuit 111 can increase the amount of delay of one of the signals DQS_SEL(l)-DQS_SEL(4) by m delay time units to generate another one of the signals DQS_SEL(l)-DQS_SEL(4). The delay time unit can correspond to 1 / n of one clock period of the signal DQS(i), where m and n are positive integers. For example, assuming n is 4, the memory interface circuit 111 can increase the amount of delay of the signal DQS_SEL(l) by 1-3 delay time units to generate the signals DQS_SEL(2)-DQS_SEL(4), respectively. The phases of the signals DQS_SEL(l)-DQS_SEL(4) can differ from each other by 90 degrees (corresponding to 1 / 4 of a clock period) or other degrees. Figure 2For example, the signal DQS_SEL(j) can include the signal DQS_SEL(1) and DQS_SEL(2). For example, the rising edges of the signal DQS_SEL(1) and DQS_SEL(2) are both within the filtering region GP. For example, the boundaries 201 and 202 of the filtering region GP are defined with respect to the rising edge of the signal CLK. For example, the boundaries 201 and 202 of the filtering region GP are obtained by extending one time unit to the left and right of the rising edge of the signal CLK, respectively. It should be noted that the width of the filtering region GP (i.e., the distance between the boundaries 201 and 202) can also be adjusted according to practical needs, and the present application is not limited thereto.

[0058] In an example embodiment, the rising edge of the signal DQS_SEL(i) is within the filtering region GP, which indicates that the boundary of the signal DQS_SEL(i) is relatively close to the boundary of the signal CLK. Therefore, if the signal DQS_SEL(i) is subsequently used as the signal DQS(i) to perform write leveling (i.e., phase correction) with the signal CLK, timing errors between the locked signal CLK and DQS(i) are likely to occur. In an example embodiment, by excluding the signal DQS_SEL(i), the probability of timing errors between the locked signal CLK and DQS(i) can be reduced.

[0059] In an example embodiment, the signal DQS_SEL(k) can include the signal DQS_SEL(3) and DQS_SEL(4). For example, the rising edges of the signal DQS_SEL(3) and DQS_SEL(4) are both not within the filtering region GP.

[0060] In an example embodiment, the rising edge of the signal DQS_SEL(k) is not within the filtering region GP, which indicates that the boundary of the signal DQS_SEL(k) is relatively far away from the boundary of the signal CLK. Therefore, if the signal DQS_SEL(k) is subsequently used as the signal DQS(i) to perform write leveling with the signal CLK, the probability of timing errors between the locked signal CLK and DQS(i) can be reduced. In an example embodiment, by selecting the signal DQS_SEL(k) as the signal DQS(i) to perform write leveling, the probability of timing errors between the locked signal CLK and DQS(i) can be reduced.

[0061] In an example embodiment, the memory interface circuit 111 can first transmit the signal DQS_SEL(i) to the volatile memory module 12(i). After determining that the first offset is not greater than the threshold value, the memory interface circuit 111 can generate the signal DQS_SEL(k) and transmit the signal DQS_SEL(k) to the volatile memory module 12(i), and so on until a suitable signal DQS_SEL(k) is found.

[0062] Figure 3 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application. Please refer to Figure 3 , the memory control circuit unit 31 can be the same as or similar to the memory control circuit unit 11 of Figure 1 . The memory control circuit unit 31 can include a memory interface circuit 311, a memory controller 312, and a control circuit 313. The memory interface circuit 311, the memory controller 312, and the control circuit 313 can be the same as or similar to the memory interface circuit 111, the memory controller 112, and the control circuit 113 of Figure 1 , respectively.

[0063] The memory interface circuit 311 can include an internal clock generator 32, a clock path circuit 33, a register 34, and a write path circuit 35. The internal clock generator 32 is connected to the clock path circuit 33 and the write path circuit 35. The register 34 is connected to the write path circuit 35. In addition, the memory interface circuit 311 can also have various electronic circuit elements such as a read path circuit and a multiplexer, which are not limited by the present application.

[0064] The internal clock generator 32 can be used to generate a signal (i.e., an internal clock signal) ICK. The clock path circuit 33 can generate a signal CLK according to the signal ICK. The signal CLK can be transmitted to the volatile memory module 12(i). The register 34 can be used to store an initial delay setting of the signal DQS(i). The write path circuit 35 can generate the signal DQS(i) with a specific delay state according to the signal ICK and the initial delay setting in the register 34. Then, the signal DQS(i) can be transmitted to the volatile memory module 12(i). Thereafter, the write leveling at the end of the volatile memory module 12(i) can be performed according to this signal DQS(i). The relevant details have been described above and will not be repeated here.

[0065] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present application. Please refer to Figure 4 , the memory storage device 40 includes a connection interface unit 41, a memory control circuit unit 42, a rewritable non-volatile memory module 43, and a volatile memory module 44.

[0066] The connection interface unit 41 is used to connect the memory storage device 40 to a host system. The memory storage device 40 can communicate with the host system through the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compliant with the PCI Express standard. In an example embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that contains the memory control circuit unit 42.

[0067] The memory control circuit unit 42 is connected to the connection interface unit 41, the rewritable nonvolatile memory module 43, and the volatile memory module 44. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 43 according to instructions of the host system. In addition, the memory control circuit unit 42 can include the memory control circuit unit 11 of Figure 1 or the memory control circuit unit 31 of Figure 3 .

[0068] The rewritable non-volatile memory module 43 is used to store data written by the host system. For example, the rewritable non-volatile memory module 43 can include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store 1 bit), a Multi Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store 2 bits), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store 3 bits), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store 4 bits), other flash memory modules, or other memory modules having the same characteristics.

[0069] Each storage cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". As the threshold voltage changes, each storage cell in the rewritable non-volatile memory module 43 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, thereby obtaining one or more bits stored in the storage cell.

[0070] In an example embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute a plurality of physical programming units, and the physical programming units can constitute a plurality of physical erase units. Specifically, the memory cells on the same word line can form one or more physical programming units. If one memory cell can store more than two bits, the physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical programming unit is greater than that of an upper physical programming unit, and / or the reliability of a lower physical programming unit is higher than that of an upper physical programming unit.

[0071] In an example embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit of writing data. For example, a physical programming unit can be a physical page or a physical sector. If a physical programming unit is a physical page, the physical programming units can include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In an example embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can include 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erase unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block.

[0072] The volatile memory module 44 is used to store data in a volatile manner. For example, the volatile memory module 44 can include the volatile memory modules 12(1) to 12(4) of FIG. 1. In addition, the total number of the volatile memory modules 44 can be greater or smaller. Figure 1

[0073] Figure 5 is a flowchart of a signal correction method according to an example embodiment of the present application. Please refer to FIG. 1 for the details of the components in the flowchart. Figure 5 ​In step S501, a clock signal and a data trigger signal are generated according to an internal clock signal. In step S502, the clock signal and the data trigger signal are transmitted to a target volatile memory module among a plurality of volatile memory modules through a first signal path and a second signal path, respectively. In step S503, an offset between the data trigger signal and the clock signal at the target volatile memory module is obtained. In step S504, in response to the offset being greater than a threshold value, an initial delay setting of the data trigger signal is stored according to delay information of the data trigger signal.

[0074] Figure 6 A flowchart of a signal correction method according to an example embodiment of the present application is shown. Please refer to Figure 6 In step S601, a memory storage device is powered on (e.g., booting or waking up). In step S602, a data trigger signal is generated according to an internal clock signal and an initial delay setting. In step S603, a delay of the data trigger signal is adjusted according to the clock signal to align the data trigger signal with the clock signal at the target volatile memory module.

[0075] However, Figure 5 The steps in Figure 6 have been described above and will not be repeated here. It is worth noting that Figure 5 The steps in Figure 6 may be implemented as a plurality of program codes or circuits, and the present application is not limited in this regard. In addition, Figure 5 The method of Figure 6 may be used in combination with the above example embodiments or may be used alone, and the present application is not limited in this regard.

[0076] In summary, the signal correction method, the memory storage device, and the memory control circuit unit provided by the embodiments of the present application can store an initial delay setting of a data trigger signal for different volatile memory modules. In particular, the offset between the data trigger signal generated according to the initial delay setting and a clock signal at a volatile memory module will be greater than a threshold value. Thus, after performing write leveling on the data trigger signal, the probability of timing errors between the locked clock signal and the data trigger signal can be reduced.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal calibration method, characterized in that, For a memory storage device, the memory storage device including multiple volatile memory modules, the signal calibration method includes: The clock signal and data trigger signal are generated based on the internal clock signal; The clock signal and the data trigger signal are transmitted to the target volatile memory module among the plurality of volatile memory modules through the first signal path and the second signal path, respectively. Obtain the offset between the data trigger signal at the target volatile memory module and the clock signal; and In response to the offset being greater than a threshold, the initial delay setting of the data trigger signal is stored based on the delay information of the data trigger signal at the time the offset is greater than the threshold, wherein the initial delay setting is used to regenerate the data trigger signal.

2. The signal calibration method according to claim 1, wherein the data trigger signal includes a first data trigger signal and a second data trigger signal, the first data trigger signal having a first offset between the target volatile memory module and the clock signal that is not greater than the critical value, the second data trigger signal having a second offset between the target volatile memory module and the clock signal that is greater than the critical value, and the step of storing the initial delay setting of the data trigger signal according to the delay information of the data trigger signal in response to the offset being greater than the critical value includes: In response to the second offset being greater than the threshold value, the initial delay setting of the data trigger signal is stored according to the delay information of the second data trigger signal.

3. The signal calibration method according to claim 2 further includes: In response to the first offset not being greater than the threshold value, the delay information of the first data trigger signal is discarded.

4. The signal calibration method according to claim 2, further comprising: The delay of the first data trigger signal is increased by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of one clock cycle of the data trigger signal, where m and n are both positive integers.

5. The signal calibration method according to claim 1, further comprising: After storing the initial delay setting, the data trigger signal is generated based on the internal clock signal and the initial delay setting; as well as The delay of the data trigger signal is adjusted according to the clock signal to align the data trigger signal with the clock signal at the target volatile memory module.

6. The signal calibration method according to claim 5, wherein the step of generating the data trigger signal based on the internal clock signal and the initial delay setting includes: Detect the power-on signal; as well as In response to the power-on signal, the data trigger signal is generated based on the internal clock signal and the initial delay setting.

7. The signal calibration method according to claim 1, wherein the step of obtaining the offset between the data trigger signal at the target volatile memory module and the clock signal includes: Obtain multiple candidate offsets between the data trigger signal at the target volatile memory module and the clock signal; as well as The offset is obtained by performing statistical calculations on the multiple candidate offsets.

8. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; Rewritable non-volatile memory module; Multiple volatile memory modules; as well as The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module, and the plurality of volatile memory modules. The memory control circuit unit is used to: The clock signal and data trigger signal are generated based on the internal clock signal; The clock signal and the data trigger signal are transmitted to the target volatile memory module among the plurality of volatile memory modules through the first signal path and the second signal path, respectively. Obtain the offset between the data trigger signal at the target volatile memory module and the clock signal; as well as In response to the offset being greater than a threshold, the initial delay setting of the data trigger signal is stored based on the delay information of the data trigger signal at the time the offset is greater than the threshold, wherein the initial delay setting is used to regenerate the data trigger signal.

9. The memory storage device according to claim 8, wherein the data trigger signal includes a first data trigger signal and a second data trigger signal, the first data trigger signal having a first offset between the target volatile memory module and the clock signal not greater than the threshold value, the second data trigger signal having a second offset between the target volatile memory module and the clock signal greater than the threshold value, and the memory control circuit unit, in response to the offset being greater than the threshold value, storing the initial delay setting of the data trigger signal according to the delay information of the data trigger signal includes: In response to the second offset being greater than the threshold value, the initial delay setting of the data trigger signal is stored according to the delay information of the second data trigger signal.

10. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: In response to the first offset not being greater than the threshold value, the delay information of the first data trigger signal is discarded.

11. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: The delay of the first data trigger signal is increased by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of one clock cycle of the data trigger signal, where m and n are both positive integers.

12. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: After storing the initial delay setting, the data trigger signal is generated based on the internal clock signal and the initial delay setting; and The delay of the data trigger signal is adjusted according to the clock signal to align the data trigger signal with the clock signal at the target volatile memory module.

13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit generating the data trigger signal according to the internal clock signal and the initial delay setting includes: Detect the power-on signal; as well as In response to the power-on signal, the data trigger signal is generated based on the internal clock signal and the initial delay setting.

14. The memory storage device of claim 8, wherein the operation of the memory control circuit unit obtaining the offset of the data trigger signal between the target volatile memory module and the clock signal comprises: Obtain multiple candidate offsets between the data trigger signal at the target volatile memory module and the clock signal; as well as The offset is obtained by performing statistical calculations on the multiple candidate offsets.

15. A memory control circuit unit, characterized in that, The memory control circuit unit, used to control multiple volatile memory modules, includes: Memory controller; Memory interface circuitry, connected to the memory controller and the plurality of volatile memory modules; and The control circuit is connected to the memory interface circuit. The memory interface circuit is used to generate clock signals and data trigger signals based on the internal clock signal. The memory interface circuit is also used to transmit the clock signal and the data trigger signal to the target volatile memory module among the plurality of volatile memory modules through the first signal path and the second signal path, respectively. The control circuit is used to obtain the offset between the data trigger signal at the target volatile memory module and the clock signal, and The control circuit is also configured to, in response to the offset being greater than a threshold, store an initial delay setting for the data trigger signal based on the delay information of the data trigger signal at the time the offset is greater than the threshold, wherein the initial delay setting is used to regenerate the data trigger signal.

16. The memory control circuit unit of claim 15, wherein the data trigger signal includes a first data trigger signal and a second data trigger signal, the first data trigger signal having a first offset between the target volatile memory module and the clock signal that is not greater than the threshold value, the second data trigger signal having a second offset between the target volatile memory module and the clock signal that is greater than the threshold value, and the operation of the control circuit storing the initial delay setting of the data trigger signal according to the delay information of the data trigger signal in response to the offset being greater than the threshold value includes: In response to the second offset being greater than the threshold value, the initial delay setting of the data trigger signal is stored according to the delay information of the second data trigger signal.

17. The memory control circuit unit according to claim 16, wherein the control circuit is further configured to: In response to the first offset not being greater than the threshold value, the delay information of the first data trigger signal is discarded.

18. The memory control circuit unit according to claim 16, wherein the memory interface circuit is further configured to: The delay of the first data trigger signal is increased by m delay time units to generate the second data trigger signal, and the delay time unit corresponds to 1 / n of one clock cycle of the data trigger signal, where m and n are both positive integers.

19. The memory control circuit unit according to claim 15, wherein the memory interface circuit is further configured to: After storing the initial delay setting, the data trigger signal is generated based on the internal clock signal and the initial delay setting; and The delay of the data trigger signal is adjusted according to the clock signal to align the data trigger signal with the clock signal at the target volatile memory module.

20. The memory control circuit unit of claim 19, wherein the operation of the memory interface circuit generating the data trigger signal according to the internal clock signal and the initial delay setting includes: Detect the power-on signal; as well as In response to the power-on signal, the data trigger signal is generated based on the internal clock signal and the initial delay setting.

21. The memory control circuit unit of claim 15, wherein the operation of the control circuit obtaining the offset between the data trigger signal at the target volatile memory module terminal and the clock signal includes: Obtain multiple candidate offsets between the data trigger signal at the target volatile memory module and the clock signal; as well as The offset is obtained by performing statistical calculations on the multiple candidate offsets.

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