Semiconductor memory device

Abstract

A semiconductor memory device includes an array of memory cells, a page buffer, and control logic. The array of memory cells includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells by a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external supply voltage terminal, and an internal operation circuit coupled to the first node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0086593, filed on July 1, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to electronic devices, and more specifically, to semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be formed in a two-dimensional structure (where strings are arranged horizontally on a semiconductor substrate) or a three-dimensional structure (where strings are stacked vertically on a semiconductor substrate). Three-dimensional memory devices are memory devices designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor memory device capable of preventing or delaying junction breakdown of transistors in a page buffer during an erase operation.

[0006] Another embodiment of this disclosure provides a semiconductor memory device capable of preventing or mitigating leakage current in the page buffer during programming operations.

[0007] According to one embodiment of this disclosure, a semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one of the plurality of memory cells via a bit line and is configured to store data in the at least one memory cell. The control logic controls the operation of the page buffer. The page buffer includes: a first transistor coupled between the bit line and a first node; a second transistor coupled between the bit line and an external power supply voltage terminal; and internal operating circuitry coupled to the first node. When a programming disable bias is transmitted to the bit line, the control logic controls the page buffer to transmit the programming disable bias from the internal operating circuitry to the bit line by turning on the first transistor and to disconnect the connection between the external power supply voltage terminal and the bit line by turning off the second transistor. Simultaneously with the programming disable bias being transmitted to the bit line, a first voltage greater than 0V is applied to the external power supply voltage terminal.

[0008] In one embodiment, the page buffer may further include a third transistor coupled between the first node and ground. While programming to prevent bias from being transmitted to the bit line, control logic can control the page buffer to disconnect the first node from ground by turning off the third transistor.

[0009] In one embodiment, the internal operating circuitry can receive a power supply voltage from the internal power supply voltage terminal and output a second voltage supplied by the internal power supply voltage terminal to the first node as a programmable disable bias voltage.

[0010] In one embodiment, the internal operating circuitry can receive a power supply voltage from the internal power supply voltage terminal and output a third voltage, generated based on a second voltage supplied from the internal power supply voltage terminal, to the first node as a programmable disable bias.

[0011] In one embodiment, the first voltage may be a voltage between 0.5V and 1V.

[0012] In one embodiment, the first transistor may be a high-voltage protection transistor.

[0013] In one embodiment, the internal operating circuitry may include: a fourth transistor coupled between a first node and a second node; a fifth transistor coupled between an internal power supply voltage and a third node; a sixth transistor coupled between the second node and the third node; a seventh transistor coupled between the third node and the fourth node; and an eighth transistor coupled between the second node and the fourth node.

[0014] According to another embodiment of this disclosure, a semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one of the plurality of memory cells via a bit line and is configured to erase data stored in the at least one memory cell. The control logic controls the operation of the page buffer. The page buffer includes: a first transistor coupled between the bit line and a first node; a second transistor coupled between the first node and ground; a third transistor coupled between the bit line and an external power supply voltage terminal; and internal operating circuitry coupled to the first node. When an erase bias is applied to the bit line, an erase voltage is applied to the external power supply voltage terminal. Furthermore, the control logic controls the page buffer to connect the external power supply voltage terminal and the bit line by turning on the third transistor, and applies a first voltage greater than 0V and less than the turn-on voltage to the gate of the first transistor.

[0015] In one embodiment, the control logic can control the page buffer to apply a turn-on voltage greater than the erase voltage to the gate of the third transistor.

[0016] In one embodiment, the first voltage may be between 1V and 2V.

[0017] In one embodiment, the first transistor may be a high-voltage protection transistor.

[0018] In one embodiment, while the erase bias is transmitted to the bit line, the control logic can control the page buffer to disconnect the first node from ground by turning off the second transistor.

[0019] In one embodiment, the internal operating circuitry may include: a fourth transistor coupled between a first node and a second node; a fifth transistor coupled between an internal power supply voltage and a third node; a sixth transistor coupled between the second node and the third node; a seventh transistor coupled between the third node and the fourth node; and an eighth transistor coupled between the second node and the fourth node.

[0020] In one embodiment, while the erase bias is transmitted to the bit line, the control logic can control the page buffer to disconnect the connection between the first node and the second node by turning off the fourth transistor.

[0021] This technology can provide a semiconductor memory device capable of preventing or delaying junction breakdown of transistors in the page buffer during erase operations.

[0022] Furthermore, this technology can provide a semiconductor memory device capable of preventing or mitigating leakage current in the page buffer during programming operations. Attached Figure Description

[0023] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Figure 2 It is a diagram. Figure 1 A block diagram of one embodiment of a memory cell array.

[0025] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks in the memory block.

[0026] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of any of the memory blocks in the memory blocks.

[0027] Figure 5 It is a diagram. Figure 1 A circuit diagram of an embodiment of any memory block included in the memory cell array.

[0028] Figure 6 The illustration shows an embodiment according to this disclosure. Figure 1 A circuit diagram of a page buffer included in a semiconductor memory device.

[0029] Figure 7 It is a diagram. Figure 6 A circuit diagram of one embodiment of the internal operating circuit.

[0030] Figure 8A This is a diagram illustrating the operation of a page buffer connected to a programmable string during programming operations of a semiconductor memory device according to an embodiment of the present disclosure.

[0031] Figure 8B This is a diagram illustrating the operation of a page buffer connected to a programming disable string during programming operations of a semiconductor memory device according to an embodiment of the present disclosure.

[0032] Figure 9 This is a diagram illustrating the operation of a page buffer during an erase operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0033] Figure 10 This is a diagram illustrating the operation of a page buffer connected to a programming disable string during programming operations of a semiconductor memory device according to another embodiment of the present disclosure.

[0034] Figure 11 This is a diagram illustrating the operation of a page buffer during an erase operation of a semiconductor memory device according to another embodiment of the present disclosure.

[0035] Figure 12 The illustration includes Figure 1 A block diagram of a semiconductor memory device's memory system.

[0036] Figure 13 It is a diagram. Figure 12 A block diagram of an application example of a memory system.

[0037] Figure 14 This is a block diagram illustrating a computing system, which includes a reference... Figure 13 The memory system described. Detailed Implementation

[0038] Specific structural or functional descriptions are provided in this specification or application to describe embodiments presented in accordance with the concepts of this disclosure. Embodiments may be implemented in various forms and should not be construed as an exhaustive representation of the teachings.

[0039] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] refer to Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, and a voltage generator 150.

[0041] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and can be configured using non-volatile memory cells with a vertical channel structure. Memory cell array 110 can be configured as a two-dimensional memory cell array. According to one embodiment, memory cell array 110 can be configured as a three-dimensional memory cell array. Furthermore, each memory cell among the multiple memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In another embodiment, each memory cell in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each memory cell in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to one embodiment, the memory cell array 110 may include a plurality of memory cells, each storing five or more bits of data.

[0042] The address decoder 120, read and write circuitry 130, and voltage generator 150 operate as peripheral circuitry driving the memory cell array 110. At this time, the peripheral circuitry operates under the control of control logic 140. The address decoder 120 is connected to the memory cell array 110 via word line WL. The address decoder 120 is configured to operate in response to the control logic 140. The address decoder 120 receives addresses through an input / output buffer (not shown) within the semiconductor memory device 100.

[0043] Address decoder 120 is configured to decode block addresses among received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read voltage application operation, address decoder 120 applies a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines. Similarly, during a program verification operation, address decoder 120 applies a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines.

[0044] Address decoder 120 is configured to decode the column address in the received address. Address decoder 120 transmits the decoded column address to read and write circuitry 130.

[0045] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0046] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0047] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, while continuously supplying sensing current to the bit lines connected to the memory cell, the multiple page buffers PB1 to PBm sense changes in the amount of current flowing according to the programming state of the corresponding memory cell through sensing nodes, and latch the sensed changes as sensed data. The read and write circuit 130 operates in response to page buffer control signals output from control logic 140.

[0048] During a read operation, the read and write circuit 130 senses data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include column select circuitry, etc.

[0049] Control logic 140 is connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals to adjust the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110. Control logic controls voltage generator 150 to generate various voltages used during programming operations of memory cell array 110. Furthermore, control logic 140 controls address decoder 120 to transmit the voltages generated by voltage generator 150 via global lines to local lines of the memory block targeted for operation. Simultaneously, during a read operation, control logic 140 controls read and write circuitry 130 to read data from the selected page of the memory block via bit lines BL1 to BLm, and stores the data in page buffers PB1 to PBm. Furthermore, during a programming operation, control logic 140 controls read and write circuitry 130 to program the data stored in page buffers PB1 to PBm into the selected page. Control logic 140 can be implemented in hardware, software, or a combination of both. For example, control logic 140 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0050] In response to a control signal output from control logic 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and in response to control by control logic 140, generate multiple voltages by selectively activating these multiple pump capacitors.

[0051] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on control logic 140.

[0052] Figure 2 It is a diagram. Figure 1 A block diagram of one embodiment of the memory cell array 110.

[0053] refer to Figure 2The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Reference) Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0054] Figure 3 It is a diagram. Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0055] refer to Figure 3 The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a 'U' shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 3 In this diagram, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it should be understood that three or more unit strings can be arranged in the column direction.

[0056] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0057] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In another embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the barrier insulating film.

[0058] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0059] In one embodiment, source-select transistors of cell strings arranged in the same row are connected to source-select lines extending in the row direction, and source-select transistors of cell strings arranged in different rows are connected to different source-select lines. Figure 3In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0060] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0061] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0062] The first memory cells MC1 to the nth memory cell MCn can be divided into: the first memory cells MC1 to the pth memory cells MCp, and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other through the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0063] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0064] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. The drain select transistors (DST) of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0065] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0066] A page is configured for memory cells connected to the same word line within a cell string arranged in the row direction. For example, memory cells in cell strings CS11 to CS1m in the first row, connected to the first word line WL1, are configured as one page. Memory cells in cell strings CS21 to CS2m in the second row, connected to the first word line WL1, are configured as another page. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0067] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0068] In one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. Providing more dummy memory cells improves the reliability of operation for memory block BLKa; however, it increases the size of memory block BLKa. Providing fewer dummy memory cells reduces the size of memory block BLKa, but may decrease the reliability of operation for memory block BLKa.

[0069] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0070] Figure 4 It is a diagram. Figure 2 A circuit diagram of another embodiment of memory block BLKb of any one of memory blocks BLK1 to BLKz.

[0071] refer to Figure 4The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes, stacked on a substrate (not shown) located below the memory block BLKb: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0072] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a single source select line.

[0073] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0074] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0075] In addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb represents the memory block with Figure 3 The circuitry is similar to that of the memory block BLKa.

[0076] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0077] In one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the reliability of operation for the memory block BLKb increases; however, the size of the memory block BLKb increases. With fewer dummy memory cells provided, the size of the memory block BLKb can be reduced, but the reliability of operation for the memory block BLKb may decrease.

[0078] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have a required threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0079] Figure 5 It is a diagram. Figure 1 A circuit diagram of an embodiment of any one of the memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0080] refer to Figure 5 The memory block BLKc comprises multiple cell strings CS1 to CSm. Each cell string CS1 to CSm can be connected to multiple bit lines BL1 to BLm. Each cell string CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0081] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In another embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the barrier insulating film.

[0082] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn.

[0083] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0084] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0085] Memory cells connected to the same word line are configured as a page. Cell strings CS1 to CSm can be selected by selecting the drain select line DSL. A page within the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0086] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. The even-numbered cell strings among the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0087] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured to have a three-dimensional structure. Furthermore, as... Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured to have a two-dimensional structure.

[0088] Figure 6 This is a circuit diagram illustrating a page buffer PB1 included in a semiconductor memory device 100 according to an embodiment of the present disclosure. Figure 6 The page buffer shown can also represent Figure 1 The read and write circuit 130 includes other page buffers PB2 to PBm. Because the multiple page buffers PB1 to PBm included in the read and write circuit 130 can be configured similarly to each other, any one of the page buffers is described as an example.

[0089] Page buffer PB1 is connected to the memory cell via bit line BL1. Page buffer PB1 may include: a first transistor TR1 connected between bit line BL1 and node NODE_A; a second transistor TR2 connected between node NODE_A and ground; a third transistor TR3 connected between bit line BL1 and external power supply voltage terminal VEXT; and internal operation circuitry 200 connected to node NODE_A. The first transistor TR1 can be controlled by a bit line selection signal SEL_BL and can be operated to selectively connect bit line BL1 and node NODE_A. The second transistor TR2 can be controlled by a bit line discharge signal BL_DIS and can be operated to selectively connect node NODE_A and ground. The third transistor TR3 is controlled by a bit line bias signal BL_BIAS and can be operated to selectively connect bit line BL1 and external power supply voltage terminal VEXT. The internal operation circuitry 200 can operate based on the internal power supply voltage VCORE.

[0090] The internal operation circuitry 200 can be configured to perform programming, reading, or erasing operations on memory cells connected to bit line BL1. The internal operation circuitry 200 can be designed in various ways as needed. References are given below. Figure 7 An internal operating circuit 200 according to one embodiment will be described.

[0091] Figure 7 It is a diagram. Figure 6 A circuit diagram of one embodiment of the internal operation circuit 200. The internal operation circuit 200 can operate in response to signals output from the control logic 140. The signals PB_SENSE, SA_PRECH_N, SA_SENSE, SA_CSOC, SA_DISCH, and PRECHSO_N, which will be described below, can be control signals output from the control logic 140. The internal operation circuit 200 is described in detail below.

[0092] refer to Figure 7 The internal operating circuit 200 is connected to node A, NODE_A. The internal operating circuit 200 can perform a bit line pre-charge operation, charging the bit line BL1 with charge supplied from the internal power supply voltage VCORE via first NMOS transistors N1 to N5 and first PMOS transistors P1 to P3. Furthermore, the internal operating circuit 200 can discharge the charge charged to bit line BL1 to ground voltage via first NMOS transistor N1, fourth NMOS transistor N4, and fifth NMOS transistor N5.

[0093] The first NMOS transistor N1 is connected between node A (NODE_A) and the common node CSO. The first PMOS transistor P1 is connected between the internal power supply voltage VCORE and the sense amplifier node SAN. The second NMOS transistor N2 is connected between the common node CSO and the sense amplifier node SAN. The second PMOS transistor P2 is connected between the sense amplifier node SAN and the sense node SO. The third NMOS transistor N3 is connected between the sense node SO and the common node CSO. The third PMOS transistor P3 is connected between the internal power supply voltage VCORE and the sense node SO. The fourth transistor N4 and the fifth transistor N5 are connected in series between the common node CSO and ground.

[0094] The first NMOS transistor N1 is controlled by the page buffer sensing signal PB_SENSE, the second NMOS transistor N2 is controlled by the current sensing signal SA_CSOC, and the third NMOS transistor N3 is controlled by the sense amplifier sensing signal SA_SENSE. Furthermore, the fourth NMOS transistor N4 is controlled by the sense amplifier discharge signal SA_DISCH, and the fifth NMOS transistor N5 and the first PMOS transistor P1 are controlled by the voltage of node QS of the sense latch circuit LATS. The second PMOS transistor P2 is controlled by the sense amplifier precharge signal SA_PRECH_N, and the third PMOS transistor P3 is controlled by the sense node precharge signal PRECHSO_N. That is, the page buffer sensing signal PB_SENSE is applied to the gate of the first NMOS transistor N1, the current sensing signal SA_CSOC is applied to the gate of the second NMOS transistor N2, and the sense amplifier sensing signal SA_SENSE is applied to the gate of the third NMOS transistor N3. Furthermore, the sense amplifier discharge signal SA_DISCH is applied to the gate of the fourth NMOS transistor N4, and the voltage of node QS of the sense latch circuit LATS is applied to the gate of the fifth NMOS transistor N5 and the gate of the first PMOS transistor P1. The sense amplifier precharge signal SA_PRECH_N is applied to the gate of the second PMOS transistor P2, and the sense node precharge signal PRECHSO_N is applied to the gate of the third PMOS transistor P3.

[0095] A sense latch circuit (LATS) may include a latch configured with two inverters connected to node QS; and a reset transistor and a set transistor that control the voltage of node QS. Because the structure of a sense latch circuit (LATS) is well known, Figure 7 Its specific configuration is omitted.

[0096] Although reference Figure 7The configuration of the internal operating circuitry 200 has been described, but this disclosure is not limited thereto. That is, with... Figure 7 Various internal operating circuits 200 with different configurations shown can be applied to this disclosure.

[0097] Figure 8A This is a diagram illustrating the operation of a page buffer connected to a programmable string during programming operations of a semiconductor memory device according to an embodiment of the present disclosure. Meanwhile, Figure 8B This is a diagram illustrating the operation of a page buffer connected to a programming disable string during programming operations of a semiconductor memory device according to an embodiment of the present disclosure.

[0098] During programming operations of the semiconductor memory device 100, a programming enable voltage can be applied to a bit line connected to a programming enable string, and a programming disable voltage can be applied to a bit line connected to a programming disable string. A programming enable string may refer to a string of memory cells that are among the memory cells selected as programming targets, where the memory cells whose programming is incomplete have a threshold voltage set to increase when a programming voltage is applied to a word line. A programming disable string may refer to a string of memory cells that are among the memory cells selected as programming targets, where the memory cells whose programming is complete have a threshold voltage not set to increase when a programming voltage is applied to a word line.

[0099] A programmable voltage can be applied to the bit line connected to the programmable string. The programmable voltage can be a relatively low voltage, and for example, it can be ground. When the cell string connected to the first bit line BL1 is a programmable string, the ground voltage needs to be transmitted to the first bit line BL1 as a programmable bias. Therefore, in this case, as... Figure 8A As shown, the on-voltage V ON This can be applied to the first transistor TR1 as a bit line select signal SEL_BL. Simultaneously, the on-state voltage V... ON The bit line discharge signal BL_DIS can be applied to the second transistor TR2. When both the first transistor TR1 and the second transistor TR2 are turned on, the ground voltage can be transmitted to the first bit line BL1 through the first transistor TR1 and the second transistor TR2. In this case, although Figure 8A Not shown, but can be turned off. Figure 7 The first NMOS transistor N1, therefore the voltage from the internal operating circuit 200 cannot be transmitted to node NODE_A.

[0100] In this configuration, 0V can be applied to the external power supply voltage terminal VEXT, and the 0V voltage can be applied to the third transistor TR3 as a bit line bias signal BL_BIAS. Therefore, the third transistor TR3 can be turned off.

[0101] A programming disable voltage can be applied to the bit line connected to the programming disable string. The programming disable voltage can be a relatively high voltage compared to the programming enable voltage. According to one embodiment of this disclosure, when the cell string connected to the first bit line BL1 is a programming disable string, the programming disable voltage can be transmitted from the internal operating circuitry 200 to the first bit line BL1. For example, the internal power supply voltage VCORE or the voltage generated therefrom needs to be transmitted to the first bit line BL1 as a programming disable bias. Therefore, in this case, as... Figure 8B As shown, the on-voltage V ON The bit line select signal SEL_BL can be applied to the first transistor TR1. Simultaneously, to prevent node A NODE_A from being connected to ground, the turn-off voltage V... OFF The bit line discharge signal BL_DIS can be applied to the second transistor TR2. The internal operation circuit 200 can be operated to transmit the internal power supply voltage VCORE, or the voltage generated therefrom, as a programming disable bias to node NODE_A. Therefore, the programming disable bias can be transmitted from the internal operation circuit 200 to the first bit line BL1 through the first transistor TR1.

[0102] In this case, with reference Figure 8A Similarly, 0V can be applied to the external power supply voltage terminal VEXT, and the 0V voltage can be applied to the third transistor TR3 as a bit line bias signal BL_BIAS. Therefore, the third transistor TR3 can be turned off.

[0103] like Figure 8B As shown, when the programming disable bias voltage is transmitted to the first bit line BL1, and a voltage of 0V is applied to the gate of the third transistor TR3 and 0V is applied to the source (i.e., the external power supply voltage terminal VEXT), a leakage current I may occur from the first bit line BL1 side to the third transistor TR3 side. LKG This can cause the potential connected to the first line BL1 of the programming disable string to not increase sufficiently, thus potentially causing programming perturbations.

[0104] Figure 9 This is a diagram illustrating the operation of a page buffer during an erase operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0105] During the erase operation of memory cells included in a memory block, erase characteristics can be improved by applying an erase bias voltage from the bit line side to the channel region and simultaneously applying an erase bias voltage from the common source line side to the channel region. To apply the erase bias voltage from the bit line BL1 side to the channel region, the erase voltage V can be received from the external power supply voltage terminal VEXT of the page buffer PB1. ERS Erasure voltage V ERS It can be a relatively large voltage, and can be greater than the internal power supply voltage VCORE. Therefore, in this case, the erase voltage V ERS It can be received from a separate external power supply voltage terminal VEXT, rather than from the internal operating circuit 200.

[0106] More specifically, see reference Figure 9 Erasure voltage V ERS It can be applied to the external power supply voltage terminal VEXT and the voltage V is turned on. ON This can be applied to the third transistor TR3 as a bit line bias signal BL_BIAS. In this case, the turn-on voltage V... ON It can be higher than the erase voltage V ERS The voltage. For example, the turn-on voltage V applied to the third transistor TR3. ON It can be compared to the erase voltage V ERS The voltage is approximately 2V to 4V. Therefore, the third transistor TR3 can be turned on. Consequently, the erase voltage V received from the external power supply voltage terminal VEXT... ERS It can be transmitted to the first bit line BL1 through the third transistor TR3.

[0107] At the same time, to prevent the connection between the first line BL1 and node NODE_A, the turn-off voltage V is used. OFF It can be applied to the first transistor TR1 as a bit line select signal SEL_BL. Meanwhile, in Figure 9 In the example, the turn-off voltage V OFF The bit line discharge signal BL_DIS is applied to the second transistor TR2, but the second transistor TR2 can be turned on.

[0108] The erase voltage V is a high voltage. ERS While being applied to the first bit line BL1, the first transistor TR1 can be configured as a high-voltage transistor to protect the internal operating circuit 200, which is primarily configured with low-voltage transistors. In this case, the first transistor TR1 can function as a high-voltage protection transistor. However, when a voltage of 0V is applied to the gate of the first transistor TR1, and serves as the high-voltage erase voltage V... ERSWhen the first line BL1, which serves as the source of the first transistor TR1, is applied, junction breakdown may occur due to gate-induced drain leakage (GIDL) current, depending on the voltage state of node NODE_A.

[0109] When summarizing Figure 8B and Figure 9 When the bit line bias conditions are respectively programming disabled and erased, the voltage conditions of the external power supply voltage terminal VEXT, the bit line bias signal BL_BIAS and the bit line selection signal SEL_BL can be summarized as shown in Table 1 below.

[0110] [Table 1]

[0111] BL bias conditions VEXT BL_BIAS SEL_BL Programming Prohibited 0V 0V <![CDATA[V ON ]]> erase <![CDATA[V ERS ]]> <![CDATA[V ERS +2V]]> 0V

[0112] However, when the voltage conditions shown in Table 1 are applied, as described above, during programmed disable operation, a leakage current I may occur from the first line BL1 side to the third transistor TR3 side. LKG Furthermore, during the erase operation, junction breakdown may occur in the first transistor TR1 due to GIDL current.

[0113] According to another embodiment of the semiconductor memory device and the method of operating the semiconductor memory device, when the bit line bias conditions are an erase state and a programmable disable state, the voltage conditions of the external power supply voltage terminal VEXT, the bit line bias signal BL_BIAS and the bit line select signal SEL_BL can be summarized as shown in Table 2 below.

[0114] [Table 2]

[0115] BL bias conditions VEXT BL_BIAS SEL_BL Programming Prohibited Va 0V <![CDATA[V ON ]]> erase <![CDATA[V ERS ]]> <![CDATA[V ERS +2V]]> Vb

[0116] In Table 2 above, the first voltage Va is a voltage greater than 0V, and the second voltage Vb is also a voltage greater than 0V. When the voltage conditions shown in Table 2 are applied, the leakage current I from the first line BL1 side to the third transistor TR3 side can be suppressed during programmed disable operation. LKG Furthermore, during the erase operation, junction breakdown due to GIDL current in the first transistor TR1 can be prevented. (Refer to the following text.) Figure 10 and Figure 11 This disclosure will be described in more detail.

[0117] Figure 10 This is a diagram illustrating the operation of a page buffer connected to a programming disable string during programming operations of a semiconductor memory device according to another embodiment of the present disclosure.

[0118] refer to Figure 10A programming disable voltage can be applied to the bit line connected to the programming disable string. The programming disable voltage can be a relatively high voltage compared to the programming enable voltage. When the cell string connected to the first bit line BL1 is a programming disable string, the programming disable voltage can be transferred from the internal operating circuit 200 to the first bit line BL1. For example, the internal power supply voltage VCORE, or the voltage generated therefrom, needs to be transferred to the first bit line BL1 as a programming disable bias. Therefore, in this case, as... Figure 10 As shown, the on-voltage V ON The bit line select signal SEL_BL can be applied to the first transistor TR1. Simultaneously, to prevent node A NODE_A from being connected to ground, the turn-off voltage V... OFF The bit line discharge signal BL_DIS can be applied to the second transistor TR2. The internal operation circuit 200 can be operated to transmit the internal power supply voltage VCORE, or the voltage generated therefrom, as a programming disable bias to node NODE_A. Therefore, the programming disable bias can be transmitted from the internal operation circuit 200 to the first bit line BL1 through the first transistor TR1.

[0119] Reference Figure 8B The situations described are different, according to Figure 10 In the illustrated embodiment, a first voltage Va greater than 0V can be applied to the external power supply voltage terminal VEXT, and a voltage of 0V can be applied to the third transistor TR3 as a bit line bias signal BL_BIAS. Therefore, the third transistor TR3 can be turned off.

[0120] according to Figure 10 As shown, while the programming disable bias voltage is transmitted to the first bit line BL1, a voltage of 0V is applied to the gate of the third transistor TR3, and a first voltage Va greater than 0V is applied to the source, i.e., the external power supply voltage terminal VEXT. The first voltage Va can be determined differently. For example, the first voltage Va can be a low voltage between 0.5V and 1V. In this case, leakage current I from the first bit line BL1 side to the third transistor TR3 side can be prevented. LKG Therefore, the potential of the first line BL1 connected to the programming disable string can be sufficiently increased without leakage current, and as a result, programming disturbances can be prevented.

[0121] Figure 11 This is a diagram illustrating the operation of a page buffer (shown as page buffer PB1) during an erase operation of a semiconductor memory device according to another embodiment of the present disclosure.

[0122] refer to Figure 11 Erasure voltage V ERSIt can be applied to the external power supply voltage terminal VEXT and the voltage V is turned on. ON This can be applied to the third transistor TR3 as a bit line bias signal BL_BIAS. In this case, the turn-on voltage V... ON It can be higher than the erase voltage V ERS The voltage. For example, the turn-on voltage V applied to the third transistor TR3. ON It can be compared to the erase voltage V ERS The voltage is approximately 2V to 4V. Therefore, the third transistor TR3 can be turned on. Consequently, the erase voltage V received from the external power supply voltage terminal VEXT... ERS It can be transmitted to the first bit line BL1 through the third transistor TR3.

[0123] At the same time, Figure 11 In this embodiment, a second voltage Vb greater than 0V can be applied to the first transistor TR1 as a bit line selection signal SEL_BL. Furthermore, the turn-off voltage V... OFF The bit line discharge signal BL_DIS is applied to the second transistor TR2 to disconnect the connection between node A NODE_A and ground.

[0124] The second voltage Vb can be greater than 0V but less than the on-state voltage V. ON For example, the second voltage Vb can be a low voltage between 1V and 2V. In this case, a voltage of 0V is applied to the gate of the first transistor TR1. Figure 9 Compared to the previous embodiment, the breakdown voltage is increased in the junction overlap region. That is, the possibility of junction breakdown can be reduced.

[0125] However, when the second voltage Vb is applied to the gate of the first transistor TR1, the first transistor TR1 can be weakly turned on. This means that node A NODE_A and the first bit line BL1 can be connected. However, because the second transistor TR2 is turned off, the connection between node A NODE_A and ground is broken. Furthermore, when the transistor connected to node A NODE_A in the internal operating circuit 200 (e.g., ...) Figure 7 When the first NMOS transistor (N1) is turned off, the connection between node A (NODE_A) and the internal operation circuit 200 is also cut off. Thus, the same effect as when the first transistor (TR1) is completely turned off can be achieved.

[0126] Figure 12 The illustration includes Figure 1 Block diagram of a semiconductor memory device 100 and a memory system 1000.

[0127] refer to Figure 12The memory system 1000 includes a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 The semiconductor memory device described. Repeated descriptions are omitted below.

[0128] Memory controller 1100 connects to a host computer and semiconductor memory device 100. Memory controller 1100 is configured to access semiconductor memory device 100 in response to requests from the host computer. For example, memory controller 1100 is configured to control read, write, erase, and background operations of semiconductor memory device 100. Memory controller 1100 is configured to provide an interface between semiconductor memory device 100 and the host computer. Memory controller 1100 is configured to drive firmware for controlling semiconductor memory device 100.

[0129] The memory controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: operating memory for the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the memory controller 1100. Furthermore, during write operations, the memory controller 1100 can temporarily store programming data provided by the host.

[0130] The host interface 1130 includes protocols for performing data exchange between the host and the memory controller 1100. As one embodiment, the memory controller 1100 is configured to communicate with the host via at least one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0131] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface 1140 includes a NAND interface or a NOR interface.

[0132] Error correction block 1150 is configured to detect and correct errors in data received from semiconductor memory device 100 using error correction codes (ECC). As an example, the error correction block may be provided as a component of memory controller 1100.

[0133] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As one embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as: a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), and universal flash storage (UFS).

[0134] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0135] As another example, the memory system 1000 is provided as one of a variety of components of an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, web tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3D TV, digital recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, and digital video player, device capable of transmitting and receiving information in a wireless environment, one of a variety of electronic devices for configuring a home network, one of a variety of electronic devices for configuring a computer network, one of a variety of electronic devices for configuring a telematics network, RFID device, or one of a variety of components for configuring a computing system.

[0136] As one embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in methods such as: stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processed stacked package (WSP).

[0137] Figure 13 It is a diagram. Figure 12 A block diagram of an application example of a memory system.

[0138] refer to Figure 13 The memory system 2000 includes a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0139] exist Figure 13 In this context, the multiple groups communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip is connected to a reference... Figure 1 The semiconductor memory chip of the semiconductor memory device 100 described is similarly configured and operated.

[0140] Each group is configured to communicate with the memory controller 2200 via a shared channel. The memory controller 2200 and the reference... Figure 12 The memory controller 1100 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0141] Figure 14 This is a block diagram of a computing system 3000, which includes a reference... Figure 13 The memory system described.

[0142] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0143] The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0144] exist Figure 14 In this configuration, semiconductor memory device 2100 is connected to system bus 3500 via memory controller 2200. However, semiconductor memory device 2100 can also be configured to be directly connected to system bus 3500. In this case, the functions of memory controller 2200 are performed by central processing unit 3100 and RAM 3200.

[0145] exist Figure 14 The reference is provided in the middle. Figure 13 The memory system 2000 is described. However, the memory system 2000 can be referenced from... Figure 12 The described memory system 1000 is replaced. As an embodiment, the computing system 3000 can be configured to include a reference... Figure 12 and Figure 13 Both memory systems 1000 and 2000 are described.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cells for storing data; A page buffer is coupled to at least one of the plurality of memory cells via a bit line and is configured to store data in the at least one memory cell. as well as The control logic is configured to control the operation of the page buffer. The page buffer mentioned above includes: A first transistor is coupled between the bit line and the first node; A second transistor is coupled between the bit line and an external power supply voltage terminal; and The internal operating circuitry is coupled to the first node. The control logic is configured as follows: When the programming disable bias is transmitted to the bit line, the page buffer is controlled to transmit the programming disable bias from the internal operating circuitry to the bit line by turning on the first transistor, and to disconnect the external power supply voltage terminal from the bit line by turning off the second transistor; and During programming, while the programming disable bias is transmitted to the bit line, a first voltage greater than 0V is applied to the external power supply voltage terminal to suppress leakage current from the bit line side to the second transistor side.

2. The semiconductor memory device according to claim 1, wherein: The page buffer further includes a third transistor coupled between the first node and ground; and The control logic is configured to, while the programming disable bias is transmitted to the bit line, control the page buffer to disconnect the connection between the first node and the ground by turning off the third transistor.

3. The semiconductor memory device of claim 1, wherein the internal operating circuitry is configured to: Receive power voltage from internal power supply voltage terminals; and The second voltage supplied by the internal power supply voltage terminal is output to the first node as the programming disable bias voltage.

4. The semiconductor memory device of claim 1, wherein the internal operating circuitry is configured to: Receive power voltage from internal power supply voltage terminals; and A third voltage, generated based on a second voltage supplied from the internal power supply voltage terminal, is output to the first node as the programming disable bias voltage.

5. The semiconductor memory device of claim 1, wherein the first voltage is between 0.5 volts and 1 volt.

6. The semiconductor memory device of claim 1, wherein the first transistor is a high-voltage protection transistor.

7. The semiconductor memory device of claim 1, wherein the internal operating circuitry comprises: The fourth transistor is coupled between the first node and the second node; The fifth transistor is coupled between the internal power supply voltage terminal and the third node; A sixth transistor is coupled between the second node and the third node; The seventh transistor is coupled between the third and fourth nodes; as well as The eighth transistor is coupled between the second node and the fourth node.

8. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cells for storing data; A page buffer is coupled to at least one of the plurality of memory cells via a bit line and is configured to erase data stored in the at least one memory cell; as well as The control logic is configured to control the operation of the page buffer. The page buffer mentioned above includes: A first transistor is coupled between the bit line and the first node; The second transistor is coupled between the first node and ground; A third transistor is coupled between the bit line and the external power supply voltage terminal; and The internal operating circuitry is coupled to the first node. The control logic is configured as follows: When an erase bias is applied to the bit line, an erase voltage is applied to the external power supply voltage terminal. Control the page buffer to connect the external power supply voltage terminal and the bit line by turning on the third transistor; and During the erase operation, while the erase voltage is applied to the bit line through the external power supply voltage terminal, a first voltage greater than 0V and less than the turn-on voltage is applied to the gate of the first transistor in order to increase the breakdown voltage in the junction overlap region of the first transistor.

9. The semiconductor memory device of claim 8, wherein the control logic is configured to control the page buffer to apply an on-state voltage greater than the erase voltage to the gate of the third transistor.

10. The semiconductor memory device of claim 8, wherein the first voltage is between 1 volt and 2 volts.

11. The semiconductor memory device of claim 8, wherein the first transistor is a high-voltage protection transistor.

12. The semiconductor memory device of claim 8, wherein the control logic is configured to: control the page buffer to disconnect the connection between the first node and the ground by turning off the second transistor while the erase bias is transmitted to the bit line.

13. The semiconductor memory device of claim 8, wherein the internal operating circuitry comprises: The fourth transistor is coupled between the first node and the second node; The fifth transistor is coupled between the internal power supply voltage terminal and the third node; A sixth transistor is coupled between the second node and the third node; The seventh transistor is coupled between the third and fourth nodes; as well as The eighth transistor is coupled between the second node and the fourth node.

14. The semiconductor memory device of claim 13, wherein the control logic is configured to: control the page buffer to disconnect the connection between the first node and the second node by turning off the fourth transistor while the erase bias is transmitted to the bit line.

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