A semiconductor structure and a method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor structure, comprising: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate; the first bonding structure comprises a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer comprises a first surface and a second surface arranged opposite to each other, the first surface of the first metal layer has a first groove, and the second metal layer is located in the first groove; the first conductive via is in contact with and connected to the second surface of the first metal layer, and the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer coincide.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Three-dimensional integrated circuits can improve packaging density, circuit operating speed, and realize new multifunctional devices and circuit systems. Currently, all semiconductor manufacturers are committed to the research of three-dimensional integrated circuits.

[0003] In a three-dimensional integrated circuit, bonding between wafers is involved. In the prior art, bonding between wafers is mainly achieved through copper-copper bonding.

[0004] However, the copper-copper bonding in the prior art is prone to failure, and the bonding performance needs to be improved. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the background technology.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] An embodiment of the present invention provides a semiconductor structure, comprising: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate; the first bonding structure comprises a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer comprises a first surface and a second surface arranged opposite to each other, the first surface of the first metal layer has a first groove, and the second metal layer is located in the first groove; the first conductive via is in contact with and connected to the second surface of the first metal layer, and the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer coincide.

[0008] In the above solution, the thickness of the second metal layer is smaller than the depth of the first groove.

[0009] In the above solution, the thickness of the second metal layer is less than 1 μm.

[0010] In the above solution, the second metal layer includes at least one material selected from the group consisting of bismuth, cadmium, tin, lead, dysprosium, and indium.

[0011] In the above solution, the first metal layer includes at least one material of copper or tungsten.

[0012] In the above solution, the shape of the bonding surface of the first bonding structure includes circular, elliptical, or rectangular.

[0013] In the above solution, the semiconductor structure further includes a second substrate, and a second bonding structure formed in the second substrate; the second bonding structure is bonded to the first bonding structure.

[0014] In the above solution, projections of the bonding surface of the first bonding structure and the bonding surface of the second bonding structure in the vertical direction overlap.

[0015] In the above solution, the second bonding structure includes a third metal layer made of the same material as the first metal layer, the third metal layer includes a first surface and a second surface arranged opposite to each other, and the first surface of the third metal layer is bonded to the first bonding structure.

[0016] In the above solution, the semiconductor structure further includes a second conductive via, the second conductive via is formed in the second substrate, and the second conductive via is in contact with and connected to the second surface of the third metal layer.

[0017] In the above solution, the second bonding structure includes a fourth metal layer made of the same material as the second metal layer; the first surface of the third metal layer has a second groove, and the fourth metal layer is located in the second groove.

[0018] In the above solution, projections of the second conductive through hole and the second groove in a direction perpendicular to the first surface of the third metal layer overlap.

[0019] In the above solution, the first surface of the third metal layer is concave, and the maximum depth of the concave is between 1-5 nm.

[0020] In the above solution, the first surface of the third metal layer is convex, and the maximum height of the convexity is between 1-5 nm.

[0021] In the above solution, the bonding surface of the first bonding structure is indented toward the first substrate by 1-5 nm to accommodate the first convex surface of the third metal layer.

[0022] An embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a first substrate; forming a first bonding structure and a first conductive via in the first substrate;

[0023] The first bonding structure includes a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, and the forming of the first bonding structure includes: forming the first metal layer, the first metal layer including a first surface and a second surface arranged opposite to each other; forming a first groove on the first surface of the first metal layer; and forming the second metal layer in the first groove;

[0024] The first conductive via is in contact with the second surface of the first metal layer, and projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer overlap.

[0025] In the above solution, the method further includes: providing a second substrate; forming a second bonding structure in the second substrate; and bonding the second bonding structure to the first bonding structure.

[0026] In the above solution, forming the second bonding structure includes: forming a third metal layer, the material of the third metal layer is the same as the material of the first metal layer, and the third metal layer includes a first surface and a second surface arranged opposite to each other.

[0027] In the above solution, bonding the second bonding structure to the first bonding structure comprises:

[0028] The first surface of the third metal layer is bonded to the bonding surface of the first bonding structure.

[0029] In the above solution, the method further includes: forming a second conductive via in the second substrate, wherein the second conductive via is in contact with and connected to the second surface of the third metal layer.

[0030] In the above solution, forming the second bonding structure also includes: forming a second groove on the first surface of the third metal layer, forming a fourth metal layer in the second groove, and the material of the fourth metal layer is the same as that of the second metal layer.

[0031] The semiconductor structure and the method for forming the same provided by the embodiment of the present invention, wherein the semiconductor structure comprises: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate; the first bonding structure comprises a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer comprises a first surface and a second surface arranged opposite to each other, the first surface of the first metal layer has a first groove, and the second metal layer is located in the first groove; the first conductive via is in contact with and connected to the second surface of the first metal layer, and the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer coincide. The first bonding structure comprises a second metal layer having a lower melting point, and compared with other bonding structures comprising only the first metal layer, the first bonding structure can be bonded at a lower temperature. At the same time, the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer overlap. During bonding, the first conductive via expands due to heat, which pushes the second metal layer in the first groove to fuse with other bonding structures to form an intermetallic compound. Therefore, even if there is a small gap between the first bonding structure and the other bonding structures, the first bonding structure and the other bonding structures can be smoothly fused, reducing the flatness requirements for the bonding surface during bonding.

[0032] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a semiconductor structure provided in the related art;

[0034] Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a second metal layer with a gap above it provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of bonding between a first bonding structure and a second bonding structure provided in an embodiment of the present invention;

[0037] Figure 5 A schematic diagram of a third metal layer provided in an embodiment of the present invention having a concave first surface;

[0038] Figure 6 A schematic diagram of a third metal layer provided in an embodiment of the present invention having a first convex surface;

[0039] Figure 7A flowchart of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0040] Figure 8a-8g A process flow chart of a method for forming a semiconductor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0043] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0045] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Figure 1 A schematic diagram of a semiconductor structure provided for related art, as shown in the figure, the semiconductor structure includes a first substrate 11, a first bonding structure 12 formed in the first substrate 11, a first conductive via 13 formed in the first substrate 11 and connected to the first bonding structure 12, a second substrate 21, a second bonding structure 22 formed in the second substrate 21, and a second conductive via 23 formed in the second substrate 21 and connected to the second bonding structure 22. The material of the first bonding structure 12 is copper, the material of the second bonding structure 22 is also copper, and the first bonding structure 12 and the second bonding structure 22 form a copper-copper bond.

[0048] However, copper-copper bonding requires mutual bonding at a high temperature of 400°C. The high bonding temperature limits the selection of many material processes and may cause component characteristic deviations. In addition, copper-copper bonding has high requirements for surface flatness, which increases the difficulty of process manufacturing.

[0049] Based on this, the following technical solutions of the embodiments of the present invention are proposed.

[0050] An embodiment of the present invention provides a semiconductor structure, comprising: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate; the first bonding structure comprises a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer comprises a first surface and a second surface arranged opposite to each other, the first surface of the first metal layer has a first groove, and the second metal layer is located in the first groove; the first conductive via is in contact with and connected to the second surface of the first metal layer, and the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer coincide.

[0051] The first bonding structure provided by the embodiment of the present invention includes a second metal layer with a lower melting point. Compared with other bonding structures including only the first metal layer, the first bonding structure provided by the embodiment of the present invention can be bonded at a lower temperature. At the same time, the projections of the first conductive via and the first groove in the direction perpendicular to the first surface of the first metal layer overlap. During bonding, the first conductive via expands due to heat, which will push the second metal layer in the first groove to fuse with other bonding structures to form an intermetallic compound. Therefore, even if there is a small gap between the first bonding structure and the other bonding structures, the first bonding structure and the other bonding structures can be smoothly fused, reducing the flatness requirements for the bonding surface during bonding.

[0052] In order to make the above-mentioned purposes, features and advantages of the present invention more clearly understood, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention.

[0053] Figure 2 A schematic diagram of a semiconductor structure provided for an embodiment of the present invention, as shown in the figure, the semiconductor structure includes a first substrate 11, and a first bonding structure 12 and a first conductive via 13 formed in the first substrate 11; the first bonding structure 12 includes a first metal layer 121 and a second metal layer 122, the melting point of the second metal layer 122 is lower than that of the first metal layer 121, the first metal layer 121 includes a first surface 121a and a second surface 121b arranged opposite to each other, the first surface 121a includes a first groove 121c, and the second metal layer 122 is located in the first groove 121c; the first conductive via 13 is in contact with the second surface 121b of the first metal layer 121, and the projections of the first conductive via 13 and the first groove 121c in a direction perpendicular to the first surface 121a of the first metal layer 121 coincide with each other.

[0054] It should be noted that the projections of the first conductive via 13 and the first groove 121c in the direction perpendicular to the first surface 121a of the first metal layer 121 overlap, that is, the cross section of the first conductive via 13 parallel to the first surface 121a and the cross section of the first groove 121c parallel to the first surface 121a have the same shape and size. In this way, the thermal expansion thrust of the first conductive via 13 on the molten second metal layer 122 during bonding can be increased, thereby improving the bonding reliability.

[0055] In a specific embodiment, the first conductive through hole 13 and the first groove 121 c are cylindrical, and the diameter of the first groove 121 c is the same as the diameter of the first conductive through hole 13 .

[0056] The first conductive via 13 includes but is not limited to a through silicon via (TSV), and the first conductive via 13 is used to transmit an electrical signal.

[0057] In a specific embodiment, the material of the first conductive via 13 is the same as that of the first metal layer 121 .

[0058] In a specific embodiment, the material of the first conductive via 13 includes but is not limited to copper. The material of the first substrate 11 can be silicon, germanium, gallium nitride, gallium arsenide, indium phosphide (InP), silicon on insulator (SOI), germanium on insulator (GeOI), etc., but is not limited thereto, and can also be other materials that can be used as a substrate.

[0059] The first conductive via 13 includes but is not limited to a through silicon via (TSV), and the first conductive via 13 is used to transmit an electrical signal.

[0060] In one embodiment, the first metal layer 121 includes but is not limited to at least one of copper and tungsten.

[0061] In one embodiment, the second metal layer 122 includes but is not limited to at least one of bismuth, cadmium, tin, lead, dysprosium, and indium.

[0062] The second metal layer 122 may completely fill the first groove 121c, or may partially fill the first groove 121c. Figure 3 As shown, in one embodiment, the thickness of the second metal layer 122 is less than the depth of the first groove 121c, in other words, the second metal layer 122 does not completely fill the first groove 121c. In this way, a gap not filled by the second metal layer 122 is left at the top of the first groove 121c, which can prevent the first conductive via 13 from squeezing the second metal layer 122 from the first groove 121c to the first surface 121a of the first metal layer 121 when expanding.

[0063] It is understandable that the thickness of the second metal layer is not necessarily the thicker the better. In some specific embodiments, the thickness of the second metal layer 122 should be less than 1 μm, such as 0.8 μm.

[0064] It should be clear that the bonding surface of the first bonding structure 12 refers to the surface of the first bonding structure 12 that is bonded to other bonding structures during bonding. It can be understood that the bonding surface includes the first surface 121a of the first metal layer and the surface of the second metal layer exposed from the first groove 121c. In one embodiment, the shape of the bonding surface of the first bonding structure 12 includes but is not limited to a circle, an ellipse, or a rectangle.

[0065] In one embodiment, the semiconductor structure further includes a second substrate 21, and a second bonding structure 22 formed in the second substrate 21, wherein the second bonding structure 22 is bonded to the first bonding structure 12. Figure 4 shown.

[0066] It should be clarified that the bonding surface of the second bonding structure 22 refers to the surface of the second bonding structure 22 that is bonded to other bonding structures during bonding. In one embodiment, the projections of the bonding surface of the second bonding structure 22 and the bonding surface of the first bonding structure 12 in the vertical direction coincide with each other. In other words, the shape and size of the bonding surface of the second bonding structure 22 are the same as the shape and size of the bonding surface of the first bonding structure 12. However, it is not limited to this. In other embodiments, the shape and size of the bonding surface of the second bonding structure 22 and the shape and size of the bonding surface of the first bonding structure 12 may also be different.

[0067] The second bonding structure 22 includes a third metal layer 221, and the material of the third metal layer 221 is the same as that of the first metal layer 121; the third metal layer 221 includes a first surface 221a and a second surface 221b that are oppositely arranged, and the first surface 221a of the third metal layer 221 is bonded to the first bonding structure 12.

[0068] In one embodiment, the semiconductor structure further includes a second conductive via 23 , wherein the second conductive via 23 is formed in the second substrate 21 , and the second conductive via 23 is in contact with and connected to the second surface 221 b of the third metal layer 221 .

[0069] In one embodiment, the second bonding structure 22 includes a fourth metal layer 222, and the material of the fourth metal layer 222 is the same as that of the second metal layer 122. The first surface 221a of the third metal layer 221 has a second groove 221c, and the fourth metal layer 222 is located in the second groove 221c.

[0070] In a specific embodiment, the projections of the second conductive via 23 and the second groove 221c in a direction perpendicular to the first surface 221a of the third metal layer 221 overlap. In this way, during bonding, the second conductive via 23 expands due to heat, which pushes the fourth metal layer 222 and the first bonding structure 12 to form an intermetallic compound, thereby improving the bonding strength.

[0071] In one embodiment, the first surface 221a of the third metal layer 221 is concave. Figure 5 In a specific embodiment, the concave shape includes but is not limited to a spherical concave shape.

[0072] When the third metal layer 221 is bonded to the first bonding structure 12, the first conductive via 13 expands due to heat, pushing the molten second metal layer 122 to fuse with the first surface 221a of the third metal layer 221 to form an intermetallic compound, thereby increasing the bonding strength. At the same time, since the second metal layer 122 in a molten state has fluidity, it will fill the space formed by the concave shape, and the bonding reliability will not be affected by the concave shape of the bonding surface.

[0073] In order to ensure the reliability of bonding, the depth of the recess should not be too large; in some embodiments, the maximum depth of the recess is between 1-5 nm.

[0074] In one embodiment, the first surface 221a of the third metal layer 221 is convex. Figure 6 In a specific embodiment, the convex shape includes but is not limited to a spherical convex shape.

[0075] Correspondingly, the bonding surface of the first bonding structure 12 bonded to the third metal layer 221 should be retracted into the first substrate by 1-5 nm to accommodate the first convex surface 221 a of the third metal layer 221 .

[0076] In summary, due to the chemical effect of the low melting point metal and the thermal expansion effect of the metal, the first surface 221a of the third metal layer 221 can be smoothly bonded to the first bonding structure 12 whether it is concave or convex, thereby reducing the flatness requirement for the bonding surface during bonding.

[0077] The present invention also provides a method for forming a semiconductor structure. Figure 7 As shown, the method comprises the following steps:

[0078] Step 701, providing a first substrate;

[0079] Step 702, forming a first bonding structure and a first conductive via in the first substrate; the first bonding structure includes a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, and the forming of the first bonding structure includes: forming the first metal layer, the first metal layer including a first surface and a second surface arranged opposite to each other; forming a first groove on the first surface of the first metal layer; forming the second metal layer in the first groove; the first conductive via is in contact with and connected to the second surface of the first metal layer, and the projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer coincide with each other.

[0080] Next, combine Figure 8a-8g The method for forming the semiconductor structure according to the embodiment of the present invention is further described in detail.

[0081] First, step 701 is performed to provide a first substrate 11, such as Figure 8a shown.

[0082] The material of the first substrate 11 may be silicon, germanium, gallium nitride, gallium arsenide, indium phosphide (InP), silicon on insulator (SOI), germanium on insulator (GeOI), etc., but is not limited thereto and may also be other materials that can be used as a substrate.

[0083] Next, step 702 is performed to form a first bonding structure 12 and a first conductive via 13 in the first substrate 11. Figure 8b-8d The first bonding structure 12 includes a first metal layer 121 and a second metal layer 122 having a melting point lower than that of the first metal layer 121, the first metal layer 121 includes a first surface 121a and a second surface 121b arranged opposite to each other, a first groove 121c is formed on the first surface 121a of the first metal layer 121, and the second metal layer 122 is formed in the first groove 121c; the first conductive via 13 is in contact with the second surface 121b of the first metal layer 121, and the projections of the first conductive via 13 and the first groove 121c in a direction perpendicular to the first surface 121a of the first metal layer 121 overlap.

[0084] Figure 8b-8dThe formation process of the first bonding structure 12 and the first conductive via 13 is shown. It should be noted that this is only an example, and other methods and steps may also be used to form the first bonding structure 12 and the first conductive via 13 .

[0085] See also Figure 8b A first metal layer 121 is formed in the first substrate 11, wherein the first metal layer 121 includes a first surface 121a and a second surface 121b that are oppositely disposed, and the first surface 121a is exposed from the first substrate 11 for subsequent bonding.

[0086] See also Figure 8c A first groove 121c is formed on the first surface 121a, and a second metal layer 122 is formed in the first groove 121c. The first metal layer 121 and the second metal layer 122 constitute a first bonding structure 12.

[0087] In one embodiment, the surface of the second metal layer 122 exposed from the first groove 121 c is flush with the first surface 121 a .

[0088] In one embodiment, the surface of the second metal layer 122 exposed from the first groove 121c is retracted toward the inside of the first substrate 11 by a certain distance compared to the first surface 121a. In other words, the thickness of the second metal layer 122 is less than the depth of the first groove 121c. In this way, the first conductive via 13 can be prevented from squeezing the second metal layer 122 from the first groove 121c to the first surface 121a of the first metal layer 121 when expanding.

[0089] See also Figure 8d , a first conductive via 13 is formed in the first substrate 11, the first conductive via 13 is in contact with the second surface 121b, and the projections of the first conductive via 13 and the first groove 121c in a direction perpendicular to the first surface 121a of the first metal layer 121 coincide with each other. In this way, during bonding, the first conductive via 13 expands due to heat, which pushes the second metal layer 122 to form an intermetallic compound with other bonding structures, thereby improving the bonding strength. Specifically, the first conductive via 13 includes but is not limited to through silicon vias (TSVs).

[0090] In one embodiment, the method for forming the semiconductor structure further includes providing a second substrate 21; forming a second bonding structure 22 in the second substrate 21; and bonding the second bonding structure 22 to the first bonding structure 12. Figure 8e-8g shown.

[0091] See also Figure 8e, providing a second substrate 21, wherein the material of the second substrate 21 may be the same as or different from the material of the first substrate 11.

[0092] See also Figure 8f , forming a second bonding structure 22 in the second substrate 21. In one embodiment, forming the second bonding structure 22 includes: forming a third metal layer 221, the material of the third metal layer 221 is the same as the material of the first metal layer 121, and the third metal layer 221 includes a first surface 221a and a second surface 221b arranged opposite to each other.

[0093] In one embodiment, the method further includes forming a second conductive via 23 in the second substrate 21 , wherein the second conductive via 23 is in contact with and connected to the second surface 221 b of the third metal layer 221 .

[0094] In one embodiment, forming the second bonding structure 22 also includes: forming a second groove 221c on the first surface 221a of the third metal layer 221, forming a fourth metal layer 222 in the second groove 221c, and the material of the fourth metal layer 222 is the same as that of the second metal layer 122.

[0095] See also Figure 8g , the second bonding structure 22 is bonded to the first bonding structure 12 .

[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a first substrate, and a first bonding structure and a first conductive via formed in the first substrate; The first bonding structure includes a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, the first metal layer includes a first surface and a second surface arranged opposite to each other, the first surface of the first metal layer has a first groove, and the second metal layer is located in the first groove; The first conductive via is in contact with the second surface of the first metal layer, and projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer overlap.

2. The semiconductor structure according to claim 1, characterized in that: The thickness of the second metal layer is smaller than the depth of the first groove.

3. The semiconductor structure according to claim 1, characterized in that: The thickness of the second metal layer is less than 1 μm.

4. The semiconductor structure according to claim 1, characterized in that The second metal layer includes at least one material selected from the group consisting of bismuth, cadmium, tin, lead, dysprosium, and indium.

5. The semiconductor structure according to claim 1, characterized in that: The first metal layer includes at least one of copper and tungsten.

6. The semiconductor structure according to claim 1, characterized in that The bonding surface of the first bonding structure may be in a circular, elliptical, or rectangular shape.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes a second substrate and a second bonding structure formed in the second substrate; the second bonding structure is bonded to the first bonding structure.

8. The semiconductor structure according to claim 7, characterized in that: The bonding surface of the first bonding structure and the bonding surface of the second bonding structure have the same shape and area.

9. The semiconductor structure according to claim 7, characterized in that: The second bonding structure includes a third metal layer made of the same material as the first metal layer, the third metal layer includes a first surface and a second surface that are oppositely disposed, and the first surface of the third metal layer is bonded to the first bonding structure.

10. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further includes a second conductive via formed in the second substrate, and the second conductive via is in contact with and connected to the second surface of the third metal layer.

11. The semiconductor structure according to claim 10, characterized in that: The second bonding structure includes a fourth metal layer made of the same material as the second metal layer; the first surface of the third metal layer has a second groove, and the fourth metal layer is located in the second groove.

12. The semiconductor structure according to claim 11, characterized in that: Projections of the second conductive via and the second groove in a direction perpendicular to the first surface of the third metal layer overlap.

13. The semiconductor structure according to claim 9, characterized in that: The first surface of the third metal layer is concave, and the maximum depth of the concave is between 1-5 nm.

14. The semiconductor structure according to claim 9, characterized in that: The first surface of the third metal layer is convex, and the maximum height of the convexity is between 1-5 nm.

15. The semiconductor structure according to claim 14, characterized in that: The bonding surface of the first bonding structure is indented toward the first substrate by 1-5 nm to accommodate the first convex surface of the third metal layer.

16. A method for forming a semiconductor structure, characterized in that: include: providing a first substrate; forming a first bonding structure and a first conductive via in the first substrate; The first bonding structure includes a first metal layer and a second metal layer having a melting point lower than that of the first metal layer, and the forming of the first bonding structure includes: forming the first metal layer, the first metal layer including a first surface and a second surface arranged opposite to each other; forming a first groove on the first surface of the first metal layer; and forming the second metal layer in the first groove; The first conductive via is in contact with the second surface of the first metal layer, and projections of the first conductive via and the first groove in a direction perpendicular to the first surface of the first metal layer overlap.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method further includes: providing a second substrate; forming a second bonding structure in the second substrate; and bonding the second bonding structure to the first bonding structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The second bonding structure is formed, including: forming a third metal layer, the material of the third metal layer is the same as the material of the first metal layer, and the third metal layer includes a first surface and a second surface arranged opposite to each other.

19. The method for forming a semiconductor structure according to claim 18, wherein: Bonding the second bonding structure to the first bonding structure comprises: The first surface of the third metal layer is bonded to the bonding surface of the first bonding structure.

20. The method for forming a semiconductor structure according to claim 18, wherein: The method further includes: forming a second conductive via in the second substrate, wherein the second conductive via is in contact with and connected to the second surface of the third metal layer.

21. The method for forming a semiconductor structure according to claim 18, wherein: The forming of the second bonding structure also includes: forming a second groove on the first surface of the third metal layer, forming a fourth metal layer in the second groove, and the material of the fourth metal layer is the same as that of the second metal layer.

Images