Semiconductor dielectric layer structure and method of fabrication

Abstract

The application discloses a semiconductor dielectric layer structure and a manufacturing method. The semiconductor dielectric layer structure comprises a semiconductor substrate, an epitaxial layer arranged on the surface of the semiconductor substrate, a plurality of grooves arranged on the epitaxial layer, a first thermal oxidation layer arranged on the surface of the epitaxial layer, in-situ doped polysilicon filled in the grooves, a gate oxide layer formed between the in-situ doped polysilicon and the grooves, a silicon nitride layer arranged on the surface of the first thermal oxidation layer between the adjacent grooves, a second thermal oxidation layer arranged on the surface of the silicon nitride layer, a deposited oxide layer arranged on the surface of the second thermal oxidation layer, a contact hole formed by hollowing out the deposited oxide layer, the second thermal oxidation layer, a part of the first thermal oxidation layer and the silicon nitride layer at the bottom of the second thermal oxidation layer, and the bottom end of the contact hole extending to the surface of the epitaxial layer in the middle part of the bottom end, so that the top of the epitaxial layer is exposed, and the bottom end edge of the bottom part of the contact hole extends to the in-situ doped polysilicon to expose the gate oxide layer of the inner wall of the groove. The application can achieve the purpose of reducing reverse leakage current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor dielectric layer structure and a manufacturing method. BACKGROUND

[0002] The Schottky diode has the advantages of low on-voltage and fast switching speed, but also has the disadvantage of large reverse leakage current. The power loss of the Schottky diode in a circuit includes forward loss, turn-on loss, turn-off loss and reverse loss. Since the reverse leakage current of the Schottky diode is large, the reverse loss is the main source of power loss. In terms of structural principle, the trench MOS Schottky can effectively reduce the electric field at the Schottky contact and weaken the influence of the Schottky barrier lowering effect by using the electric field shielding effect. Since the Schottky leakage current is exponentially dependent on the electric field, the trench MOS Schottky structure can greatly reduce the leakage current compared to the planar Schottky.

[0003] In terms of manufacturing process, the contact hole etching of the planar Schottky often uses a wet etching process, which causes less damage to the semiconductor surface and has an ideal semiconductor surface. However, due to the particularity of the oxide layer structure of the trench MOS Schottky, the contact hole etching often needs dry etching. In order to ensure that the oxide layer is etched clean, a certain over-etching amount must be ensured, which will cause damage to the semiconductor surface and increase the reverse leakage current. Figure 14 As shown in the following, the process steps of the commonly used trench MOS Schottky from the production process to the contact hole etching are briefly described as follows:

[0004] 1) A thermal oxide layer 2 is grown on a semiconductor epitaxial layer 1. The thermal oxide layer 2 will serve as a mask layer for trench etching, and its thickness is adjusted according to the selectivity ratio of trench etching, generally with a thickness of 600-800 nm;

[0005] 2) A window for the trench is etched on the thermal oxide layer 2 through a photolithography and etching process, and the remaining thermal oxide layer 2 will serve as a mask medium for trench etching. After etching is completed, all photoresists are removed;

[0006] 3) The trench pattern is etched using the thermal oxide layer 2 as a mask;

[0007] 4) A thermal oxide layer 2 is grown as a gate oxide layer 3 of the trench MOS, and its wet etching rate is the same as that of the thermal oxide layer 2;

[0008] 5) After depositing in-situ doped polysilicon 4, it is etched back, and the remaining in-situ doped polysilicon 4 will serve as the filling material of the trench and as the gate contact material of the trench MOS;

[0009] 6)Deposited oxide layer 5 as a dielectric layer between the semiconductor and the top layer metal. The wet etching rate of the deposited oxide layer 5 can reach 7 times of the wet etching rate of the thermal oxide layer, and the difference is large. However, the dry etching rates of the two are not much different;

[0010] 7)Coating photoresist 6 and photoetching, and the photoresist 6 formed will be used as a mask layer for contact hole etching. It can be seen that the contact hole etching needs to separate the deposited oxide layer 5 and the thermal oxide layer 2, and then the semiconductor surface can be contacted;

[0011] 8)Due to the oxide layer structure of the contact hole to be etched, the dry etching method is generally used for contact hole etching; if the wet etching is used, the deposited oxide layer 5 will be etched clean in advance, and then the thermal oxide layer 3 (gate oxide layer) will be seriously over-etched, causing device failure;

[0012] 9)After the contact hole etching, the photoresist is removed;

[0013] 10)Subsequently, a Schottky barrier, a top layer metal, a passivation layer and the like will be continuously manufactured, which is not described here. SUMMARY

[0014] The embodiment of the present application provides a semiconductor dielectric layer structure and a manufacturing method, and aims to solve the problem of more reverse leakage of the existing Schottky diode.

[0015] The present application provides a semiconductor dielectric layer structure, which comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, the epitaxial layer is provided with a plurality of grooves, a first thermal oxide layer is arranged on the surface of the epitaxial layer, in-situ doped polysilicon is filled in the grooves, a gate oxide layer is formed between the in-situ doped polysilicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxide layer adjacent to the grooves, a second thermal oxide layer is arranged on the surface of the silicon nitride layer, a deposited oxide layer is arranged on the surface of the second thermal oxide layer, the deposited oxide layer, the second thermal oxide layer, the silicon nitride layer at the bottom of the second thermal oxide layer and a part of the first thermal oxide layer are hollowed out to form a contact hole, the bottom middle part of the contact hole extends to the surface of the epitaxial layer, the top of the epitaxial layer is exposed, and the bottom edge of the bottom part in the bottom of the contact hole extends to the in-situ doped polysilicon, the gate oxide layer of the inner wall of the groove is exposed, the filling height of the polysilicon in the groove in the contact hole area falls within 0-20 nm below the top surface interface of the epitaxial layer, and the filling height of the polysilicon in the groove outside the contact hole area falls within the thickness range of the silicon nitride layer.

[0016] Further, the thickness of the first thermal oxide layer is 27-33 nm.

[0017] Further, the thickness of the silicon nitride layer is 180-220 nm.

[0018] Further, the second thermal oxide layer has a thickness of 549-671 nm.

[0019] Further, the oxide layer has a thickness of 330-470 nm.

[0020] In another aspect, the application also provides a method for manufacturing the semiconductor dielectric layer structure as described in any of the above aspects, the method comprising:

[0021] Step one, growing a first thermal oxide layer on an epitaxial layer of a semiconductor, depositing a silicon nitride layer on a surface of the first thermal oxide layer, depositing an undoped in-situ polysilicon on a surface of the silicon nitride layer, and completely oxidizing the undoped in-situ polysilicon on the silicon nitride layer to form a second thermal oxide layer;

[0022] Step two, etching a window of a trench on the first thermal oxide layer, the silicon nitride layer and the second thermal oxide layer by an etching process, and removing all photoresists after the etching is completed;

[0023] Step three, etching a trench on the epitaxial layer by using the window, and generating a thermal oxide layer on an inner wall of each trench as a gate oxide layer of a trench MOS;

[0024] Step four, depositing an in-situ doped polysilicon, and performing a first re-etching on the in-situ doped polysilicon so that an interface of the in-situ doped polysilicon falls within a thickness range of the silicon nitride layer;

[0025] Step five, depositing on a surface of the second thermal oxide layer and the in-situ doped polysilicon after the re-etching is completed to form a deposited oxide layer;

[0026] Step six, coating and photoetching a photoresist on a surface of the deposited oxide layer to form a photoresist pattern as a mask layer for etching a contact hole;

[0027] Step seven, etching the deposited oxide layer and the second thermal oxide layer at corresponding positions based on the photoresist pattern by dry etching until the silicon nitride layer and the in-situ doped polysilicon are exposed;

[0028] Step eight, removing the photoresist completely, and performing a second re-etching on the in-situ doped polysilicon by dry etching until a surface of the in-situ doped polysilicon is 0-20 nm below a top surface interface of the epitaxial layer, the first thermal oxide layer under the silicon nitride layer is exposed, and the in-situ doped polysilicon left finally is used as a filling material of the trench and a gate contact material of the trench MOS;

[0029] Step nine, etching the silicon nitride layer in the contact hole by wet etching, and then etching the first thermal oxide layer in the contact hole until the epitaxial layer is exposed to obtain the semiconductor dielectric layer structure.

[0030] Further, the assembly hole further comprises a plurality of second assembly holes, and the undoped in-situ polysilicon has a thickness of 245-295 nm.

[0031] Further, the accommodating groove is circular, and the capacitor is also circular, and the silicon nitride layer in the contact hole is etched by wet etching through hot phosphoric acid.

[0032] Further, the first thermal oxide layer in the contact hole is etched by wet etching.

[0033] Further, the amount of wet etching of the first thermal oxide layer is controlled to be 120%.

[0034] The embodiment of the present application provides a semiconductor medium layer structure and a manufacturing method. The semiconductor medium layer structure comprises a semiconductor substrate, the surface of the semiconductor substrate is provided with an epitaxial layer, the epitaxial layer is provided with a plurality of grooves, the surface of the epitaxial layer is provided with a first thermal oxide layer, the grooves are filled with in-situ doped polysilicon, a gate oxide layer is formed between the in-situ doped polysilicon and the grooves, the surface of the first thermal oxide layer between the adjacent grooves is provided with a silicon nitride layer, the surface of the silicon nitride layer is provided with a second thermal oxide layer, the surface of the second thermal oxide layer is provided with a deposited oxide layer, the deposited oxide layer, the second thermal oxide layer, the silicon nitride layer at the bottom of the second thermal oxide layer and a part of the first thermal oxide layer are hollowed out to form a contact hole, the bottom middle part of the contact hole extends to the surface of the epitaxial layer, the top of the epitaxial layer is exposed, and the bottom edge of the bottom part in the contact hole extends to the in-situ doped polysilicon, the gate oxide layer of the inner wall of the groove is exposed, the filling height of the polysilicon in the groove in the contact hole area falls within 0-20 nm below the surface interface of the top of the epitaxial layer, and the filling height of the polysilicon in the groove outside the contact hole area falls within the thickness range of the silicon nitride layer. Compared with the prior art, the semiconductor medium layer structure of the present application is based on the deposited oxide layer, the silicon nitride layer at the bottom of the oxide layer and a part of the first thermal oxide layer, and the contact hole is formed by hollowing out, the bottom middle part of the contact hole extends to the surface of the epitaxial layer, the top of the epitaxial layer is exposed, the bottom edge of the bottom part in the contact hole extends to the in-situ doped polysilicon, and the gate oxide layer of the inner wall of the groove is exposed, so that the Schottky diode using the semiconductor medium layer structure can have a more ideal contact surface, and the purpose of reducing reverse leakage current is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0036] Figure 1 The overall schematic diagram of the semiconductor medium layer structure provided by the embodiment of the present application is shown.

[0037] Figure 2 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0038] Figure 3 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0039] Figure 4 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0040] Figure 5 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0041] Figure 6 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0042] Figure 7 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0043] Figure 8 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0044] Figure 9 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0045] Figure 10 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0046] Figure 11 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0047] Figure 12 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0048] Figure 13 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0049] Figure 14 A structure schematic diagram of an embodiment of a semiconductor medium layer structure manufacturing method provided by the embodiment of the present application;

[0050] Figure: 1, epitaxial layer; 2, first thermal oxide layer; 3, silicon nitride layer; 4, undoped in situ polysilicon; 5, second thermal oxide layer; 6, gate oxide layer; 7, in situ doped polysilicon; 8, deposited oxide layer; 9, photoresist. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0052] It should be understood that, when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application. As used in the specification and the appended claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise.

[0054] It should be further understood that the term "and / or" used in the specification and the appended claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0055] As Figure 1The embodiment of the present application provides a semiconductor dielectric layer structure, which comprises a semiconductor substrate, the surface of the semiconductor substrate is provided with an epitaxial layer 1, the epitaxial layer 1 is provided with a plurality of grooves, the surface of the epitaxial layer 1 is provided with a first thermal oxidation layer 2, the grooves are filled with in-situ doped polysilicon 7, a gate oxide layer 6 is formed between the in-situ doped polysilicon 7 and the grooves, the surface of the first thermal oxidation layer 2 adjacent to the grooves is provided with a silicon nitride layer 3, the surface of the silicon nitride layer 3 is provided with a second thermal oxidation layer 5, the surface of the second thermal oxidation layer 5 is provided with a deposited oxide layer 8, the deposited oxide layer 8, the thermal oxidation layer 5, the silicon nitride layer 3 at the bottom of the thermal oxidation layer 5 and a part of the first thermal oxidation layer 2 are hollowed out to form a contact hole, the bottom end of the contact hole extends to the surface of the epitaxial layer 1, the top of the epitaxial layer 1 is exposed, and the bottom end edge of the bottom of the contact hole extends to the in-situ doped polysilicon 7, the gate oxide layer 6 of the inner wall of the groove is exposed, the filling height of the polysilicon in the groove in the contact hole area is 0-20nm below the top surface interface of the epitaxial layer, and the filling height of the polysilicon in the groove outside the contact hole area is within the thickness range of the silicon nitride layer. Compared with the prior art, the semiconductor dielectric layer structure is based on the deposited oxide layer 8, the thermal oxidation layer 5, the silicon nitride layer 3 at the bottom of the thermal oxidation layer 5 and a part of the first thermal oxidation layer 2 which are hollowed out to form a contact hole, the bottom end of the contact hole extends to the surface of the epitaxial layer 1, the top of the epitaxial layer 1 is exposed, and the bottom end edge of the bottom of the contact hole extends to the in-situ doped polysilicon 7, the gate oxide layer 6 of the inner wall of the groove is exposed, which can ensure that the Schottky diode using the semiconductor dielectric layer structure has a relatively ideal contact surface, and the purpose of reducing reverse leakage current is achieved.

[0056] In an embodiment, the thickness of the first thermal oxidation layer 2 is preferably 27-33nm, the thickness of the silicon nitride layer 3 is preferably 180-220nm, the thickness of the second thermal oxidation layer 5 is preferably 549-671nm, and the thickness of the deposited oxide layer 8 is preferably 330-470nm.

[0057] Figure 2 A flowchart of a specific embodiment of the method for manufacturing the semiconductor dielectric layer structure is shown.

[0058] Step one, growing a first thermal oxidation layer 2 with a thickness of 27-33nm on the epitaxial layer 1 of the semiconductor; then depositing a silicon nitride layer 3 with a thickness of 180-220nm on the surface of the first thermal oxidation layer 2; then depositing undoped in-situ polysilicon 4 with a thickness of 549-671nm on the surface of the silicon nitride layer 3, as shown in FIG. 1; finally, completely oxidizing the undoped in-situ polysilicon 4 on the silicon nitride layer 3 to generate a second thermal oxidation layer 5, as shown in FIG. 2. Figure 2 Figure 3 ​As shown. Because the silicon nitride layer 3 effectively blocks oxygen, the thickness of the dielectric layer below the silicon nitride layer 3 remains unchanged; only the undoped in-situ polysilicon 4 is oxidized to form the second thermal oxide layer 5. Typically, the second thermal oxide layer 5 on the silicon nitride layer 3 is obtained through deposition, resulting in a relatively poor quality deposited second thermal oxide layer 5. This invention obtains a high-quality second thermal oxide layer 5 on a high-quality silicon nitride layer by depositing undoped in-situ polysilicon 4 on the silicon nitride layer and then completely oxidizing the undoped in-situ polysilicon 4.

[0059] Step Two, as follows Figure 4 As shown, the trench window is etched into the first thermal oxide layer 2, the silicon nitride layer 3, and the second thermal oxide layer 5 using an etching process. The unetched portion of the second thermal oxide layer 5 will serve as a mask during trench etching. After the window etching is completed, the photoresist 9 is completely removed.

[0060] Step 3, as follows Figure 5 As shown, trenches are etched on epitaxial layer 1 according to the window; as Figure 6 As shown, a thermal oxide layer is generated on the inner wall of each trench as the gate oxide layer 6 of the trench MOS.

[0061] Step 4, as follows Figure 7 As shown, in-situ doped polysilicon 7 is deposited and then etched back for the first time. It is necessary to control the amount of etch back so that the interface of the in-situ doped polysilicon 7 falls within the thickness range of the silicon nitride layer 3.

[0062] Step 5, as follows Figure 8 As shown, an oxide layer 8 with a thickness of 630–770 nm is deposited on the surface of the second thermal oxide layer 5 and the in-situ doped polysilicon 7 after the etch-back process.

[0063] Step Six, as Figure 9 As shown, photoresist 9 is coated and photolithographically formed on the surface of the deposited oxide layer 8, and the resulting photoresist 9 pattern serves as a masking layer for the etching of the contact holes. The contact holes need to be completely etched away from the deposited oxide layer 8, the second thermal oxide layer 5, the deposited silicon nitride, and the thermal oxide layer 2.

[0064] Step 7, as follows Figure 10 As shown, based on the photoresist pattern 9, the oxide layer 8 and the second thermal oxide layer 5 deposited at the corresponding positions are etched by dry etching until the silicon nitride layer 3 and the in-situ doped polysilicon 7 are exposed. Since the silicon nitride layer 3, the in-situ doped polysilicon 7 have a high selectivity to the deposited oxide layer 8 and the second thermal oxide layer 5, the etching endpoint can be easily placed at the interface between the deposited silicon nitride layer 3 and the in-situ doped polysilicon 7.

[0065] Step 8, as Figure 11As shown, the photoresist 9 is removed completely; the in-situ doped polysilicon 7 is etched back for the second time by dry etching until the surface of the in-situ doped polysilicon 7 is within 20 nm below the interface, the first thermal oxide layer 2 under the silicon nitride layer 3 is exposed, and the in-situ doped polysilicon left finally is used as the filling material of the trench and the gate contact material of the trench MOS, as shown in Figure 12 The interface refers to the top surface of the epitaxial layer 1.

[0066] Step nine, as shown in Figure 13 , the silicon nitride layer 3 in the contact hole is etched by wet etching, and finally as shown in Figure 1 , the first thermal oxide layer 2 in the contact hole is etched until the epitaxial layer 1 is exposed, obtaining the semiconductor medium layer structure. When the silicon nitride layer 3 is etched by wet etching, hot phosphoric acid is used for wet etching to ensure that the deposited oxide layer 8 and the in-situ doped polysilicon 7 will not be etched. The thickness uniformity of the first thermal oxide layer 2 is good, and the wet etching is controlled within 120% to ensure that the first thermal oxide layer 2 on the surface of the semiconductor is etched completely. The thickness of the deposited oxide layer 8 will also be lost by about 300 nm. And because the semiconductor surface is finally exposed by wet etching, a relatively ideal surface state can be ensured, achieving the purpose of reducing reverse leakage current.

[0067] It should be noted that the wet etching of the first thermal oxide layer 2 is controlled to be 120%, which means that the wet etching time is controlled according to 120% of the thickness of the first thermal oxide layer 2.

[0068] The semiconductor medium layer structure disclosed in the present application forms a contact hole based on the deposited oxide layer 8, the second thermal oxide layer 5, the silicon nitride layer 3 at the bottom of the second thermal oxide layer 5, and part of the first thermal oxide layer 2, and the bottom middle of the contact hole extends to the surface of the epitaxial layer 1, so that the top of the epitaxial layer 1 is exposed, and the bottom edge of the bottom of the contact hole extends to the in-situ doped polysilicon 7, exposing the gate oxide layer 6 of the inner wall of the trench, which can ensure that the Schottky diode using the semiconductor medium layer structure has a relatively ideal contact surface, achieving the purpose of reducing reverse leakage current.

[0069] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0070] It should also be noted that, in the specification, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0071] Without further limitation, an element defined by an "includes a... " statement is not meant to be an exclusive inclusion, such that a process, method, article, or apparatus that includes elements in addition to or other than those listed apart from the item defined in the "includes a... " statement are not covered even though the defined item can be inherently or constructively a subset of the element.

Claims

1. A method for fabricating a semiconductor dielectric layer structure, characterized in that, The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, the epitaxial layer is provided with a plurality of grooves, a first thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polysilicon is filled in the grooves, a gate oxide layer is formed between the in-situ doped polysilicon and the grooves, a silicon nitride layer is arranged on the surface of the first thermal oxidation layer adjacent to the grooves, a second thermal oxidation layer is arranged on the surface of the silicon nitride layer, a deposited oxide layer is arranged on the surface of the second thermal oxidation layer, the deposited oxide layer, the second thermal oxidation layer, the silicon nitride layer at the bottom of the second thermal oxidation layer and a part of the first thermal oxidation layer are hollowed out to form a contact hole, the bottom end of the contact hole extends to the surface of the epitaxial layer in the middle, the top of the epitaxial layer is exposed, and the bottom end of the bottom of the contact hole extends to the in-situ doped polysilicon, the gate oxide layer of the inner wall of the groove is exposed, the filling height of the polysilicon in the groove in the contact hole area is 0-20 nm below the top surface interface of the epitaxial layer, and the filling height of the polysilicon in the groove outside the contact hole area is within the thickness range of the silicon nitride layer; The manufacturing method comprises: Step one, growing a first thermal oxidation layer on the epitaxial layer of a semiconductor, depositing a silicon nitride layer on the surface of the first thermal oxidation layer, depositing undoped in-situ polysilicon on the surface of the silicon nitride layer, completely oxidizing the undoped in-situ polysilicon on the silicon nitride layer to generate a second thermal oxidation layer; Step two, etching a window of a groove on the first thermal oxidation layer, the silicon nitride layer and the second thermal oxidation layer through an etching process, and removing all photoresists after etching is completed; Step three, etching a groove on the epitaxial layer by using the window, and generating a thermal oxidation layer on the inner wall of each groove as a gate oxide layer of a groove MOS; Step four, depositing in-situ doped polysilicon and performing first back etching on the in-situ doped polysilicon, so that the interface of the in-situ doped polysilicon is within the thickness range of the silicon nitride layer; Step five, depositing on the surface of the second thermal oxidation layer and the in-situ doped polysilicon after back etching to generate a deposited oxide layer; Step six, coating and photoetching photoresists on the surface of the deposited oxide layer to form a photoresist pattern as a mask layer for etching of a contact hole; Step seven, based on the photoresist pattern, etching the deposited oxide layer and the second thermal oxidation layer at corresponding positions by dry etching until the silicon nitride layer and the in-situ doped polysilicon are exposed; Step eight, removing the photoresists completely, and performing second back etching on the in-situ doped polysilicon by dry etching until the surface of the in-situ doped polysilicon is 0-20 nm below the top surface interface of the epitaxial layer, the first thermal oxidation layer under the silicon nitride layer is exposed, and the in-situ doped polysilicon left finally is used as a filling material of the groove and a gate contact material of the groove MOS; Step nine, etching the silicon nitride layer in the contact hole by wet etching, and then etching the first thermal oxidation layer in the contact hole until the epitaxial layer is exposed, to obtain a semiconductor medium layer structure.

2. The method of claim 1, wherein The thickness of the undoped in-situ polysilicon is 245-295 nm.

3. The method of claim 1, wherein the step of forming the semiconductor dielectric layer structure is performed by a method selected from the group consisting of: a thermal oxidation method, a plasma oxidation method, a chemical vapor deposition method, a sputtering method, and a combination thereof. The silicon nitride layer in the contact hole is etched by wet etching with hot phosphoric acid.

4. The method of claim 1, wherein The first thermal oxide layer in the contact hole is etched by wet etching.

5. The method of claim 4, wherein the step of forming the semiconductor dielectric layer structure is performed by a method selected from the group consisting of: a thermal oxidation method, a plasma oxidation method, a chemical vapor deposition method, a sputtering method, and a combination thereof. The amount of wet etching of the first thermal oxide layer is controlled to 120%.

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