Epitaxial wafer of light-emitting diode with improved luminous efficiency and preparation method thereof

Abstract

The present disclosure provides an epitaxial wafer for a light-emitting diode (LED) with improved luminous efficiency and a method for preparing the same, belonging to the field of optoelectronic manufacturing technology. The preparation method comprises: providing a substrate; sequentially growing an n-type layer, a light-emitting layer, and a p-type layer on the substrate, wherein the light-emitting layer comprises a plurality of stacked active layers, each of which comprises a sequentially stacked InGaN quantum well layer, a Mg metal layer, a p-type GaN layer, and a GaN quantum barrier layer; before forming the p-type GaN layer, introducing an Mg source into a reaction chamber, surface-treating the InGaN quantum well layer, and forming the Mg metal layer within a pit on the surface of the InGaN quantum well layer. The embodiments of the present disclosure can improve the crystal quality at the interface between the quantum well and the quantum barrier and the internal quantum efficiency of the light-emitting diode, thereby improving the luminous efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an epitaxial wafer of a light-emitting diode (LED) with improved luminous efficiency and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs), a highly influential new product in the optoelectronics industry, boast small size, long lifespan, rich colors, and low energy consumption. They are widely used in lighting, display screens, signal lights, backlights, toys, and other fields. The core structure of LEDs is the epitaxial wafer, and its fabrication significantly influences the optoelectronic properties of LEDs.

[0003] Epitaxial wafers typically consist of a substrate, an n-type GaN layer, a light-emitting layer, and a p-type GaN layer, stacked sequentially on the substrate. The light-emitting layer typically comprises multiple alternating layers of InGaN quantum well layers and GaN quantum barrier layers.

[0004] Since the InGaN quantum well layer is a high-In component material, In-rich nanoclusters and V-shaped pits will grow on its surface. As a result, the surface of the InGaN quantum well layer is uneven and a large number of defects or dislocations will be formed, which in turn leads to poor crystal quality at the interface between the quantum well and the quantum barrier. In addition, the strain caused by growing the InGaN quantum well layer on the GaN polar surface will produce a strong built-in polarization field, resulting in the separation of electrons and holes in the light-emitting layer, greatly reducing the radiative recombination rate and affecting the internal quantum efficiency (IQE) of the light-emitting diode. Summary of the Invention

[0005] The present disclosure provides an epitaxial wafer for a light-emitting diode (LED) with improved luminous efficiency and a method for preparing the same, which can improve the crystal quality at the interface between quantum wells and quantum barriers and the internal quantum efficiency of the LED, thereby improving luminous efficiency. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a method for preparing an epitaxial wafer of a light-emitting diode, the method comprising:

[0007] providing a substrate;

[0008] An n-type layer, a light-emitting layer, and a p-type layer are sequentially grown on the substrate. The light-emitting layer includes a plurality of stacked active layers. Each active layer includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer, and a GaN quantum barrier layer stacked in sequence. Before forming the p-type GaN layer, an Mg source is introduced into a reaction chamber to perform surface treatment on the InGaN quantum well layer, thereby forming the Mg metal layer in pits on the surface of the InGaN quantum well layer.

[0009] Optionally, the Mg metal layer is formed in the following manner: the flow rate of the Mg source is 50 sccm to 500 sccm, the time of the Mg source introduction is 5s to 30s, the growth temperature is 750°C to 810°C, the growth pressure is 200Torr to 500Torr, and the growth atmosphere is a mixed atmosphere of ammonia, nitrogen and hydrogen.

[0010] Optionally, when growing the InGaN quantum well layer, the growth temperature is 700° C. to 830° C., the growth pressure is 100 Torr to 300 Torr, and the growth atmosphere is a mixed atmosphere of ammonia and nitrogen.

[0011] Optionally, when growing the p-type GaN layer, the growth temperature is 800° C. to 880° C., the growth pressure is 200 Torr to 500 Torr, and the growth atmosphere is a mixed atmosphere of ammonia, nitrogen, and hydrogen.

[0012] Optionally, when growing the GaN quantum barrier layer, the growth temperature is 800° C. to 960° C., and the growth pressure is 100 Torr to 300 Torr.

[0013] On the other hand, an embodiment of the present disclosure also provides an epitaxial wafer of a light-emitting diode, which includes a substrate and an n-type layer, a light-emitting layer and a p-type layer formed in sequence on the substrate; the light-emitting layer includes a plurality of stacked active layers, each of the active layers includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer and a GaN quantum barrier layer, the InGaN quantum well layer, the p-type GaN layer and the GaN quantum barrier layer are stacked in sequence, the InGaN quantum well layer has a pit near the surface of the p-type GaN layer, and the Mg metal layer fills the pit.

[0014] Optionally, in each of the active layers, the Mg doping concentration of the p-type GaN layer gradually decreases to 0 in a direction from the InGaN quantum well layer to the GaN quantum barrier layer.

[0015] Optionally, the Mg doping concentration of the region with the highest Mg doping concentration in the p-type GaN layer is 1×10 17 cm -3 to 1×10 19 cm-3 .

[0016] Optionally, the p-type GaN layer has a thickness of 2 angstroms to 20 angstroms.

[0017] Optionally, the thickness of the InGaN quantum well layer is 2 nm to 5 nm, and the thickness of the GaN quantum barrier layer is 8 nm to 20 nm.

[0018] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0019] The light-emitting layer of the epitaxial wafer prepared by the preparation method of the disclosed embodiment includes multiple stacked active layers, each of which includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer, and a GaN quantum barrier layer stacked in sequence. The Mg metal layer is formed on the surface of the InGaN quantum well layer by introducing an Mg source.

[0020] In this way, the characteristic that Mg tends to be enriched near the dislocation center with strong chemical activity is utilized. After the Mg source is introduced for treatment, Mg tends to accumulate at the position of the V-shaped pit during the treatment process. This can restore the surface of the InGaN quantum well layer to be smooth, reduce the probability of defects or dislocations diffusing to the quantum barrier layer, and improve the crystal quality at the interface between the quantum well and the quantum barrier.

[0021] A p-type GaN layer is also grown on the Mg metal layer. The holes generated by the p-type GaN layer can neutralize part of the piezoelectric polarization negative charge at this interface. Reducing the polarization charge density at the interface can reduce the polarization field strength, weaken the piezoelectric polarization field and quantum confined Stark effect, and improve the internal quantum efficiency of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 1 is a schematic structural diagram of an epitaxial wafer of a light-emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 2 This is a flow chart of a method for preparing an epitaxial wafer of a light-emitting diode provided in an embodiment of the present disclosure.

[0025] The descriptions of the marks in the figure are as follows:

[0026] 10. Substrate;

[0027] 20. n-type layer;

[0028] 3. Light-emitting layer; 30. Active layer; 31. InGaN quantum well layer; 32. Mg metal layer; 33. p-type GaN layer; 330. Pit; 34. GaN quantum barrier layer;

[0029] 40. p-type layer; 41. low-temperature p-type AlGaN layer; 42. p-type electron blocking layer; 43. high-temperature p-type GaN layer; 44. p-type ohmic contact layer;

[0030] 51. Buffer layer; 52. Undoped GaN layer; 53. AlN layer. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] Figure 1 Schematic diagram of the structure of an epitaxial wafer of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the epitaxial wafer includes a substrate 10 and an n-type layer 20 , a light-emitting layer 3 and a p-type layer 40 sequentially formed on the substrate 10 .

[0033] like Figure 1 As shown, the light-emitting layer 3 includes a plurality of stacked active layers 30, each of which includes an InGaN quantum well layer 31, a Mg metal layer 32, a p-type GaN layer 33 and a GaN quantum barrier layer 34 stacked in sequence, and the Mg metal layer 32 is a film layer formed on the surface of the InGaN quantum well layer 31 by introducing a Mg source.

[0034] The light-emitting layer 3 of the epitaxial wafer of the embodiment of the present disclosure includes multiple stacked active layers 30, each active layer 30 includes an InGaN quantum well layer 31, a Mg metal layer 32, a p-type GaN layer 33 and a GaN quantum barrier layer 34. The InGaN quantum well layer 31, the p-type GaN layer 33 and the GaN quantum barrier layer 34 are stacked in sequence. The surface of the InGaN quantum well layer 31 near the p-type GaN layer 33 has a pit 330, and the Mg metal layer 32 fills the pit 330.

[0035] For example, the pits on the surface of the InGaN quantum well layer 31 may be V-shaped pits, and the surface of the InGaN quantum well layer 31 may have a plurality of pits arranged at intervals. The Mg metal layer 32 is filled in the pits 330 to make the surface of the InGaN quantum well layer 31 smoother.

[0036] By utilizing the characteristic that Mg tends to accumulate near the dislocation centers with较强 chemical activity, after introducing the Mg source for treatment, Mg tends to aggregate at the positions of the V-shaped pits during the treatment process. This can flatten the surface of the InGaN quantum well layer 31, reduce the probability of defects or dislocations diffusing into the quantum barrier layer, and improve the crystal quality at the interface between the quantum well and the quantum barrier.

[0037] A p-type GaN layer 33 is also grown on the Mg metal layer 32. The holes generated by the p-type GaN layer 33 can neutralize some of the piezoelectric polarization negative charges at this interface. Reducing the polarization charge density at the interface can reduce the polarization field strength, weaken the piezoelectric polarization field and the quantum-confined Stark effect, and improve the internal quantum efficiency of the light-emitting diode.

[0038] Optionally, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 can be a flat substrate or a patterned substrate.

[0039] As an example, in the embodiments of the present disclosure, the substrate 10 is a sapphire substrate. The sapphire substrate is a commonly used substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat substrate.

[0040] Optionally, the n-type layer 20 can be an n-type GaN layer. The thickness of the n-type layer 20 is 0.5 μm to 3 μm. Among them, the dopant of the n-type layer 20 is silane.

[0041] Optionally, the thickness of the p-type layer 40 is 50 nm to 100 nm. Among them, the dopant of the p-type layer 40 is magnesium cyclopentadienyl.

[0042] Among them, the p-type layer 40 can include a low-temperature p-type AlGaN layer 41, a p-type electron blocking layer 42, a high-temperature p-type GaN layer 43, and a p-type ohmic contact layer 44 that are sequentially stacked on the light-emitting layer 3.

[0043] Exemplarily, the p-type electron blocking layer 42 can be a p-type Al k Ga 1-k N0.2<k<0.5 layer, and the thickness of the p-type electron blocking layer 42 can be 20 nm to 100 nm.

[0044] If the thickness of the p-type electron blocking layer 42 is too thin, the blocking effect on electrons will be reduced. If the thickness of the p-type electron blocking layer 42 is too thick, the absorption of light by the p-type electron blocking layer 42 will increase, resulting in a reduction in the light-emitting efficiency of the LED.

[0045] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer 41 and the high-temperature p-type GaN layer 43 are doped with Mg.

[0046] The Mg doping concentration of the low-temperature p-type AlGaN layer 41 is 5×1019 cm -3 to 1×10 21 cm -3 The Mg doping concentration of the high temperature p-type GaN layer 43 is 5×10 19 cm -3 to 1×10 21 cm -3 .

[0047] The thickness of the low-temperature p-type AlGaN layer 41 may be 50 nm to 100 nm. For example, the thickness of the low-temperature p-type GaN layer 33 may be 80 nm.

[0048] The thickness of the high-temperature p-type GaN layer 43 may be 100 nm to 200 nm. For example, the thickness of the low-temperature p-type GaN layer 43 may be 150 nm.

[0049] Optionally, the thickness of the p-type ohmic contact layer 44 may be 10 nm to 50 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type ohmic contact layer 44 is 20 nm.

[0050] If the p-type ohmic contact layer 44 is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the p-type ohmic contact layer 44 is too thick, it will increase the absorption of light by the p-type ohmic contact layer 44, thereby reducing the luminous efficiency of the LED.

[0051] The p-type ohmic contact layer 44 is doped with Mg, and the Mg doping concentration of the p-type ohmic contact layer 44 is 1×10 20 cm -3 to 1×10 21 cm -3 .

[0052] Alternatively, as Figure 1 As shown, a buffer layer 51 and a non-doped GaN layer 52 are further included between the substrate 10 and the n-type layer 20 . The buffer layer 51 and the non-doped GaN layer 52 are sequentially stacked on the substrate 10 .

[0053] In the embodiment of the present disclosure, the buffer layer 51 may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 950° C. and 1080° C.

[0054] The thickness of the buffer layer 51 may be 0.5 μm to 3 μm. For example, the thickness of the buffer layer 51 may be 2 μm.

[0055] By setting the thickness of the buffer layer 51 within the above range, it is possible to avoid the buffer layer 51 being too thin, which would reduce the crystal quality of the epitaxial layer grown on the thinner buffer layer 51; it is also possible to avoid the buffer layer 51 being too thick, which would increase the buffer layer 51's absorption of light, thereby reducing the luminous efficiency of the epitaxial wafer.

[0056] In the embodiment of the present disclosure, an undoped GaN layer 52 is also grown between the buffer layer 51 and the n-type layer 20. Compared with the substrate 10, since the crystal structure of the undoped GaN layer 52 is similar to that of the n-type layer 20, by providing the undoped GaN layer 52 as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0057] The thickness of the non-doped GaN layer 52 is 0.5 μm to 3 μm. For example, the thickness of the non-doped GaN layer 52 is 2 μm.

[0058] By setting the thickness of the undoped GaN layer 52 within the above range, it is possible to avoid the thickness of the undoped GaN layer 52 being too thin, which would not serve as a transition and reduce the crystal quality of the grown epitaxial layer; it is also possible to avoid the thickness of the undoped GaN layer 52 being too thick, which would increase the absorption of light by the undoped GaN layer 52, thereby reducing the luminous efficiency of the epitaxial wafer.

[0059] Alternatively, as Figure 1 As shown, an AlN layer 53 is further provided between the substrate 10 and the buffer layer 51 . The AlN layer 53 is a coating deposited on the surface of the substrate 10 .

[0060] Illustratively, the thickness of the AlN layer 53 may be 10 nm to 50 nm. For example, the thickness of the AlN layer 53 is 20 nm.

[0061] Optionally, in each active layer 30 , the Mg doping concentration of the p-type GaN layer 33 gradually decreases to 0 in a direction from the InGaN quantum well layer 31 to the GaN quantum barrier layer 34 .

[0062] Since the p-type GaN layer 33 in the active layer 30 is used to generate holes to neutralize part of the piezoelectric polarization negative charge, the concentration of Mg doping in the p-type GaN layer 33 is gradually reduced in the direction from the InGaN quantum well layer 31 to the GaN quantum barrier layer 34, which can gradually weaken the neutralization effect of the p-type GaN layer 33. In this way, the neutralization of the piezoelectric polarization negative charge can be reduced in the area away from the InGaN quantum well layer 31, so as to avoid affecting the recombination rate of electrons and holes in the light-emitting layer 3 and ensure the light-emitting effect of the light-emitting diode.

[0063] Optionally, the Mg doping concentration of the region with the highest Mg doping concentration in the p-type GaN layer 33 is 1×10 17 cm -3to 1×10 19 cm -3 .

[0064] By controlling the maximum Mg doping concentration of the p-type GaN layer 33 within the above range, it is possible to avoid setting the Mg doping concentration of the p-type GaN layer 33 too low, thereby failing to neutralize part of the piezoelectric polarization negative charge; it is also possible to avoid setting the Mg doping concentration of the p-type GaN layer 33 too high, thereby increasing the production cost.

[0065] Optionally, the thickness of the p-type GaN layer 33 is 2 angstroms to 20 angstroms. Exemplarily, the thickness of the p-type GaN layer 33 is 10 angstroms.

[0066] Optionally, the thickness of the InGaN quantum well layer 31 is 2 nm to 5 nm, and the thickness of the GaN quantum barrier layer 34 is 8 nm to 20 nm.

[0067] By controlling the thickness of the InGaN quantum well layer 31 and the GaN quantum barrier layer 34 within the above range, it is possible to avoid setting the thickness of the InGaN quantum well layer 31 and the GaN quantum barrier layer 34 too thin to achieve the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the InGaN quantum well layer 31 and the GaN quantum barrier layer 34 too thick to increase the production cost.

[0068] For example, the thickness of the InGaN quantum well layer 31 may be 3 nm, and the thickness of the GaN quantum barrier layer 34 may be 10 nm.

[0069] Optionally, the number of active layers 30 is 7 to 15 layers.

[0070] By controlling the number of active layers 30 within the above range, it is possible to avoid setting the number of active layers 30 too small, which would result in the thickness of the light-emitting layer 3 being too small and failing to meet the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the light-emitting layer 3 too thick and increasing the production cost.

[0071] For example, the number of layers of the active layer 30 may be ten.

[0072] It should be noted that Figure 1 Only a part of the structure of the light emitting layer 3 is shown, and it is not intended to limit the number of cycles of alternately stacked quantum well layers and quantum barrier layers.

[0073] Figure 2 This is a flow chart of a method for preparing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present disclosure. Figure 1 The epitaxial wafer shown. Figure 2 As shown, the preparation method comprises:

[0074] S11: providing a substrate.

[0075] S12: growing an n-type layer, a light-emitting layer, and a p-type layer in sequence on the substrate.

[0076] Among them, an n-type layer, a light-emitting layer and a p-type layer are grown in sequence on the substrate. The light-emitting layer includes multiple stacked active layers. Each active layer includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer and a GaN quantum barrier layer stacked in sequence. Before forming the p-type GaN layer, an Mg source is introduced into the reaction chamber to perform surface treatment on the InGaN quantum well layer, and a Mg metal layer is formed in the pits on the surface of the InGaN quantum well layer.

[0077] The light-emitting layer of the epitaxial wafer produced by this method includes multiple stacked active layers, each of which includes an InGaN quantum well layer, an Mg metal layer, a p-type GaN layer, and a GaN quantum barrier layer stacked in sequence. The Mg metal layer is formed on the surface of the InGaN quantum well layer by introducing an Mg source.

[0078] In this way, the characteristic that Mg tends to be enriched near the dislocation center with strong chemical activity is utilized. After the Mg source is introduced for treatment, Mg tends to accumulate at the position of the V-shaped pit during the treatment process. This can restore the surface of the InGaN quantum well layer to be smooth, reduce the probability of defects or dislocations diffusing to the quantum barrier layer, and improve the crystal quality at the interface between the quantum well and the quantum barrier.

[0079] A p-type GaN layer is also grown on the Mg metal layer. The holes generated by the p-type GaN layer can neutralize part of the piezoelectric polarization negative charge at this interface. Reducing the polarization charge density at the interface can reduce the polarization field strength, weaken the piezoelectric polarization field and quantum confined Stark effect, and improve the internal quantum efficiency of the light-emitting diode.

[0080] In step S11, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0081] As an example, in the embodiments of the present disclosure, the substrate is a sapphire substrate. Sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0082] In step S11 , the sapphire substrate may be subjected to a high-temperature cleaning treatment in a hydrogen atmosphere at 1000° C. to 1200° C. for 5 to 20 minutes, and then subjected to a nitriding treatment.

[0083] In step S11, the sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0084] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0085] The following steps may also be included before step S12:

[0086] In the first step, an AlN layer is grown on the substrate.

[0087] Specifically, a sapphire substrate is placed in a physical vapor deposition (PVD) device to deposit an AlN layer by magnetron sputtering.

[0088] The growth temperature in the PVD equipment is 400° C. to 800° C., the sputtering power is 3000W to 5000W, the pressure is 2mtorr to 20mtorr, and the AlN layer deposition thickness is 10nm to 50nm.

[0089] In the second step, a buffer layer is grown on the AlN layer.

[0090] In the embodiment of the present disclosure, the buffer layer may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 950°C and 1080°C.

[0091] The thickness of the buffer layer may be 0.5 μm to 3 μm. For example, the thickness of the buffer layer may be 2 μm.

[0092] Specifically, the AlN-coated substrate is placed in an MOCVD system to grow a buffer layer. The MOCVD reaction chamber temperature is between 950°C and 1080°C, the reaction chamber pressure is controlled between 200 Torr and 500 Torr, and the growth atmosphere is a mixture of nitrogen, hydrogen, and ammonia. The buffer layer is grown to a thickness of 0.3 μm to 0.5 μm.

[0093] The third step is to grow an undoped GaN layer on the buffer layer.

[0094] In the embodiment of the present disclosure, an undoped GaN layer is also grown between the buffer layer and the n-type layer. Compared with the substrate, since the crystal structure of the undoped GaN layer is similar to that of the n-type layer, by providing the undoped GaN layer as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0095] The thickness of the non-doped GaN layer is 0.5 μm to 3 μm. For example, the thickness of the non-doped GaN layer is 2 μm.

[0096] Specifically, an undoped GaN buffer recovery layer is grown by MOCVD in an MOCVD system with a temperature adjusted to 1000° C. to 1100° C. and a growth pressure of 100 Torr to 300 Torr, to grow an undoped GaN layer with a thickness of 0.5 μm to 3 μm.

[0097] Step S12 may include the following steps:

[0098] In the first step, an n-type layer is grown on the undoped GaN layer.

[0099] Optionally, the n-type layer may be an n-type GaN layer, the thickness of the n-type layer is 0.5 μm to 3 μm, and the dopant of the n-type layer is silane.

[0100] Specifically, in an MOCVD system with a temperature of 1000°C to 1100°C and a growth pressure of 100 Torr to 300 Torr, an n-type doped GaN layer with a thickness of 0.5 μm to 3 μm is grown, and the concentration of Si doped in the n-type GaN layer is 1×10 18 cm -3 to 1×10 19 cm -3 .

[0101] In the second step, a light-emitting layer is grown on the n-type layer.

[0102] Among them, the optical layer includes multiple stacked active layers, each active layer includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer and a GaN quantum barrier layer stacked in sequence, and the Mg metal layer is an Mg metal layer formed on the surface of the InGaN quantum well layer by introducing an Mg source.

[0103] Optionally, the number of layers of the active layer is 7 to 15. For example, the number of layers of the active layer may be 10.

[0104] The following is an example of the growth process of one of the active layers:

[0105] First, grow an InGaN quantum well layer under a mixed atmosphere of ammonia and nitrogen, at a growth temperature of 700 °C to 830 °C and a growth pressure of 100 Torr to 300 Torr, to grow an InGaN quantum well layer with a thickness of 2 nm to 5 nm.

[0106] Then, introduce a Mg source into the reaction chamber, with a flow rate of the Mg source being 50 sccm to 500 sccm, the duration of introducing the Mg source being 5 s to 30 s, a growth temperature of 750 °C to 810 °C, a growth pressure of 200 Torr to 500 Torr, and a growth atmosphere being a mixed atmosphere of ammonia, nitrogen, and hydrogen, to form a Mg metal layer on the surface of the InGaN quantum well layer.

[0107] Next, grow a Mg-doped p-type GaN layer with a thickness of 2 Å to 20 Å, at a growth temperature of 800 °C to 880 °C, a growth pressure of 200 torr to 500 torr, and a growth atmosphere being a mixed atmosphere of ammonia, nitrogen, and hydrogen.

[0108] Among them, in the direction from the InGaN quantum well layer to the GaN quantum barrier layer, the Mg doping concentration gradually decreases to zero. The Mg doping concentration in the region with the highest Mg doping concentration in the p-type GaN layer 33 is 1×10 17 cm -3 to 1×10 19 cm -3 .

[0109] Finally, when growing the GaN quantum barrier layer, control the growth temperature to be 800 °C to 960 °C, the growth pressure to be 100 Torr to 300 Torr, and grow a GaN quantum barrier layer with a thickness of 8 nm to 20 nm.

[0110] The third step is to grow a p-type layer on the light-emitting layer.

[0111] Optionally, the thickness of the p-type layer is 30 nm to 120 nm. Among them, the dopant of the p-type layer is magnesium bis(cyclopentadienyl).

[0112] Among them, the p-type layer may include a low-temperature p-type AlGaN layer, a p-type electron blocking layer, a high-temperature p-type GaN layer, and a p-type ohmic contact layer that are sequentially stacked on the light-emitting layer.

[0113] Exemplarily, the p-type electron blocking layer may be a p-type Al k Ga 1-k N(0.2 < k < 0.5) layer, and the thickness of the p-type electron blocking layer may be 20 nm to 100 nm.

[0114] If the thickness of the p-type electron blocking layer is too thin, the blocking effect on electrons will be reduced. If the thickness of the p-type electron blocking layer is too thick, the absorption of light by the p-type electron blocking layer will increase, resulting in a decrease in the light-emitting efficiency of the LED.

[0115] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer and the high-temperature p-type GaN layer are doped with Mg.

[0116] The Mg doping concentration of the low-temperature p-type AlGaN layer is 5×10 19 cm -3 to 1×10 21 cm -3 The Mg doping concentration of the high-temperature p-type GaN layer is 5×10 19 cm -3 to 1×10 21 cm -3 .

[0117] Among them, the thickness of the low-temperature p-type AlGaN layer can be 50 nm to 100 nm. For example, the thickness of the low-temperature p-type GaN layer can be 80 nm. <{

[0118] Among them, the thickness of the high-temperature p-type GaN layer can be 100 nm to 200 nm. For example, the thickness of the low- and high-temperature p-type GaN layer can be 150 nm.

[0119] Optionally, the thickness of the p-type ohmic contact layer can be 10 nm to 50 nm. As an example, in the embodiments of the present disclosure, the thickness of the p-type ohmic contact layer is 20 nm.

[0120] If the thickness of the p-type ohmic contact layer is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the thickness of the p-type ohmic contact layer is too thick, the absorption of light by the p-type ohmic contact layer will increase, resulting in a decrease in the light-emitting efficiency of the LED.

[0121] Among them, the p-type ohmic contact layer is doped with Mg, and the Mg doping concentration of the p-type ohmic contact layer is 1×10 20 cm -3 to 1×10 21 cm -3 .

[0122] When growing the low-temperature p-type AlGaN layer, adjust the growth temperature to 700 °C to 800 °C, and grow the low-temperature p-type AlGaN layer with a thickness of 50 nm to 100 nm under an environment with a growth pressure of 200 Torr to 500 Torr.

[0123] Among them, the low-temperature p-type AlGaN layer is an Al w Ga 1-w N(0.1 < w < 0.3) layer, and the Mg doping concentration is 5×1019 cm -3 to 1×10 21 cm -3 。

[0124] When growing the p-type electron blocking layer, adjust the growth temperature to 800 °C to 1000 °C, and grow it under the environment of a growth pressure of 100 Torr to 300 Torr. The p-type electron blocking layer can be an Al k Ga 1-k N layer, where 0.2 < k < 0.5 and the thickness is 20 nm to 100 nm.

[0125] When growing the high-temperature p-type GaN layer, control the growth pressure under the environment of 200 Torr to 600 Torr, the growth temperature is 800 °C to 1000 °C, and grow a p-type GaN layer with a growth thickness of 100 nm to 200 nm, and the Mg doping concentration is 5×10 19 cm -3 to 1×10 21 cm -3 。

[0126] When growing the p-type ohmic contact layer, adjust the growth temperature to 850 °C to 1000 °C, and grow a p-type ohmic contact layer with a thickness of 10 nm to 50 nm on the high-temperature p-type GaN layer under the environment of a growth pressure of 100 torr to 300 torr. The Mg doping concentration is 1×10 20 cm -3 to 1×10 21 cm -3 。

[0127] After step S12, the preparation method may further include: annealing the epitaxial wafer.

[0128] After the epitaxial growth is completed, lower the temperature of the reaction chamber to 650 °C to 850 °C, perform annealing treatment in an N2 atmosphere for 5 min to 1 min, and then gradually lower it to room temperature. Subsequently, the chip is made through subsequent processing technologies such as cleaning, deposition, photolithography, and etching.

[0129] In specific implementation, the embodiments of the present disclosure may use high-purity H2 or / and N2 as the carrier gas, use TEGa or TMGa as the Ga source, TMIn as the In source, SiH4 as the n-type dopant, TMAl as the aluminum source, ammonia gas as the N source, and Cp2Mg as the p-type dopant.

[0130] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A method for preparing an epitaxial wafer of a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; An n-type layer, a light-emitting layer, and a p-type layer are sequentially grown on the substrate. The light-emitting layer includes a plurality of stacked active layers, each of which includes an InGaN quantum well layer, a Mg metal layer, a p-type GaN layer, and a GaN quantum barrier layer stacked in sequence. Before forming the p-type GaN layer, an Mg source is introduced into a reaction chamber to perform surface treatment on the InGaN quantum well layer, forming the Mg metal layer in pits on the surface of the InGaN quantum well layer. Utilizing the characteristic that Mg tends to be enriched near chemically active dislocation centers, after the introduction of the Mg source treatment, Mg tends to accumulate at the position of the V-shaped pit during the treatment process, thereby restoring the surface of the InGaN quantum well layer to a smooth surface. Holes generated in the p-type GaN layer are used to neutralize the piezoelectric polarization negative charge, thereby reducing the polarization charge density.

2. The preparation method according to claim 1, characterized in that The Mg metal layer is formed in the following manner: The flow rate of the Mg source is 50 sccm to 500 sccm, the time of the Mg source introduction is 5s to 30s, the growth temperature is 750°C to 810°C, the growth pressure is 200 Torr to 500 Torr, and the growth atmosphere is a mixed atmosphere of ammonia, nitrogen and hydrogen.

3. The preparation method according to claim 1, characterized in that When growing the InGaN quantum well layer, the growth temperature is 700° C. to 830° C., the growth pressure is 100 Torr to 300 Torr, and the growth atmosphere is a mixed atmosphere of ammonia and nitrogen.

4. The preparation method according to claim 1, characterized in that When growing the p-type GaN layer, the growth temperature is 800° C. to 880° C., the growth pressure is 200 Torr to 500 Torr, and the growth atmosphere is a mixed atmosphere of ammonia, nitrogen, and hydrogen.

5. The preparation method according to claim 1, characterized in that When growing the GaN quantum barrier layer, the growth temperature is 800° C. to 960° C., and the growth pressure is 100 Torr to 300 Torr.

6. An epitaxial wafer of a light emitting diode, characterized in that: The epitaxial wafer comprises a substrate (10) and an n-type layer (20), a light-emitting layer (3), and a p-type layer (40) sequentially formed on the substrate (10); The light-emitting layer (3) includes a plurality of stacked active layers (30), each of the active layers (30) including an InGaN quantum well layer (31), a Mg metal layer (32), a p-type GaN layer (33) and a GaN quantum barrier layer (34). The InGaN quantum well layer (31), the p-type GaN layer (33) and the GaN quantum barrier layer (34) are stacked in sequence. A surface of the InGaN quantum well layer (31) close to the p-type GaN layer (33) has a pit (330), and the Mg metal layer (32) is filled in the pit (330). Utilizing the characteristic that Mg tends to be enriched near a dislocation center with strong chemical activity, after a Mg source is introduced for treatment, Mg tends to be concentrated at the position of the V-shaped pit during the treatment process, so that the surface of the InGaN quantum well layer is restored to be flat. The holes generated by the p-type GaN layer are utilized to neutralize the piezoelectric polarization negative charge, thereby reducing the polarization charge density.

7. The epitaxial wafer according to claim 6, characterized in that: In each active layer (30), the Mg doping concentration of the p-type GaN layer (33) gradually decreases to 0 in a direction from the InGaN quantum well layer (31) to the GaN quantum barrier layer (34).

8. The epitaxial wafer according to claim 7, characterized in that: The Mg doping concentration of the region with the highest Mg doping concentration in the p-type GaN layer (33) is 1×10 17 cm -3 to 1×10 19 cm -3 .

9. The epitaxial wafer according to claim 6, characterized in that: The thickness of the p-type GaN layer (33) is 2 angstroms to 20 angstroms.

10. The epitaxial wafer according to any one of claims 6 to 9, characterized in that: The thickness of the InGaN quantum well layer (31) is 2 nm to 5 nm, and the thickness of the GaN quantum barrier layer (34) is 8 nm to 20 nm.

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