Chip state monitoring circuit based on self-balancing differential signal integral amplification circuit

Abstract

The application discloses a chip state monitoring circuit based on a self-balanced differential signal integral amplification circuit, and relates to the technical field of chips.The chip state monitoring circuit is built in a chip, can sense a state signal of the chip, and transmit the state signal to a chip configuration circuit after amplification and analog-digital conversion, so that the chip configuration circuit can perform state monitoring and timely feedback or response, thereby improving the reliability and service life of the chip.A brand-new self-balanced differential signal integral amplification circuit is used in the chip state monitoring circuit, through a built-in positive coefficient integral network and a negative coefficient balance network, the self-balanced differential signal integral amplification circuit can enter a self-balanced stable state after being amplified to a required multiple, thereby realizing fixed multiple amplification, without timing reading, and the control mode is simple and flexible.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip status monitoring circuit based on a self-balancing differential signal integrating amplifier circuit. Background Technology

[0002] SRAM-based programmable logic devices are designed based on reconfigurable SRAM memory technology. By configuring the circuit logic, different functions can be realized by the user, and they are widely used in various fields and scenarios.

[0003] Applications of SRAM-based programmable logic devices often have high reliability requirements. However, with the increase in internal logic resource usage, processing speed, and power consumption, SRAM-based programmable logic devices are prone to various operational failures during operation, making it difficult to guarantee operational reliability. Summary of the Invention

[0004] To address the aforementioned problems and technical requirements, the applicant proposes a chip status monitoring circuit based on a self-balancing differential signal integrating amplifier circuit. The technical solution of this application is as follows:

[0005] A chip status monitoring circuit based on a self-balancing differential signal integrating amplifier circuit is characterized in that the chip status monitoring circuit includes a status sensing circuit, a self-balancing differential signal integrating amplifier circuit, and an analog-to-digital converter connected in sequence. The analog-to-digital converter is connected to the chip configuration circuit inside the chip, and the status sensing circuit is set at the detection point inside the chip and senses the differential status signal of the chip.

[0006] The self-balancing differential signal integrating amplifier circuit includes a fully differential operational amplifier, a positive coefficient integrating network, and a negative coefficient balancing network. Both networks are connected between the input and output terminals of the fully differential operational amplifier. Under the action of the positive coefficient integrating network, the fully differential operational amplifier amplifies the state signal. Under the action of the negative coefficient balancing network, the amplification of the signal is reversed. The reverse adjustment function of the negative coefficient balancing network gradually increases until the self-balancing differential signal integrating amplifier circuit reaches self-balance, so that the output signal of the self-balancing differential signal integrating amplifier circuit is stabilized as the state signal amplified by K times.

[0007] The state signal, amplified by a factor of K, is converted from analog to digital by an analog-to-digital converter and then output to the chip configuration circuit.

[0008] The beneficial technical effects of this application are:

[0009] This application discloses a chip status monitoring circuit based on a self-balancing differential signal integrating amplifier circuit. This chip status monitoring circuit, built into the chip, can monitor the chip's status and provide timely feedback or response, thereby improving the chip's reliability and lifespan. The chip status monitoring circuit internally uses a novel self-balancing differential signal integrating amplifier circuit. Through the built-in positive coefficient integrating network and negative coefficient balancing network, they interact to allow the self-balancing differential signal integrating amplifier circuit to amplify to the required factor and then enter a self-balancing stable state, thus achieving fixed-factor amplification without the need for periodic readings, resulting in a simple and flexible control method.

[0010] The amplification factor achieved by this self-balancing differential signal integrating amplifier circuit in a stable state is related to the capacitance values ​​of the sampling capacitor and the balancing capacitor. Therefore, the stable amplification factor can be adjusted by adjusting the ratio of the sampling capacitor and the balancing capacitor. The amplification factor adjustment is highly accurate and the adjustment method is precise and flexible.

[0011] The self-balancing differential signal integrating amplifier circuit has a simple circuit structure, requires no complex external circuits, and does not occupy too much chip area and chip resources, making it suitable for chip applications. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the circuit connection of the chip status monitoring circuit in the chip according to one embodiment of this application.

[0013] Figure 2 This is a circuit diagram of a self-balancing differential signal integrating amplifier circuit in a chip status monitoring circuit according to one embodiment of this application.

[0014] Figure 3 yes Figure 2 The timing diagram of the control signals of each switch.

[0015] Figure 4 This is a graph showing the voltage variation of the output signal of the self-balancing differential signal integrating amplifier circuit in this application, and a graph showing the change of the amount of charge transferred from the sampling capacitor to the two networks with the sampling period. Detailed Implementation

[0016] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0017] This application discloses a chip status monitoring circuit based on a self-balancing differential signal integrating amplifier circuit. The chip can be an FPGA chip or an ASIC chip, such as an SRAM-type FPGA. The chip status monitoring circuit includes a status sensing circuit, a self-balancing differential signal integrating amplifier circuit, and an analog-to-digital converter connected in sequence. The analog-to-digital converter is connected to the chip's internal chip configuration circuit. Please refer to... Figure 1The schematic diagram of the chip's internal structure shown illustrates how adding a chip status monitoring circuit to the existing chip architecture can monitor the chip's operational status, thereby ensuring its reliability. It should be noted that... Figure 1 The diagram only schematically illustrates the connection between the chip status monitoring circuit and the chip configuration circuit when the chip status monitoring circuit is located inside the chip, and does not represent the actual location of the chip status monitoring circuit inside the chip or the chip area it occupies.

[0018] The state sensing circuit is located at the detection point inside the chip and senses the differential state signal of the chip. A self-balancing differential signal integrating amplifier circuit amplifies the sensed state signal, and the amplified state signal is then converted from analog to digital by an analog-to-digital converter and output to the chip configuration circuit. The chip configuration circuit can provide timely feedback or respond upon receiving the state signal. The state sensing circuit can be various types of sensors, and the sensed state signal can be various important operating parameters of the chip.

[0019] For example, in a typical application, the target chip is an SRAM-type FPGA, and the status sensing circuit is a temperature sensor. The sensed status signal is a temperature signal. During chip operation, excessive heat accumulation can easily cause thermal or electrical breakdown. Since SRAM-type FPGAs cannot retain their data after power failure, monitoring the temperature signal during SRAM-type FPGA operation has significant application value. Consequently, the chip configuration circuit can adjust the chip's main operating frequency in a timely manner, effectively protecting the SRAM-type FPGA from high temperatures, thereby improving the chip's reliability and lifespan. This principle also applies to other important operating parameters besides temperature.

[0020] In this chip status monitoring circuit, the sensed status signal is generally a small AC signal in differential form, so a differential signal integrating amplifier circuit is needed to amplify the status signal. Conventional differential signal integrating amplifier circuits amplify the differential signal at a fixed period, integrating until the circuit reaches its maximum output swing. This requires periodic reading of the amplified signal, making control difficult and the amplification factor hard to adjust. Moreover, conventional differential signal integrating amplifier circuits have the problem of complex peripheral circuitry, occupying more chip resources and chip area, making them difficult to apply in scenarios with high integration requirements, such as chips. Therefore, the chip status monitoring circuit of this application cannot directly use existing common differential signal integrating amplifier circuits.

[0021] To meet the internal requirements of the chip, this application employs a novel self-balancing differential signal integrating amplifier circuit. This circuit includes a fully differential operational amplifier, a positive coefficient integrating network, and a negative coefficient balancing network, with both networks connected between the input and output terminals of the fully differential operational amplifier. The fully differential operational amplifier amplifies the state signal under the action of the positive coefficient integrating network and performs inverse regulation of the amplification under the action of the negative coefficient balancing network. The self-balancing differential signal integrating amplifier circuit as a whole amplifies the state signal, but the inverse regulation function implemented by the negative coefficient balancing network gradually strengthens until it eventually reaches self-balance with the amplification factor, causing the output signal of the self-balancing differential signal integrating amplifier circuit to eventually stabilize and output a state signal amplified by K times.

[0022] The changes in the signal amplification and inverse regulation functions of the two networks are achieved through the following method: This self-balancing differential signal integrating amplifier circuit also includes a sampling network, which samples the charge of the state signal, and the sampled charge is transferred to the two networks:

[0023] Before the self-balancing differential signal integrating amplifier circuit reaches self-balancing, a portion of the charge sampled by the sampling network is transferred to the positive coefficient integrating network to achieve signal amplification. Another portion of the charge sampled by the sampling network is transferred to the negative coefficient balancing network to achieve reverse adjustment of the signal amplification. The overall signal amplification effect is stronger than the reverse adjustment effect, thus the output signal of the self-balancing differential signal integrating amplifier circuit gradually increases. As the output signal of the fully differential operational amplifier increases, the charge transferred from the sampling network to the negative coefficient balancing network gradually increases, thereby gradually enhancing the reverse adjustment function implemented by the negative coefficient balancing network.

[0024] Once the self-balancing differential signal integrating amplifier circuit reaches self-balance, all the charges sampled by the sampling network are transferred to the negative coefficient balancing network, making the output signal of the self-balancing differential signal integrating amplifier circuit stable as the state signal after being amplified by K times.

[0025] In practice, a self-balancing differential signal integrating amplifier circuit operates periodically, with the output signal gradually increasing. Within each sampling period, the circuit sequentially goes through a sampling phase, an integration phase, and a hold phase, causing the output signal to increase until it reaches stability after several sampling periods. The working process is as follows:

[0026] During each sampling period before the self-balancing differential signal integrating amplifier circuit reaches self-balancing: (1) During the sampling phase, the sampling network samples the charge of the state signal. (2) During the integration phase, the fully differential operational amplifier starts working, and the sampling network transfers the sampled charge to the positive coefficient integrating network and the negative coefficient balancing network according to the process described above, thereby increasing the output signal of the self-balancing differential signal integrating amplifier circuit. (3) During the hold phase, the output signal of the fully differential operational amplifier remains unchanged.

[0027] As the sampling period progresses, the charge transferred from the sampling network to the integration network and the balancing network during the integration phase of different sampling periods is not fixed. The charge transferred from the sampling network to the negative coefficient balancing network increases with the increase of the output signal of the fully differential operational amplifier. This causes the reverse adjustment function implemented by the negative coefficient balancing network to gradually increase with the sampling period until it finally reaches balance with the amplification function implemented by the positive coefficient integration network. This allows the self-balancing differential signal integration amplifier circuit to reach self-balancing after several sampling periods. In each sampling period after the self-balancing differential signal integration amplifier circuit reaches self-balancing: (1) During the sampling phase, the sampling network also samples the charge of the state signal. (2) During the integration phase, the fully differential operational amplifier starts working, and the sampling network transfers all the sampled charge to the negative coefficient balancing network, so that the output signal of the self-balancing differential signal integration amplifier circuit remains unchanged. (3) During the hold phase, the output signal of the fully differential operational amplifier remains unchanged.

[0028] The sampling network is based on the sampling capacitor C s Construct a positive coefficient integral network based on the integral capacitor C. fp Constructing a negative coefficient balancing network based on the balancing capacitor C fn Setup. Please combine... Figure 2 The circuit diagram shown is of a self-balancing differential signal integrating amplifier circuit in one embodiment. The circuit structure of this self-balancing differential signal integrating amplifier circuit is simple and requires no complex external circuitry. This self-balancing differential signal integrating amplifier circuit also includes a common-mode signal generation circuit. The common-mode signal generation circuit is connected to the common-mode signal terminal Com of the fully differential operational amplifier U1, which provides a voltage value of V. com In one embodiment, the common-mode signal generation circuit is implemented by a voltage divider circuit consisting of resistors R1 and R2.

[0029] The positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier U1 are connected to a first circuit structure, and the negative input terminal In and the positive output terminal Op of the fully differential operational amplifier U1 are connected to a second circuit structure. The first circuit structure and the second circuit structure are symmetrical and have the same operation process. Each circuit structure includes a sampling network, a positive coefficient integration network and a negative coefficient balancing network.

[0030] In each sampling period of the self-balancing differential signal integrating amplifier circuit, (1) during the sampling phase, the sampling network in the first circuit structure is connected to the positive differential input terminal V of the self-balancing differential signal integrating amplifier circuit. inp Sampling is performed; the sampling network in the second circuit structure is connected to the negative differential input terminal V of the self-balancing differential signal integrating amplifier circuit. inn (2) During the integration phase, the sampling network in the first circuit structure is switched to the negative differential input terminal V of the self-balancing differential signal integrating amplifier circuit. inn The sampling network in the second circuit structure is connected to the positive differential input terminal V of the self-balancing differential signal integrating amplifier circuit. inp Thus, the changing voltage difference across the sampling capacitor in each sampling network transfers the sampled charge to the two networks in the circuit structure.

[0031] Please combine Figure 2 In the first circuit structure, the sampling capacitor C in the sampling network s The upper plate is connected to the positive differential input terminal V of the self-balancing differential signal integrating amplifier circuit via switch S6. inp Sampling capacitor C s The upper plate is also connected to the negative differential input terminal V of the self-balancing differential signal integrating amplifier circuit via switch S7. inn Sampling capacitor C s The lower plate is connected to the balancing capacitor C in the negative coefficient balancing network. fn The lower electrode plate, balancing capacitor C fn The upper plate is connected to the negative output terminal On of the fully differential operational amplifier via switch S1. The balancing capacitor C... fn The upper plate is also connected to the common-mode signal terminal Com of the fully differential operational amplifier via switch S2. Sampling capacitor C s The lower electrode is also connected to the integrating capacitor C in the positive coefficient integrating network via switch S3. fp The lower electrode, integrating capacitor C fp The upper plate is connected to the negative output terminal On of the fully differential operational amplifier via switch S4. Integrating capacitor C fp The lower plate is also connected to the positive input terminal Ip of the fully differential operational amplifier, and the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier are also connected by switch S5.

[0032] The second circuit structure is symmetrical to the first circuit structure. Figure 2 Using the same reference numerals, in the second circuit structure, the sampling capacitor C in the sampling network... s The upper electrode plate is connected to the negative differential input terminal V via switch S6. inn Sampling capacitor C s The upper electrode plate is also connected to the positive differential input terminal V via switch S7.inp Sampling capacitor C s The lower plate is connected to the balancing capacitor C in the negative coefficient balancing network. fn The lower electrode plate, balancing capacitor C fn The upper plate is connected to the positive output terminal Op of the fully differential operational amplifier via switch S1. The balancing capacitor C... fn The upper plate is also connected to the common-mode signal terminal Com of the fully differential operational amplifier via switch S2. Sampling capacitor C s The lower electrode is also connected to the integrating capacitor C in the positive coefficient integrating network via switch S3. fp The lower electrode, integrating capacitor C fp The upper plate is connected to the positive output terminal Op of the fully differential operational amplifier via switch S4. Integrating capacitor C fp The lower plate is also connected to the negative input terminal In of the fully differential operational amplifier, and the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier are also connected by switch S5.

[0033] In both circuit structures, switch S1 is controlled by control signal ctrl1, switches S2, S5 and S6 are all controlled by control signal ctrl2, switch S3 is controlled by control signal ctrl3, and switches S4 and S7 are controlled by control signal ctrl4.

[0034] based on Figure 2 Please refer to the circuit diagram shown. Figure 3 The control timing sequence of each control signal for the corresponding switch is shown. Figure 2 ,as well as Figure 4 The voltage change value shown illustrates the operation of this self-balancing differential signal integrating amplifier circuit. Since the first and second circuit structures are symmetrical and operate identically, the operation of the first circuit structure within each sampling period is described below:

[0035] (1) During the sampling phase, control signal ctrl2 controls switches S2, S5 and S6 to close, control signal ctrl3 controls switch S3 to close, control signal ctrl1 controls switch S1 to open, and control signal ctrl4 controls switches S4 and S7 to open.

[0036] Because switch S5 is closed, the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier U1 are shorted, and the negative input terminal In and the positive output terminal Op are shorted. The value generated after the shorting is connected to the sampling capacitor C through the path F→D→B. s The lower plate is simultaneously connected to the balancing capacitor C. fn The lower electrode plate.

[0037] Since switch S6 is closed and switch S7 is open, the sampling capacitor C in the first circuit structure... sThe upper electrode is connected to the positive differential input terminal V. inp Therefore, the sampling capacitor C s The sampled charge is C s Sampling capacitor C s The capacitance value.

[0038] Balance capacitor C fn The upper plate is connected to the output terminal of the common-mode signal generation circuit, and the voltage value is V. com Therefore, the balancing capacitor C fn The charge in V Ip It is the voltage value at the positive input terminal Ip of the fully differential operational amplifier, C. fn For the balancing capacitor C fn The capacitance value. Because the positive input terminal Ip and the negative output terminal On are shorted, V com =V Ip =V On ,therefore V Ip It is the voltage value at the positive input terminal Ip of the fully differential operational amplifier, V. On It is the voltage value at the negative output terminal On of the fully differential operational amplifier.

[0039] Since switches S1 and S4 are open, the integrating capacitor C... fp The charge in the sample remains unchanged, taking over the charge from the previous sampling period.

[0040] (2) During the integration phase, control signal ctrl2 controls switches S2, S5 and S6 to open, control signal ctrl3 controls switch S3 to close, control signal ctrl1 controls switch S1 to close, and control signal ctrl4 controls switches S4 and S7 to close.

[0041] With switch S5 open, the fully differential operational amplifier starts working, and the sampling capacitor C in the first circuit structure... s The upper electrode plate is switched to connect to the negative differential input terminal V. inn At this time, the sampling capacitor C s The sampled charge becomes V inn It is the negative differential input terminal V inn The voltage value. Switching from the sampling phase to the integration phase, the sampling capacitor C... s The changing voltage difference causes the sampling capacitor C to... s The sampled charge is transferred to the balancing capacitor C. fn and integrating capacitor C fp Above, the transferred charge is

[0042] Sampling capacitor Cs The lower electrode plate and the balancing capacitor C fn The lower plate and integrating capacitor C fp The lower plate is connected to and then to the positive input terminal Ip of the fully differential operational amplifier. The balancing capacitor C... fn The upper plate and the integrating capacitor C fp The upper plate is connected to and connected to the negative output terminal On of the fully differential operational amplifier.

[0043] Therefore, the balancing capacitor C at this time fn The charge in becomes Due to the balancing capacitor C fn The charge change in the sample is caused by the sampling capacitor C s This is caused by charge transfer, so the sampling capacitance C can be determined. s The balancing capacitance C transferred to the negative coefficient balancing network fn The charge is

[0044] The sampling capacitor C can be further determined. s The integrating capacitor C transferred to the positive coefficient integral network fp The charge is ΔQ fp =ΔQ s -ΔQ fn =(V inn -V inp )*C s -(V On -V Ip )*C fn .

[0045] (3) During the holding phase, control signal Ctrl2 opens switches S2, S5, and S6; control signal Ctrl3 opens switch S3; control signal Ctrl1 opens switch S1; and control signal Ctrl4 closes switches S4 and S7. Integrating capacitor C fp The two ends are connected to the input and output terminals of the fully differential operational amplifier, respectively. The fully differential operational amplifier keeps the output signal constant, and the integrating capacitor C... fp The charge remains unchanged until the next sampling period.

[0046] Based on the working process described above, it can be determined that when ΔQ s and ΔQ fn In each sampling period before the self-balancing differential signal integrating amplifier circuit reaches self-balancing, when switching to the integration stage, the sampling capacitor C... s Charge is transferred to both networks, and the amount of charge transferred to each network is as described above. Furthermore, the output signal V of the fully differential operational amplifier changes with the sampling period. On and V OpIncrease, thereby causing the sampling capacitor C s During the sampling phase, the capacitance is transferred to the balancing capacitor C. fn The charge ΔQ fn The reverse regulation function achieved by increasing the negative coefficient balancing network is enhanced.

[0047] Until after several sampling periods, ΔQ fn Increase to the level of ΔQ s When the values ​​are equal, the self-balancing differential signal integrating amplifier circuit reaches self-balancing. In each subsequent sampling period, the sampling capacitor C... s The charge ΔQ transferred to the two networks s All transferred to the balancing capacitor C fn In, instead of transferring to the integrating capacitor C fp This ensures that the output signal of the self-balancing differential signal integrating amplifier circuit is stabilized to the state signal after being amplified by K times. For example... Figure 4 As shown, the voltage of the state signal obtained from the differential input terminal is set to V. inp -V inn If the sampling period increases gradually with the input period, the output signal of the self-balancing differential signal integrating amplifier circuit will eventually stabilize at V. Op -V On After K×ΔV, the output signal of the self-balancing differential signal integrating amplifier circuit no longer changes with the sampling period, achieving a stable output effect.

[0048] Please refer to Figure 4 The sampling capacitor C shown s The amount of charge ΔQ transferred to the two networks s A diagram illustrating the change in sampling period, from Figure 4 It can be seen that as the sampling period increases, the sampling capacitance C... s Transferred to integrating capacitor C fp The charge ΔQ fp Gradually decrease the sampling capacitor C s Transferred to balancing capacitor C fn The charge ΔQ fn Gradually increase until ΔQ is reached. s During subsequent sampling periods, the balancing capacitor C is transferred to the negative coefficient balancing network. fn The charge ΔQ fn All are ΔQ s The transfer is to the integrating capacitor C. fp The charge ΔQ fp All are 0.

[0049] Furthermore, the amplification factor K of the self-balancing differential signal integrating amplifier circuit to the steady-state state signal is determined by the sampling capacitor C. s The capacitance value and balancing capacitor Cfn The capacitance value is determined by this. Please refer to... Figure 2 Assume C s =M×C fn C s It is the sampling capacitor C s The capacitance value, C fn For the balancing capacitor C fn The capacitance value, M, is a positive coefficient. V can be derived and determined. on =V com -M*(V inp -V inn V op =V com +M*(V inp -V inn Then, we can obtain the amplification factor achieved by the self-balancing differential signal integrating amplifier circuit when it reaches a steady state. Therefore, by adjusting the sampling capacitor C s and balancing capacitor C fn The ratio can be used to precisely adjust the magnification K.

[0050] The above descriptions are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.

Claims

1. A chip state monitoring circuit based on a self-balancing differential signal integrating amplification circuit, characterized in that, The chip state monitoring circuit comprises a state sensing circuit, a self-balancing differential signal integral amplification circuit and an analog-to-digital converter connected in sequence, the analog-to-digital converter is connected to a chip configuration circuit inside the chip, the state sensing circuit is arranged at a detection point inside the chip and senses a differential state signal of the chip; The self-balancing differential signal integral amplification circuit comprises a fully differential operational amplifier, a positive coefficient integral network and a negative coefficient balancing network, both of which are connected between the input and output terminals of the fully differential operational amplifier; the fully differential operational amplifier realizes signal amplification of the state signal under the action of the positive coefficient integral network and reversely adjusts the signal amplification under the action of the negative coefficient balancing network, and the reversely adjusting function realized by the negative coefficient balancing network gradually increases until the self-balancing differential signal integral amplification circuit reaches self-balancing, so that the output signal of the self-balancing differential signal integral amplification circuit is stabilized as the state signal amplified by K times; The state signal amplified by K times is converted by the analog-to-digital converter and then output to the chip configuration circuit; The self-balancing differential signal integral amplification circuit further comprises a sampling network which samples the charge of the state signal; before the self-balancing differential signal integral amplification circuit reaches self-balancing, part of the charge sampled by the sampling network is transferred to the positive coefficient integral network to realize signal amplification, and the other part of the charge sampled by the sampling network is transferred to the negative coefficient balancing network to realize the reversely adjusting function of signal amplification, and the output signal of the self-balancing differential signal integral amplification circuit gradually increases; with the increase of the output signal of the fully differential operational amplifier, the charge transferred by the sampling network to the negative coefficient balancing network gradually increases, so that the reversely adjusting function realized by the negative coefficient balancing network gradually increases; after the self-balancing differential signal integral amplification circuit reaches self-balancing, all the charge sampled by the sampling network is transferred to the negative coefficient balancing network, and the output signal of the self-balancing differential signal integral amplification circuit is stabilized as the state signal amplified by K times; In each sampling period, the self-balancing differential signal integral amplification circuit sequentially passes through a sampling stage, an integral stage and a holding stage; in each sampling period before the self-balancing differential signal integral amplification circuit reaches self-balancing: in the sampling stage, the sampling network samples the charge of the state signal; In the integral stage, the charge sampled by the sampling network is transferred to the positive coefficient integral network and the negative coefficient balancing network, so that the output signal of the self-balancing differential signal integral amplification circuit increases; in the holding stage, the output signal of the fully differential operational amplifier remains unchanged; in each sampling period after the self-balancing differential signal integral amplification circuit reaches self-balancing after a plurality of sampling periods: in the sampling stage, the sampling network samples the charge of the state signal; In the integration stage, all the charges sampled by the sampling network are transferred to the negative coefficient balance network, so that the output signal of the self-balanced differential signal integration amplification circuit remains unchanged; In the holding stage, the output signal of the fully differential operational amplifier remains unchanged.

2. The chip status monitoring circuit of claim 1, wherein, The positive coefficient integration network is based on an integration capacitor The negative coefficient balance network is based on a balance capacitor The sampling network is based on a sampling capacitor The self-balanced differential signal integration amplification circuit steady state amplification multiple K realized on the state signal is determined by the capacitance of the sampling capacitor and the balance capacitor .

3. The chip state monitoring circuit of claim 2, wherein, The self-balanced differential signal integral amplification circuit realizes an amplification multiple to the state signal in a stable state wherein, represents a capacitance value of a sampling capacitor , represents a capacitance value of a balancing capacitor .

4. The chip state monitoring circuit according to claim 1, characterized in that, In the integration stage of each sampling period before the self-balanced differential signal integration amplification circuit reaches self-balance, the fully differential operational amplifier starts to work, the charges sampled by the sampling capacitor are transferred to the positive coefficient integration network and to the negative coefficient balance network, and the charges transferred to the negative coefficient balance network increase with the increase of the output signal of the fully differential operational amplifier, so that the reverse regulation function realized by the negative coefficient balance network gradually strengthens.

5. The chip status monitoring circuit of claim 1, wherein, The self-balancing differential signal integral amplification circuit further comprises a common-mode signal generation circuit connected to a common-mode signal end of the fully differential operational amplifier ; The positive input terminal of the fully differential operational amplifier and negative output terminal The first circuit structure is connected between them, and the negative input terminal of the fully differential operational amplifier is... and positive output terminal The first circuit structure is symmetrical to the second circuit structure, which is connected to the second circuit structure. Each circuit structure includes a sampling network, a positive coefficient integration network, and a negative coefficient balancing network. In each sampling period of the self-balanced differential signal integral amplification circuit, in a sampling stage, a sampling network in the first circuit structure is connected to a positive differential input end of the self-balanced differential signal integral amplification circuit sampling is performed, and a sampling network in the second circuit structure is connected to a negative differential input end of the self-balanced differential signal integral amplification circuit sampling is performed; In the integration stage, the sampling network in the first circuit structure is connected to the negative differential input of the self-balanced differential signal integration amplification circuit , and the sampling network in the second circuit structure is connected to the positive differential input of the self-balanced differential signal integration amplification circuit . The voltage difference varied on the sampling capacitors in the two sampling networks transfers the sampled charges to the integration capacitors in the positive coefficient integration network and the balancing capacitors in the negative coefficient balancing network in the circuit structure where the sampling capacitors are located . ​ 6. The chip status monitoring circuit of claim 5, wherein, The first circuit structure comprises: Sampling capacitors in the sampling network The upper electrode plate is controlled by a switch Connect the positive differential input terminal of the self-balancing differential signal integrating amplifier circuit. Sampling capacitor The upper electrode plate is also controlled by a switch. Connect the negative differential input terminal of the self-balancing differential signal integrating amplifier circuit. Sampling capacitor The lower electrode is connected to the balancing capacitor in the negative coefficient balancing network. The lower electrode plate, balancing capacitor The upper electrode plate is controlled by a switch Connect to the negative output terminal of the fully differential operational amplifier Balance capacitor The upper electrode plate is also controlled by a switch. Connect the common-mode signal terminal of the fully differential operational amplifier Sampling capacitor The lower electrode plate is also controlled by a switch. Integrating capacitors connected in a positive coefficient integral network The lower electrode plate, the integrating capacitor The upper electrode plate is controlled by a switch Connect to the negative output terminal of the fully differential operational amplifier Integrating capacitor The lower plate is also connected to the positive input terminal of the fully differential operational amplifier. The positive input terminal of the fully differential operational amplifier and negative output terminal They are also connected by a switch bridging; wherein the switch is controlled by the control signal , the switch is controlled by the control signal , the switch is controlled by the control signal , the switch is controlled by the control signal , the switch is controlled by the control signal , and the switch is controlled by the control signal 7. The chip state monitoring circuit of claim 6, wherein, The working process of the first circuit structure in each sampling period is as follows: During the sampling phase, the control signal Control switch ,switch and switch Close, control signal Control switch Close, control signal Control switch Disconnect, control signal Control switch and switch Disconnect; sampling capacitor in the first circuit structure The upper electrode is connected to the positive differential input terminal. The positive input terminal of the fully differential operational amplifier and negative output terminal Shorting the circuit, the value after shorting is connected to the sampling capacitor. The lower electrode and the balancing capacitor The lower electrode plate, balancing capacitor The upper electrode plate is connected to the output terminal of the common-mode signal generation circuit; Integral capacitor The charge in the integral capacitor remains unchanged; During the integration phase, the control signal Control switch ,switch and switch Disconnect, control signal Control switch Close, control signal Control switch Close, control signal Control switch and switch When closed, the fully differential operational amplifier begins to operate, and the sampling capacitor in the first circuit structure... Switch the upper electrode to connect to the negative differential input terminal. Sampling capacitor The lower electrode plate and the balancing capacitor The lower plate and integrating capacitor The lower plate is connected to and connected to the positive input terminal of the fully differential operational amplifier. Balance capacitor upper plate and integrating capacitor The upper plate is connected to and connected to the negative output terminal of the fully differential operational amplifier. Sampling capacitor The changing voltage difference transfers the sampled charge to the balancing capacitor. and integrating capacitor superior; In the hold phase, the control signal controls the switch , the switch and the switch are open, the control signal controls the switch , the control signal controls the switch , the control signal controls the switch and the switch are closed; the two ends of the integration capacitor are connected to the positive input end and the negative output end of the full differential operational amplifier respectively, the full differential operational amplifier keeps the output signal unchanged.

8. The chip state monitoring circuit of claim 7, wherein, The working process of the first circuit structure in each sampling period is as follows: During the sampling phase, the sampling capacitor holds a charge of The charge in the balancing capacitor is The charge in the integrating capacitor remains the amount of charge from the previous sampling cycle. In the integration phase, the sampled capacitor becomes , the charge in the balancing capacitor becomes ; switching from the sampling phase to the integration phase, the sampling capacitor The varying voltage difference causes the sampling capacitor The charge transferred to the two networks is ; During the hold phase, the charge of the integration capacitor remains constant until the next sampling period; wherein, in each sampling period before the self-balancing differential signal integration amplification circuit reaches self-balancing, the charge of the sampling capacitor transferred to the balancing capacitor of the negative coefficient balancing network is , and the charge of the integration capacitor transferred to the positive coefficient integration network is As the sampling period changes, the output signal of the fully differential operational amplifier and increases, so that the sampling capacitance transferred to the balancing capacitance charge increases, and the reverse regulation function realized by the negative coefficient balancing network gradually strengthens; After several sampling periods, when and are equal, the self-balancing differential signal integration amplification circuit reaches self-balance, and thereafter in each sampling period after the self-balancing differential signal integration amplification circuit reaches self-balance, after switching to the integration stage, the sampling capacitor transfers the charge to the two networks all to the balancing capacitor and no longer to the integration capacitor , and the output signal of the self-balancing differential signal integration amplification circuit is stabilized as the state signal after amplification K times. wherein, is a capacitance value of the sampling capacitor , is a capacitance value of the balancing capacitor , is a voltage value of a common-mode signal outputted by the common-mode signal generating circuit to the common-mode signal terminal of the fully differential operational amplifier , is a voltage value of the positive differential input terminal , is a voltage value of the negative differential input terminal , is a voltage value of the positive input terminal of the fully differential operational amplifier , is a voltage value of the negative output terminal of the fully differential operational amplifier .

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