Semiconductor structure and manufacturing method thereof

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a bit line located on the substrate, the bit line material comprising a metal-semiconductor compound; a semiconductor channel comprising a first doped region, a channel region, and a second doped region arranged in sequence, the first doped region being in contact with the bit line; a first dielectric layer covering the sidewall surfaces of the first doped region, with a first spacer between first dielectric layers located on adjacent first doped region sidewalls on the same bit line; an insulating layer covering the sidewall surfaces of the channel region; a word line covering the sidewall surfaces of the insulating layer away from the channel region, with a second spacer between adjacent word lines; a second dielectric layer covering the sidewall surfaces of the second doped region, with a third spacer between second dielectric layers located on adjacent second doped region sidewalls; and a third dielectric layer located between the first spacer, the second spacer, and the third spacer. The embodiments of the present invention are advantageous for reducing the resistance of the bit line, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of dynamic memory develops towards a higher direction, while studying the arrangement of transistors in the dynamic memory array structure and how to reduce the size of a single functional device in the dynamic memory array structure, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When a vertical gate-all-around (GAA) transistor structure is used as a dynamic memory select transistor (access transistor), the area occupied by it can reach 4F. 2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved, but at some sizes, the bit line buried at the bottom of the transistor has a higher resistance because it is mainly composed of silicon. Summary of the Invention

[0004] The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are beneficial to reducing the resistance of the bit line and improving the electrical performance of the semiconductor structure.

[0005] To address the above-mentioned problem, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a bit line located on the substrate, wherein the material of the bit line includes a metal-semiconductor compound; a semiconductor channel located on a surface of the bit line, wherein in a direction along the substrate toward the bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence, wherein the first doped region contacts the bit line; a first dielectric layer covering sidewall surfaces of the first doped region, wherein a first spacer is provided between adjacent first dielectric layers on the sidewalls of the first doped region on the same bit line; an insulating layer covering sidewall surfaces of the channel region; a word line covering sidewall surfaces of the insulating layer away from the channel region, wherein a second spacer is provided between adjacent word lines; a second dielectric layer covering sidewall surfaces of the second doped region, wherein a third spacer is provided between adjacent second dielectric layers on the sidewalls of the second doped region; and a third dielectric layer located between the first spacer, the second spacer, and the third spacer.

[0006] Accordingly, an embodiment of the present invention further provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an initial bit line on the substrate, and forming a semiconductor channel on a surface of the initial bit line away from the substrate, wherein the semiconductor channel comprises a first doped region, a channel region, and a second doped region arranged in sequence along the substrate toward the initial bit line; forming a first dielectric layer covering sidewall surfaces of the first doped region, with a first spacer between adjacent sidewalls of the first doped region on the same initial bit line; forming an insulating layer covering sidewall surfaces of the channel region; forming a word line covering sidewall surfaces of the insulating layer away from the channel region, with a second spacer between adjacent word lines; forming a second dielectric layer covering sidewall surfaces of the second doped region, with a third spacer between adjacent sidewalls of the second dielectric layer, the first spacer, the second spacer, and the third spacer being connected and exposing a portion of the initial bit line; and performing a metallization process on the exposed initial bit line to form a bit line, wherein the material of the bit line comprises a metal-semiconductor compound.

[0007] Compared with related technologies, the technical solution provided by the embodiment of the present invention has the following advantages:

[0008] In the above technical solution, a vertical GAA transistor is formed on a substrate, and a bit line is located between the substrate and the GAA transistor, thereby forming a 3D stacked semiconductor structure, which is beneficial for improving the integration density of the semiconductor structure. In addition, because the bit line material includes a metal-semiconductor compound, it is beneficial to reduce the resistance of the bit line, thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] One or more embodiments are exemplarily described by the figures in the corresponding drawings. Unless otherwise stated, the figures in the drawings are not limited to scale.

[0010] Figures 1 to 35 This is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] As can be seen from the background art, currently, there is a need to improve the electrical performance of small-sized functional devices in semiconductor structures while increasing the integration density of semiconductor structures.

[0012] To address the aforementioned issues, the present invention provides a semiconductor structure and a method for fabricating the same. In the semiconductor structure, a vertical GAA transistor is formed on a substrate, with a bit line positioned between the substrate and the GAA transistor. This structure forms a 3D stacked semiconductor structure, facilitating improved integration density. Furthermore, because the bit line material comprises a metal-semiconductor compound, the resistance of the bit line is reduced, thereby improving the electrical performance of the semiconductor structure.

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0014] An embodiment of the present invention provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figures 1 to 5 This is a schematic diagram of the structure of the semiconductor structure provided by one embodiment of the present invention. Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention is shown. Figure 2 for Figure 1 A schematic cross-sectional view of the structure shown along the first cross-sectional direction AA1, Figure 3 for Figure 1 Another cross-sectional schematic diagram of the structure shown along the first cross-sectional direction AA1, Figure 4 for Figure 1 The structure shown is a cross-sectional schematic diagram along the second cross-sectional direction BB1, Figure 5 A schematic diagram of another structure of a semiconductor structure provided by an embodiment of the present invention.

[0015] Combined with reference Figures 1 to 5The semiconductor structure includes: a substrate 11; a bit line 104 located on the substrate 11, and the material of the bit line 104 includes a metal-semiconductor compound; a semiconductor channel 105 located on the surface of the bit line 104. In a direction Z from the substrate 11 to the bit line 104, the semiconductor channel 105 includes a first doped region I, a channel region II, and a second doped region III arranged in sequence, with the first doped region I in contact with the bit line 104; a first dielectric layer 113 covering the sidewall surface of the first doped region I, with a first gap between adjacent first dielectric layers 113 on the sidewalls of the first doped region I on the same bit line 104; an insulating layer 106 covering the sidewall surface of the channel region II; a word line 107 covering the sidewall surface of the insulating layer 106 away from the channel region II, with a second gap between adjacent word lines 107; a second dielectric layer 123 covering the sidewall surface of the second doped region II, with a third gap between the second dielectric layers 123 located on the sidewalls of adjacent second doped regions II; and a third dielectric layer 133 located between the first gap, the second gap, and the third gap.

[0016] Since the semiconductor structure includes vertical GAA transistors and the bit line 104 is located between the substrate 11 and the GAA transistors, a 3D stacked memory device can be formed, which is beneficial for improving the integration density of the semiconductor structure.

[0017] The following will be combined Figures 1 to 5 The semiconductor structure is described in more detail.

[0018] In this embodiment, the material type of substrate 11 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium. In addition, substrate 11 is doped with a first type of ions.

[0019] Furthermore, the substrate 11, the bit line 104, and the semiconductor channel 105 have the same semiconductor element, so the semiconductor channel 105 and the bit line 104 can be formed using the same film layer structure. The film layer structure is composed of semiconductor elements, so that the semiconductor channel 105 and the bit line 104 are an integrated structure, thereby improving the interface state defects between the semiconductor channel 105 and the bit line 104 and improving the performance of the semiconductor structure.

[0020] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, both the bit line 104 and the semiconductor channel 105 include silicon. In other examples, both the bit line and the semiconductor channel may include germanium, or both the bit line and the semiconductor channel may include silicon and germanium, or both the bit line and the semiconductor channel may include silicon and carbon, or both the bit line and the semiconductor channel may include arsenic and gallium, or both the bit line and the semiconductor channel may include gallium and indium.

[0021] Specifically, the material of bit line 104 includes a metal-semiconductor compound 114. Compared to unmetallized semiconductor materials, metal-semiconductor compound 114 has a relatively low resistivity. Therefore, compared to semiconductor channel 105, bit line 104 has a lower resistivity, thereby reducing the resistance of bit line 104 and the contact resistance between bit line 104 and first doped region I, further improving the electrical performance of the semiconductor structure. Furthermore, the resistivity of bit line 104 is also lower than that of substrate 11.

[0022] In some examples, the material of the region of the bit line 104 located directly below the first doped region I is a semiconductor material, and the material of the portion of the bit line 104 not covered by the first doped region I is a metal-semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, the material of the portion of the bit line 104 located directly below the first doped region I is a semiconductor material, and the material of the remaining region of the bit line 104 located directly below the first doped region I may also be a metal-semiconductor compound, with the "remaining region" herein being located outside the "partial region."

[0023] Specifically, in one example, referring to Figure 2 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced apart from each other; in another example, referring to Figure 3 , the multiple metal semiconductor compounds 114 in the same bit line 104 are interconnected. It should be noted that, Figure 3 The example only illustrates the case where the edges of adjacent metal semiconductor compounds 114 are just in contact with each other to be connected. In actual situations, the area in contact between adjacent metal semiconductor compounds 114 can be larger. This embodiment does not limit the size of the area in contact between adjacent metal semiconductor compounds 114.

[0024] In other examples, the material of the entire bit line may be a metal-semiconductor compound.

[0025] Taking silicon as the semiconductor element as an example, the metal semiconductor compound 114 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.

[0026] In this embodiment, a plurality of spaced-apart bit lines 104 may be formed on the substrate 11, and each bit line 104 may be in contact with at least one first doping region I. Figures 1 to 4 In the figure, four mutually spaced bit lines 104 and each bit line 104 in contact with four first doping regions I are taken as an example. The number of bit lines 104 and the number of first doping regions I in contact with each bit line 104 can be reasonably set according to actual electrical requirements.

[0027] The bit line 104 is doped with the second type of ions, while the substrate 11 is doped with the first type of ions. The second type of ions is different from the first type of ions, and both the first type of ions and the second type of ions are either N-type or P-type ions. Thus, the bit line 104 and the substrate 11 form a PN junction, which helps prevent leakage in the bit line 104 and further improves the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the substrate 11 may not be doped with the first type of ions.

[0028] Specifically, the N-type ion is at least one of arsenic ion, phosphorus ion or antimony ion; the P-type ion is at least one of boron ion, indium ion or gallium ion.

[0029] Furthermore, the first doping region I, the channel region II and the second doping region III in the semiconductor channel 105 are doped with the same type of doping ions, namely the second type ions, and the doping concentration of the doping ions in the first doping region I is consistent with the doping concentration in the channel region II and the second doping region III.

[0030] Therefore, the device formed by the semiconductor channel 105 is a junctionless transistor, that is, the doping ions in the first doping region I, the channel region II and the second doping region III are of the same type, for example, the doping ions are all N-type ions. Furthermore, the doping ions in the first doping region I, the channel region II and the second doping region III can be the same. The term "junctionless" here refers to a PN junction, i.e., the transistor formed by the semiconductor channel 105 has no PN junction, i.e., the doping concentration of the doping ions in the first doping region I, the channel region II, and the second doping region III are the same. This has the following advantages: on the one hand, no additional doping is required for the first doping region I and the second doping region III, thereby avoiding the problem of difficulty in controlling the doping process of the first doping region I and the second doping region III. In particular, as transistor dimensions continue to shrink, if additional doping is performed on the first doping region I and the second doping region III, the doping concentration becomes even more difficult to control. On the other hand, since the device is a junctionless transistor, it is advantageous to avoid the use of ultra-steep source-drain concentration gradient doping processes to form ultra-steep PN junctions in the nanometer range, thereby avoiding problems such as threshold voltage drift and increased leakage current caused by doping mutations. It is also advantageous to suppress the short channel effect, and it can still operate within the scale range of a few nanometers, thereby helping to further improve the integration density and electrical performance of the semiconductor structure. It is understood that the additional doping here refers to the doping performed to make the doping ion type of the first doping region I and the second doping region III different from the doping ion type of the channel region II.

[0031] In some examples, the doping concentration of the second type ions in the semiconductor channel 105 is 1×10 19 atom / cm 3 ~1×10 20 atom / cm 3 , and in the direction Z along the substrate 11 pointing to the bit line 104, the height of the semiconductor channel 105 is 100nm~150nm, and the heights of the first doping region I, the channel region II and the second doping region III are all 30nm~50nm.

[0032] In this embodiment, the orthographic projection of the channel region II on the substrate 11 is smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11. In a cross section perpendicular to the direction Z pointing from the bit line 104 to the semiconductor channel 105, this facilitates the formation of a channel region II with a smaller cross-sectional area, thereby improving the control capability of the subsequently formed word line over the channel region II, thereby making it easier to control the conduction or shutdown of the GAA transistor. In other embodiments, the orthographic projections of the first doped region, the channel region, and the second doped region on the substrate can be equal; alternatively, the orthographic projections of the channel region and the second doped region on the substrate can both be smaller than the orthographic projection of the first doped region on the substrate.

[0033] In some examples, in a cross section perpendicular to the direction Z, the width W of the channel region II and the length L of the channel region II are both no greater than 10 nm, which helps ensure that subsequently formed word lines have good control over the channel region II.

[0034] Specifically, the first dielectric layer 113 may include a fourth dielectric layer 143 and a fifth dielectric layer 153. The fourth dielectric layer 143 is located between adjacent bit lines 104 and between adjacent first doped regions I on adjacent bit lines 104. The fifth dielectric layer 153 is located on the sidewalls of the adjacent first doped regions I on the same bit line 104 and on the sidewalls of the fourth dielectric layer 143. The first dielectric layer 113 is used to achieve electrical insulation between adjacent semiconductor channels 105 and adjacent bit lines 104.

[0035] In some examples, the material of the fourth dielectric layer 143 is the same as the material of the fifth dielectric layer 153. Furthermore, the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 can both be silicon oxide. In other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer can also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation performance.

[0036] In this embodiment, the orthographic projection of the outer periphery of the insulating layer 106 on the substrate 11 is smaller than the orthographic projection of the outer periphery of the second dielectric layer 123 on the substrate 11, that is, Figure 2 and Figure 4The insulating layer 106 is further away from the outer wall of the semiconductor channel 105 than the second dielectric layer 123 is, and is closer to the semiconductor channel 105. Furthermore, the insulating layer 106 is further away from the outer wall of the semiconductor channel 105 than the first dielectric layer 113 is, and is also closer to the semiconductor channel 105. The insulating layer 106 is made of silicon oxide.

[0037] In other embodiments, the insulating layer and the second dielectric layer may be of the same film structure, that is, the insulating layer and the second dielectric layer may be formed by the same process step, wherein the material of the insulating layer and the material of the second dielectric layer include at least one of silicon oxide or silicon nitride.

[0038] Specifically, the first interval, the second interval and the third interval are connected.

[0039] In some examples, reference Figures 2 to 4 The orthographic projections of the first spacer and the second spacer on the substrate 11 coincide with each other, the third dielectric layer 133 fills the first spacer, the second spacer, and the third spacer, and the top surface of the third dielectric layer 133 away from the substrate 11 is higher than the top surface of the second doped region III away from the substrate 11.

[0040] In some other examples, reference Figure 5 The third dielectric layer 133 located in the second spacer has a gap 109. That is, in addition to the third dielectric layer 133, gaps 109 are also present between adjacent word lines 107. This helps reduce the capacitance generated between adjacent word lines 107, thereby improving the electrical characteristics of the semiconductor structure. In other examples, the gap may exist not only in the third dielectric layer located in the second spacer, but also in the third dielectric layer located in the first spacer, or in the third dielectric layer located in the third spacer.

[0041] The semiconductor structure may further include a metal contact layer 108 located on a top surface of the second doped region III away from the substrate 11, wherein the metal semiconductor compound 114 and the metal contact layer 108 contain the same metal element. The metal element includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0042] Because the metal contact layer 108 contains metal elements, when the lower electrode of the capacitor structure is subsequently formed on the metal contact layer 108, the metal contact layer 108 forms an ohmic contact with the lower electrode, preventing the lower electrode from directly contacting the semiconductor material and forming a Schottky barrier contact. The ohmic contact helps reduce the contact resistance between the second doped region III and the lower electrode, thereby reducing the energy consumption of the semiconductor structure during operation and improving the RC delay effect, thereby improving the electrical performance of the semiconductor structure. In addition, from a manufacturing process perspective, the metal contact layer 108 and the metal-semiconductor compound 114 contain the same metal elements, which facilitates the formation of the metal contact layer 108 and the metal-semiconductor compound 114 in the bit line 104 in a single process step.

[0043] Furthermore, the orthographic projection of the metal contact layer 108 on the substrate 11 covers the orthographic projection of the second doping region III on the substrate 11, which is beneficial to increasing the contact area between the metal contact layer 108 and the lower electrode, thereby reducing the contact resistance between the metal contact layer 108 and the lower electrode, thereby improving the electrical performance of the semiconductor structure.

[0044] The semiconductor structure may further include: a transition layer 118, located between the second doping region III and the metal contact layer 108, and the transition layer 118 is located on a portion of the top surface of the second doping region III, and the metal contact layer 108 wraps the remaining surface of the transition layer 118, the transition layer 118 and the second doping region III are doped with the same type of doping ions, and the doping concentration of the doping ions in the transition layer 118 is greater than the doping concentration in the second doping region III, then the resistance of the transition layer 118 is less than the resistance of the second doping region III, which is beneficial to further reduce the transmission resistance between the second doping region III and the lower electrode.

[0045] In other embodiments, the semiconductor structure may not include a transition layer, and the top surface of the second doped region only has a metal contact layer.

[0046] The semiconductor structure may further include: a capacitor structure (not shown in the figure), which is located on the surface formed by the metal contact layer 108 and the third dielectric layer 133 .

[0047] In summary, the substrate 11 has a vertical GAA transistor, and the bit line 104 is located between the substrate 11 and the GAA transistor, thereby forming a 3D stacked semiconductor structure, which is beneficial to improving the integration density of the semiconductor structure. At the same time, the material of the bit line 104 includes a metal semiconductor compound 114, which is beneficial to reducing the resistance of the bit line 104, thereby reducing the contact resistance between the bit line 104 and the first doped region I, and further improving the electrical performance of the semiconductor structure. In addition, the device formed by the semiconductor channel 105 is a junctionless transistor, which is beneficial to avoid the use of an ultra-steep source-drain concentration gradient doping process, thereby avoiding problems such as threshold voltage drift and increased leakage current caused by doping mutations, and is also beneficial to suppressing the short channel effect, thereby further improving the integration density and electrical performance of the semiconductor structure.

[0048] Correspondingly, another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0049] Figures 1 to 35 A schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in another embodiment of the present invention is provided. The method for manufacturing the semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiments will not be described in detail below.

[0050] refer to Figures 6 to 9 , providing a substrate 11; forming an initial bit line 124 on the substrate 11, and forming a semiconductor channel 105 on a surface of the initial bit line 124 away from the substrate 11, in a direction along the substrate 11 pointing to the initial bit line 124, the semiconductor channel 105 includes a first doped region I, a channel region II and a second doped region III arranged in sequence.

[0051] Specifically, providing a substrate 11 and forming an initial bit line 124 on the substrate 11 to surround the semiconductor channel 105 includes the following steps:

[0052] refer to Figure 6 A substrate 110 is provided. Specifically, the material type of the substrate 110 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0053] The substrate 110 includes: a base 11 doped with first type ions; and an initial semiconductor layer 10 disposed on the base 11 .

[0054] The initial semiconductor layer 10 is doped and annealed so that the initial semiconductor layer 10 is doped with second-type ions for subsequent etching of the initial semiconductor layer 10 to form an initial bit line 124 and a semiconductor channel 105. The second-type ions are different from the first-type ions. Both the first-type ions and the second-type ions are either N-type ions or P-type ions.

[0055] The doping treatment may be performed by high-temperature diffusion or ion implantation. After the initial semiconductor layer 10 is doped by ion implantation, the annealing temperature is 800° C. to 1000° C.

[0056] In this embodiment, the doping concentration of the second type ions in the initial semiconductor layer 10 is 1×10 19 atom / cm 3 ~1×10 20 atom / cm 3 , and in the direction from the initial semiconductor layer 10 to the substrate 11, the doping depth of the second type ions in the initial semiconductor layer 10 is 150 nm to 250 nm. Furthermore, the first type ions are P-type ions, and the second type ions are N-type ions. In other embodiments, the first type ions may be N-type ions, and the second type ions may be P-type ions.

[0057] A buffer layer 120 and a barrier layer 130 are sequentially stacked on the side of the initial semiconductor layer 10 away from the substrate 11. In some examples, the buffer layer 120 and the barrier layer 130 can be formed by a deposition process. The buffer layer 120 is made of silicon oxide, and the barrier layer 130 is made of silicon nitride.

[0058] Furthermore, a chemical vapor deposition process may be used to deposit silicon nitride to form the barrier layer 130 . The oxidation rate of the silicon nitride film layer is very slow, which is beneficial for protecting the substrate 100 located below the silicon nitride film layer and preventing the substrate 100 from being oxidized.

[0059] In some examples, substrate 110 is a silicon substrate. Because the lattice constant and thermal expansion coefficient of silicon nitride significantly mismatch those of the silicon substrate, if silicon nitride is directly formed on the silicon substrate, the defect density at the interface between the silicon nitride and silicon is high, easily becoming carrier traps and recombination centers, affecting the carrier mobility of silicon and, consequently, the performance and operating life of the semiconductor structure. Furthermore, silicon nitride films exhibit high stress and are prone to cracking when deposited directly on a silicon substrate. Therefore, forming silicon oxide as a buffer layer 120 before depositing silicon nitride on the silicon substrate can help improve the performance and operating life of the conductor structure.

[0060] Continue to refer Figure 6A first mask layer 102 is formed on the barrier layer 130 . The first mask layer 102 has a plurality of mutually separated first openings b. In the extension direction X of the first openings b, the length of the first openings b is consistent with the length of the subsequently formed bit lines.

[0061] refer to Figure 7 The barrier layer 130 , the buffer layer 120 and the initial semiconductor layer 10 are etched using the first mask layer 102 as a mask to form a plurality of first trenches a, and the first mask layer 102 is removed.

[0062] In this embodiment, the depth of the first trench a is 250 to 300 nm along a direction Z perpendicular to the surface of the substrate 11. Because the depth of the first trench a is greater than the doping depth of the second type ions in the initial semiconductor layer 10, it is beneficial to ensure that the initial semiconductor layer 10 doped with the second type ions is completely etched, facilitating the subsequent formation of semiconductor channels and bit lines with a high doping concentration of the second type ions.

[0063] refer to Figure 8 , a fourth dielectric layer 143 is formed in the first trench a.

[0064] In this embodiment, the fourth dielectric layer 143 can be formed using the following process steps: performing a deposition process to form a fourth dielectric film that covers the top surface of the barrier layer 130 and completely fills the first trench a; performing a chemical mechanical planarization process on the fourth dielectric film until the top surface of the barrier layer 130 is exposed, with the remaining fourth dielectric film serving as the fourth dielectric layer 143. The fourth dielectric film is made of silicon oxide.

[0065] Furthermore, a second mask layer 112 is formed on the top surface formed by the fourth dielectric layer 143 and the remaining substrate 110. The second mask layer 112 has a plurality of mutually discrete second openings c. In the extension direction Y along the second openings c, the length of the second openings c is consistent with the length of the subsequently formed word line.

[0066] In this embodiment, combined with reference Figure 6 and Figure 8 The extension direction X of the first opening b is perpendicular to the extension direction Y of the second opening c, so that the semiconductor channel 105 formed finally presents a 4F 2 The arrangement is conducive to further improving the integration density of the semiconductor structure. In other embodiments, the extension direction of the first opening intersects with the extension direction of the second opening, and the angle between the two may not be 90°.

[0067] Furthermore, the ratio of the opening width of the first opening b along direction Y to the opening width of the second opening c along direction X is 2 to 1, ensuring that a through hole can be subsequently formed that exposes the first dielectric layer surrounding the sidewalls of the channel region II, thereby facilitating the subsequent formation of a first gap for wordline fabrication. In some examples, the opening width of the first opening b along direction Y is equal to the opening width of the second opening c along direction X, and the spacing between adjacent first openings b is equal to the spacing between adjacent second openings c. This, on the one hand, ensures that the multiple semiconductor channels formed subsequently are arranged in a regular pattern, further improving the integration density of the semiconductor structure; on the other hand, the same mask can be used to form the first mask layer 102 and the second mask layer 112, thereby reducing the manufacturing cost of the semiconductor structure.

[0068] In this embodiment, the methods of forming the first mask layer 102 and the second mask layer 112 both include self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0069] refer to Figure 9 , the initial semiconductor layer 10 is etched using the second mask layer 112 as a mask (refer to Figure 6 ) and the fourth dielectric layer 143, forming a plurality of second trenches d, initial bit lines 124, and semiconductor channels 105. In the direction Z perpendicular to the surface of the substrate 11, the depth of the second trenches d is less than the depth of the first trenches a. This facilitates the formation of the initial bit lines 124 while simultaneously forming a plurality of mutually separated semiconductor channels 105 on a side of the initial bit lines 124 away from the substrate 11, and the initial bit lines 124 are in contact with the first doped regions I of the semiconductor channels 105. The second mask layer 112 is removed.

[0070] In some examples, the depth of the second trench d is 100 nm to 150 nm. Since the doping depth of the second type ions in the initial semiconductor layer 10 is 150 nm to 250 nm, it is beneficial for the initial semiconductor layer 10 that is mostly or completely doped with the second type ions to be transformed into the semiconductor channel 105 after two etchings.

[0071] In addition, the material of the substrate 110 is silicon, and the material of the fourth dielectric layer 143 is silicon oxide. In the step of etching the initial semiconductor layer 10 and the fourth dielectric layer 143 using the second mask layer 112 as a mask, the etching rate of the silicon oxide is greater than the etching rate of the silicon, so that part of the sidewall of the initial bit line 124 will be exposed.

[0072] In order to achieve electrical insulation between adjacent initial bit lines 124 and adjacent semiconductor channels 105, after the initial semiconductor layer 10 and the fourth dielectric layer 143 are etched using the second mask layer 112 as a mask, the remaining fourth dielectric layer 143 is still located in the gaps between adjacent initial bit lines 124 and in the gaps between adjacent semiconductor channels 105.

[0073] The doping ions in the first doping region I, the channel region II, and the second doping region III are of the same type, for example, all N-type ions, and the doping concentrations of the doping ions in the first doping region I, the channel region II, and the second doping region III are the same, meaning that the device formed by the semiconductor channel 105 is a junctionless transistor. Furthermore, the doping ions in the first doping region I, the channel region II, and the second doping region III can be the same. This, on the one hand, eliminates the need for additional doping of the first doping region I and the second doping region III, thereby avoiding the difficulty in controlling the doping process for the first doping region I and the second doping region III. In particular, as transistor dimensions continue to shrink, additional doping of the first doping region I and the second doping region III makes it even more difficult to control the doping concentration. On the other hand, since the device is a junctionless transistor, it avoids the use of an ultra-steep source-drain concentration gradient doping process, which would create an ultra-steep PN junction at the nanometer scale. This avoids problems such as threshold voltage drift and increased leakage current caused by doping mutations, and helps suppress short channel effects, allowing operation within a few nanometers. This helps further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to doping performed to make the doping ion type of the first doping region I and the second doping region III different from the doping ion type of the channel region II.

[0074] Furthermore, forming a GAA transistor with a semiconductor channel 105 perpendicular to the initial bit line 124 and away from the top surface of the substrate 11 can constitute a 3D stacked semiconductor structure, which is conducive to designing GAA transistors with smaller size features without adversely affecting the electrical performance of the GAA transistor, thereby improving the integration density of the semiconductor structure.

[0075] In this embodiment, the initial bit line 124 and the semiconductor channel 105 are simultaneously formed through two etching processes using the first mask layer 102 and the second mask layer 112. This facilitates controlling the size of the semiconductor channel 105 by adjusting the sizes of the first opening b and the second opening c, and forms a semiconductor channel 105 with high dimensional accuracy. Furthermore, both the initial bit line 124 and the semiconductor channel 105 are formed by etching the initial semiconductor layer 10. That is, the initial bit line 124 and the semiconductor channel 105 are formed using the same film structure, making the initial bit line 124 and the semiconductor channel 105 an integrated structure. This reduces interface state defects between the initial bit line 124 and the semiconductor channel 105, thereby improving the performance of the semiconductor structure. Furthermore, after etching the initial semiconductor layer 10 using the first mask layer 102 as a mask, a fourth dielectric layer 143 is formed in the first trench a, preparing for the subsequent formation of a gap between the sidewalls of the channel region II and the first isolation layer, thereby facilitating the subsequent formation of the first gap for forming the word line.

[0076] refer to Figures 10 to 35 A first dielectric layer 113 is formed covering the sidewall surface of the first doped region I, with a first gap between adjacent first dielectric layers 113 on the sidewalls of the first doped region I on the same initial bit line 124; an insulating layer 106 is formed covering the sidewall surface of the channel region II; a word line 107 is formed covering the insulating layer 106 away from the sidewall surface of the channel region II, with a second gap between adjacent word lines 107; a second dielectric layer 123 is formed covering the sidewall surface of the second doped region III, with a third gap between the second dielectric layers 123 located on the sidewalls of adjacent second doped regions III, the first gap, the second gap, and the third gap being connected and exposing a portion of the initial bit line 124; and the exposed initial bit line 124 is metallized to form a bit line 104, wherein the material of the bit line 104 includes a metal semiconductor compound 114.

[0077] in, Figure 12 for Figure 11 The structure shown is a cross-sectional schematic diagram along the first cross-sectional direction AA1, Figure 13 for Figure 11 The structure shown is a schematic cross-sectional view along the second cross-sectional direction BB1. It should be noted that, in the following, one or both of the schematic cross-sectional views along the first cross-sectional direction AA1 and the second cross-sectional direction BB1 will be provided as needed for description. When only one figure is referenced, the figure is the schematic cross-sectional view along the first cross-sectional direction AA1; when both figures are referenced, the figure first shows the schematic cross-sectional view along the first cross-sectional direction AA1, followed by the schematic cross-sectional view along the second cross-sectional direction BB1.

[0078] In some examples, reference Figures 10 to 27The steps of forming the first dielectric layer 113, the insulating layer 106, the word line 107 and the second dielectric layer 123 include the following:

[0079] refer to Figures 10 and 11 , forming an initial first dielectric layer 113 a , the initial first dielectric layer 113 a surrounds the sidewalls of the semiconductor channel 105 , and a fourth gap e is formed between the initial first dielectric layers 113 a on the sidewalls of adjacent semiconductor channels 105 on the same initial bit line 124 .

[0080] Specifically, refer to Figure 10 , forming a fifth dielectric film 103, the fifth dielectric film 103 conformally covers the second trench d (reference Figure 9 ) and is also located on the sidewall and bottom of the barrier layer 130 and the top surface of the fourth dielectric layer 143.

[0081] Combined with reference Figure 10 and Figure 11 The fifth dielectric film 103 is subjected to a maskless dry etching process until the barrier layer 130 is exposed. Within the same etching time, the fifth dielectric film 103 is etched to the same thickness in different regions to form a fifth dielectric layer 153 .

[0082] Combined with reference Figures 11 to 13 The fourth dielectric layer 143 is located in the second trench d (reference Figure 9 ), the fourth dielectric layer 143 is located in the gap between adjacent semiconductor channels 105, the fourth dielectric layer 143 and the fifth dielectric layer 153 together constitute the initial first dielectric layer 113a, and there is a fourth gap e between the fifth dielectric layer 153 located on the sidewall of the second trench d.

[0083] The material of the fourth dielectric layer 143 is the same as that of the fifth dielectric layer 153. This facilitates the subsequent removal of the fourth and fifth dielectric layers 143 and 153 corresponding to the sidewalls of the channel region II through an etching process. This creates a gap between the sidewalls of the channel region II and the subsequently formed first isolation layer, facilitating the subsequent formation of a gap for forming word lines. Furthermore, the material of the fourth dielectric layer 143 and the fifth dielectric layer 153 are both silicon oxide.

[0084] In other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer may also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation effect. Then, the fourth dielectric layer and the fifth dielectric layer corresponding to the sidewalls of the channel region can be removed step by step.

[0085] refer to Figure 14 , forming a first isolation layer 163 , the first isolation layer 163 fills the fourth gap e, and the material of the first isolation layer 163 is different from the material of the initial first dielectric layer 113 a.

[0086] Specifically, the first isolation layer 163 can be formed using the following process steps: performing a deposition process to form a first isolation film that covers the top surface of the barrier layer 130 and fills the fourth spacer e; performing a chemical mechanical planarization process on the first isolation film, the barrier layer 130, the buffer layer 120, and the initial first dielectric layer 113a until the top surface of the second doped region III is exposed, and the remaining first isolation film serves as the first isolation layer 163. The material of the first isolation film includes silicon nitride.

[0087] refer to Figure 15 , partially etching the initial first dielectric layer 113a until the sidewall of the second doped region III is exposed.

[0088] refer to Figures 16 to 19 ,in, Figure 17 for Figure 16 A top view of Figure 18 is a cross-sectional schematic diagram along the third cross-sectional direction CC1, Figure 19 It is a cross-sectional schematic diagram along the second cross-sectional direction BB1.

[0089] A second isolation layer 173 is formed. The second isolation layer 173 surrounds the sidewalls of the second doped region III and the sidewalls of the first isolation layer 163. The second isolation layer 173 on the sidewalls of the second doped region III and the second isolation layer 173 on the sidewalls of the first isolation layer 163 together form a through hole f. The initial first dielectric layer 113 a is exposed at the bottom of the through hole f. The material of the second isolation layer 173 is different from that of the initial first dielectric layer 113 a.

[0090] Further, refer to Figure 18 and Figure 19 The second isolation layer 173 surrounds the sidewalls of the second doped region III and covers the top surface of the fifth dielectric layer 153 and a portion of the top surface of the fourth dielectric layer 143 . The through hole f exposes a portion of the top surface of the fourth dielectric layer 143 .

[0091] In this embodiment, the second isolation layer 173 can be formed using the following process steps: a deposition process is performed to form a second isolation film that conformally covers the surface formed by the semiconductor channel 105, the initial first dielectric layer 113a, and the first isolation layer 163; the second isolation film is subjected to a maskless dry etching process until the top surface of the second doped region III is exposed, and the etching process etches the second isolation film to the same thickness in different regions within the same etching time, thereby forming the second isolation layer 173 that exposes the first isolation layer 163. The material of the second isolation layer 173 includes silicon nitride.

[0092] Furthermore, in the aforementioned first mask layer 102 and second mask layer 112, the ratio of the opening width of the first opening b along the direction Y to the opening width of the second opening c along the direction X is 2 to 1. This helps ensure that, when forming the second isolation layer 173, the second isolation layer 173 completely fills the gaps between adjacent semiconductor channels 105 on the same initial bit line 124 while not completely filling the gaps between adjacent semiconductor channels 105 on adjacent initial bit lines 124. This ensures that a through hole f is formed that exposes a portion of the top surface of the fourth dielectric layer 143, facilitating the subsequent removal of a portion of the initial first dielectric layer 113a using the through hole f.

[0093] Combine Figures 20 to 22 , the initial first dielectric layer 113 a exposed on the sidewall of the channel region II by the through hole f is removed, and the remaining initial first dielectric layer 113 a serves as the first dielectric layer 113 .

[0094] Since the through hole f exposes a portion of the top surface of the first dielectric layer 113, and the material of the first dielectric layer 113 is different from the materials of the second dielectric layer 123 and the third dielectric layer 133, an etching solution can be injected into the through hole f to remove the first dielectric layer 113 located on the sidewall of the channel region II through a wet etching process, while retaining the first dielectric layer 113 located on the sidewall of the first doped region I.

[0095] Furthermore, the first isolation layer 163 and the second isolation layer 173 together form a support framework, which is in contact with and connected to the second doped region III, and partially embedded in the first dielectric layer 113. During the wet etching process, the support framework supports and secures the semiconductor channel 105. When the etching solution flows, it exerts a compressive force on the semiconductor channel 105, which helps prevent the semiconductor channel 105 from tilting or deflecting due to the compression, thereby improving the stability of the semiconductor structure. Furthermore, the support framework wraps around the sidewalls of the second doped region III, helping to prevent damage to the second doped region III caused by the etching solution.

[0096] After the initial first dielectric layer 113 a located on the sidewall of the channel region II is removed, a second gap g is formed between the channel region II and the first isolation layer 163 . The through hole f and the second gap g together form a cave structure h.

[0097] refer to Figure 23 and Figure 24 , the exposed sidewalls of the channel region II are thermally oxidized to form an insulating layer 106 , and the insulating layer 106 covers the sidewall surfaces of the remaining channel region II, with a fifth spacer i between the insulating layer 106 and the first isolation layer 163 .

[0098] Further, refer to Figure 24The fifth spacer i is also located between the insulating layer 106 on the sidewalls of the adjacent semiconductor channels 105 of the adjacent initial bit lines 124 .

[0099] During the thermal oxidation process, the top surface of the second doped region III is also exposed, and a portion of the second doped region III near the top surface and a portion of the channel region II are converted into an insulating layer 106, so that the orthographic projection of the channel region II on the substrate 11 is smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11. This is beneficial for forming a channel region II with a smaller cross-sectional area in a cross section perpendicular to the direction Z pointing to the semiconductor channel 105 from the initial bit line 124 without using an etching process. This is beneficial for improving the control ability of the subsequently formed word line over the channel region II, thereby making it easier to control the conduction or shutdown of the GAA transistor. . The material of the insulating layer 106 is silicon oxide. In other embodiments, an insulating layer covering the sidewall surface of the channel region can also be formed by a deposition process.

[0100] In this embodiment, the insulating layer 106 located on the top surface of the remaining second doped region III is removed in a subsequent process step. In other embodiments, the insulating layer located on the top surface of the remaining second doped region III can be removed after the thermal oxidation treatment, leaving only the insulating layer covering the sidewall surface of the remaining channel region.

[0101] Continue to refer Figure 23 and Figure 24 , the orthographic projection of the outer periphery of the insulating layer 106 on the substrate 11 is smaller than the orthographic projection of the outer periphery of the second isolation layer 173 on the substrate 11, that is, the insulating layer 106 is farther away from the outer wall of the semiconductor channel 105 than the second isolation layer 173 is farther away from the outer wall of the semiconductor channel 105, and is closer to the semiconductor channel 105, thereby ensuring that there is a fifth gap i between the insulating layer 106 and the first isolation layer 163, so that the subsequent word line can surround the insulating layer 106 located on the side wall of the channel region II. In addition, the insulating layer 106 is farther away from the outer wall of the semiconductor channel 105 than the first dielectric layer 113 (refer to Figure 20 ) is away from the outer wall of the semiconductor channel 105, or can be closer to the semiconductor channel 105.

[0102] refer to Figures 25 to 27 , forming an initial word line, the initial word line completely filling the fifth spacer i and the through-hole f, and the initial word line also being located between the insulating layer 106 on the sidewall of the channel region II on the adjacent initial bit line 124; removing the initial word line located in the through-hole f, and the remaining initial word line serving as word line 107. The initial word line can be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0103] The initial word line is self-aligned to fill the hole structure h (refer to Figure 20), after removing the initial word line located in the through hole f, it is beneficial to self-align to form a word line 107 with precise size, without having to design the size of the word line 107 through an etching process, which is beneficial to simplify the steps of forming the word line 107, and by adjusting the size of the fifth spacer i, a small-sized word line 107 can be obtained.

[0104] refer to Figure 28 After forming the word line 107, a third isolation layer 183 is formed, and the third isolation layer 183 fills the through hole f (refer to Figure 26 ).

[0105] In this embodiment, the third isolation layer 183 can be formed using the following process steps: a deposition process is performed to form a third isolation film covering the top surface of the insulating layer 106 located on the top surface of the second doped region III and completely filling the through hole f; the third isolation film is chemically and mechanically planarized until the top surface of the insulating layer 106 is exposed, with the remaining third isolation film serving as the third isolation layer 183. The third isolation film is made of the same material as the first and second isolation layers, both comprising silicon nitride. In other embodiments, the third isolation film can also be chemically and mechanically planarized until the top surface of the second doped region is exposed, i.e., the insulating layer located on the top surface of the second doped region is simultaneously removed, with the remaining third isolation film serving as the third isolation layer.

[0106] Continue to refer Figure 28 , remove the insulating layer 106 located on the top surface of the second doping region III, and use an epitaxial growth process to form an initial transition layer 128 on the top surface of the second doping region III, and the orthographic projection of the initial transition layer 128 on the substrate 11 covers the orthographic projection of the second doping region III on the substrate 11.

[0107] In addition, in the epitaxial growth process step, the initial transition layer 128 is also doped with the same type of doping ions as those in the second doping region III, and the doping concentration of the doping ions in the initial transition layer 128 is greater than the doping concentration in the second doping region III, then the resistance of the initial transition layer 128 is less than the resistance of the second doping region III.

[0108] On the one hand, the use of the epitaxial growth process is beneficial to improving the continuity between the second doped region III and the initial transition layer 128, reducing contact defects caused by different lattice characteristics or lattice dislocations, reducing contact resistance caused by contact defects, and improving the carrier transmission capacity and movement speed, thereby improving the conductivity between the second doped region III and the initial transition layer 128, and reducing the heat generated during the operation of the semiconductor structure; on the other hand, the use of the epitaxial growth process is beneficial to increasing the positive projection of the initial transition layer 128 on the substrate 11, which is beneficial to making the positive projection area of the initial transition layer 128 on the substrate 11 larger than the positive projection area of the second doped region III on the substrate 11. It can be used as a mask subsequently to avoid the formation of a second dielectric layer surrounding the side wall of the second doped region III from being etched to expose the second doped region III, so as to ensure that the subsequently formed second dielectric layer has a good protective effect on the second doped region III.

[0109] Combined with reference Figure 28 and Figure 29 Using the initial transition layer 128 as a mask, the first isolation layer 163, the second isolation layer 173, and the third isolation layer 183 are etched to expose the sidewalls of the second doped region III. The top surface of the remaining first isolation layer 163 is no higher than the top surface of the word line 107. The orthographic projection of the initial transition layer 128 on the substrate 11 covers the orthographic projection of the second doped region III on the substrate 11, which helps prevent the semiconductor channel 105 from being etched during this step.

[0110] refer to Figure 30 , forming a conformal covering the surface of the initial transition layer 128, the sidewall of the second doped region III, the top surface of the word line 107 and the first isolation layer 163 (reference Figure 29 ); chemically and mechanically planarize the second dielectric film until the surface of the initial transition layer 128 is exposed, and then etch the remaining second dielectric layer using the initial transition layer 128 as a mask. Because the orthographic projection area of the initial transition layer 128 on the substrate 11 is larger than the orthographic projection area of the second doped region III on the substrate 11, this facilitates removing the second dielectric film located on the surface of the initial transition layer 128, the top surface of the first isolation layer 163, and a portion of the top surface of the word line 107 while preventing etching of the second dielectric film directly opposite the orthographic projection of the initial transition layer 128 on the substrate 11, thereby forming the second dielectric layer 123 surrounding the sidewalls of the second doped region III, thereby ensuring that the second dielectric layer 123 effectively protects the second doped region III. The second dielectric film can be formed using a deposition process.

[0111] Further, refer to Figure 30 , the remaining first isolation layer 163 is removed to expose the top surface of the initial bit line 124 .

[0112] In other embodiments, the first isolation layer, the second isolation layer and the third isolation layer are etched using the initial transition layer as a mask to expose the initial bit line and the sidewall of the second doped region; then the exposed sidewall of the second doped region is thermally oxidized to form a second dielectric layer.

[0113] refer to Figures 1 to 4 The exposed initial bit line 124 and the initial transition layer 128 are metallized to form a bit line 104 . The material of the bit line 104 includes a metal semiconductor compound 114 .

[0114] Specifically, a metal layer is formed on the surface of the initial transition layer 128 and the top surface of the initial bit line 124. The metal layer provides metal elements for the subsequent formation of the bit line. The metal layer is also located on the exposed surfaces of the second dielectric layer 123, the word line 107, and the first dielectric layer 113. The material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0115] Annealing is performed to convert a portion of the initial transition layer 128 into the metal contact layer 108 and a portion of the initial bit line 124 (refer to FIG. Figure 30 ) is converted into bit line 104.

[0116] After forming the bit line 104, the remaining metal layer is removed.

[0117] In some embodiments, during the annealing process, the metal layer reacts with the initial transition layer 128 and the initial bit line 124, and a portion of the initial transition layer 128 is converted into the metal contact layer 108, and a portion of the initial bit line 124 is converted into the bit line 104. Specifically, in one example, referring to Figure 2 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced apart from each other; in another example, referring to Figure 3 , multiple metal-semiconductor compounds 114 in the same bit line 104 are interconnected.

[0118] In other embodiments, the entire thickness of the initial transition layer can be converted to a metal contact layer, and the entire thickness of the initial bit line can be converted to a bit.

[0119] In other embodiments, when the initial transition layer is not formed on the top surface of the second doped region, the insulating layer on the top surface of the second doped region is not removed first, and only the initial bit line is metallized later. After the bit line is formed, the insulating layer on the top surface of the second doped region is removed. Figure 30 and Figures 1 to 4, forming a third dielectric layer 133, the third dielectric layer 133 fills the first space between adjacent first dielectric layers 113, the second space between adjacent word lines 107, and the third space between adjacent second dielectric layers 123, for achieving electrical insulation between adjacent semiconductor channels 105 and adjacent word lines 107. In some examples, referring to Figure 5 When forming the third dielectric layer 133 , the third dielectric layer 133 located in the second interval may further have gaps.

[0120] In some other examples, reference Figures 10 to 14 and Figures 31 to 35 The steps of forming the first dielectric layer 113, the insulating layer 106, the word line 107 and the second dielectric layer 123 include the following:

[0121] refer to Figures 10 to 14 An initial first dielectric layer 113 a is formed, the initial first dielectric layer 113 a surrounds the sidewalls of the semiconductor channel 105, and a fourth gap e is formed between the initial first dielectric layers 113 a on the sidewalls of adjacent semiconductor channels 105 on the same initial bit line 124; a first isolation layer 163 is formed, the first isolation layer 163 fills the fourth gap e, and the material of the first isolation layer 163 is different from that of the initial first dielectric layer 113 a.

[0122] Specifically, the steps of forming the initial first dielectric layer 113 a and the first isolation layer 163 are the same as those in the above example and are not described herein in detail.

[0123] refer to Figure 31 , etching part of the initial first dielectric layer 113a (refer to Figure 14 ) until the sidewalls of the second doped region III and the sidewalls of the channel region II are exposed, and the remaining initial first dielectric layer 113a serves as the first dielectric layer 113.

[0124] refer to Figures 32 to 33 , a protective layer 116 is formed to cover the sidewalls of the second doping region III and the sidewalls of the channel region II, and a sixth gap k is present between the protective layer 116 and the first isolation layer 163. The protective layer 116 on the sidewalls of the channel region II is the insulating layer 106, and the protective layer 116 covering the sidewalls of the second doping region III is the second dielectric layer 123.

[0125] Further, refer to Figure 33 The sixth spacer k is also located between the protection layers 116 on the sidewalls of the adjacent semiconductor channels 105 of the adjacent initial bit lines 124 .

[0126] In this embodiment, the semiconductor channel 105 is made of silicon. The step of forming the protective layer 116 includes performing a thermal oxidation treatment on the exposed sidewalls of the channel region II and the sidewalls and top surface of the second doped region III. The protective layer 116 then covers the remaining sidewall surfaces of the channel region II and the remaining second doped region III, and covers the remaining top surface of the second doped region III. In other embodiments, the protective layer covering the sidewalls of the channel region and the sidewalls and top surface of the second doped region can also be formed by a deposition process.

[0127] Due to the thermal oxidation treatment of the exposed sidewalls of channel region II and second doped region III, portions of channel region II and second doped region III are converted into protective layer 116, making the orthographic projections of channel region II and second doped region III on substrate 11 smaller than the orthographic projection of first doped region I on substrate 11. This facilitates the formation of channel region II and second doped region III with a smaller cross-sectional area in a cross section perpendicular to direction Z pointing from initial bit line 124 to semiconductor channel 105, without using an etching process. This improves the control capability of subsequently formed word lines over channel region II, thereby facilitating the on / off control of GAA transistors.

[0128] In this embodiment, the protective layer 116 located on the top surface of the remaining second doped region III is removed in a subsequent process step. In other embodiments, the protective layer located on the top surface of the remaining second doped region can be removed after the thermal oxidation treatment, leaving only the protective layer covering the remaining channel region and the sidewall surface of the remaining second doped region.

[0129] refer to Figures 34 to 35 , forming an initial word line, the initial word line completely filling the sixth spacer k and also located between the protective layer 116 on the sidewalls of the semiconductor channel 105 adjacent to the initial bit line 124; removing a portion of the initial word line, and the remaining initial word line serving as word line 107, which only surrounds the sidewalls of the insulating layer 106 located on the sidewalls of the channel region II. The initial word line can be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0130] The initial word line fills the sixth space k in a self-aligned manner, which is beneficial for forming a word line 107 with precise dimensions in a self-aligned manner.

[0131] After forming the word line 107, the steps of forming a third isolation layer, forming an initial transition layer, metallizing the initial transition layer and the initial bit line to form a metal contact layer and the bit line, and forming a third dielectric layer are the same as the above example and are not repeated here.

[0132] Furthermore, a capacitor structure (not shown) is formed on the surface formed by the metal contact layer 108 and the third dielectric layer 133. In other embodiments, the metal contact layer may not be formed, and after removing the insulating layer located on the top surface of the second doped region, the capacitor structure is directly formed on the surface formed by the second doped region and the third dielectric layer.

[0133] In summary, by forming the first dielectric layer 113 and the second dielectric layer 123, the first dielectric layer 113 is etched using the second dielectric layer 123 as a mask to form a cavity structure of a specific shape. A deposition process is used to self-align and form a word line 107 of precise dimensions within the cavity structure. This eliminates the need to design the dimensions of the word line 107 through an etching process, thereby simplifying the steps for forming the word line 107. Furthermore, by regulating the dimensions of the cavity structure, a small-sized word line 107 can be obtained. Furthermore, metallization treatment is performed on the initial bit line 124 and the initial transition layer 128, thereby reducing the resistance of the ultimately formed bit line 104 and metal contact layer 108. This allows the metal contact layer 108 to form an ohmic contact with the capacitor structure, preventing direct contact between the capacitor structure and the semiconductor material, thereby forming a Schottky barrier contact. This reduces the contact resistance between the second doped region III and the capacitor structure, thereby reducing the energy consumption of the semiconductor structure during operation and improving the electrical performance of the semiconductor structure.

[0134] Those skilled in the art will appreciate that the above-described embodiments are specific examples of the present invention, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; A bit line is located on the substrate, and the material of the bit line includes a metal semiconductor compound; a semiconductor channel located on a surface of the bit line, wherein in a direction along the substrate pointing to the bit line, the semiconductor channel comprises a first doped region, a channel region, and a second doped region arranged in sequence, wherein the first doped region contacts the bit line; a first dielectric layer covering the sidewall surface of the first doped region, wherein a first gap exists between the first dielectric layers on adjacent sidewalls of the first doped region on the same bit line; an insulating layer covering the sidewall surface of the channel region; word lines, covering the sidewall surface of the insulating layer away from the channel region, with a second gap between adjacent word lines; a second dielectric layer covering a surface of a sidewall of the second doping region, wherein a third gap exists between the second dielectric layers located on adjacent sidewalls of the second doping region; a third dielectric layer, located in the first interval, the second interval, and the third interval; It also includes: a metal contact layer, located on a top surface of the second doping region away from the substrate, and the metal semiconductor compound and the metal contact layer contain the same metal element; It also includes: a transition layer, located between the second doping region and the metal contact layer, and the metal contact layer wraps the transition layer, the transition layer and the second doping region are doped with the same type of doping ions, and the doping concentration of the doping ions in the transition layer is greater than the doping concentration in the second doping region, and the doping ions are one of N-type ions or P-type ions.

2. The semiconductor structure according to claim 1, wherein The orthographic projection of the metal contact layer on the substrate covers the orthographic projection of the second doped region on the substrate.

3. The semiconductor structure according to claim 1, wherein: The substrate, the bit line, and the semiconductor channel have the same semiconductor element.

4. The semiconductor structure according to claim 1, wherein: The first doping region, the channel region and the second doping region are doped with the same type of doping ions, and the doping concentration of the doping ions in the first doping region is consistent with the doping concentration in the channel region and the second doping region, and the doping ions are one of N-type ions or P-type ions.

5. The semiconductor structure according to claim 1, wherein An orthographic projection of the channel region on the substrate is smaller than an orthographic projection of the second doping region on the substrate, and smaller than an orthographic projection of the first doping region on the substrate.

6. The semiconductor structure according to claim 1, wherein The insulating layer and the second dielectric layer are of the same film layer structure.

7. The semiconductor structure according to claim 1, wherein: An orthographic projection of the periphery of the insulating layer on the substrate is smaller than an orthographic projection of the periphery of the second dielectric layer on the substrate.

8. The semiconductor structure according to claim 1, wherein: The first dielectric layer includes a fourth dielectric layer and a fifth dielectric layer. The fourth dielectric layer is located in the gap between adjacent bit lines and in the gap between adjacent first doped regions on adjacent bit lines. The fifth dielectric layer is located on the sidewall of the adjacent first doped region on the same bit line and on the sidewall of the fourth dielectric layer.

9. The semiconductor structure according to claim 1, wherein: The third dielectric layer located in the second interval has a gap therein.

10. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming an initial bit line on the substrate, and forming a semiconductor channel on a surface of the initial bit line away from the substrate, wherein the semiconductor channel comprises a first doped region, a channel region, and a second doped region arranged in sequence in a direction along the substrate toward the initial bit line; forming a first dielectric layer covering the sidewall surface of the first doped region, with a first gap between the first dielectric layers on adjacent sidewalls of the first doped region on the same initial bit line; forming an insulating layer covering the sidewall surface of the channel region; forming word lines covering sidewall surfaces of the insulating layer away from the channel region, with a second gap between adjacent word lines; forming a second dielectric layer covering the sidewall surface of the second doped region, with a third spacer between the second dielectric layers located on adjacent sidewalls of the second doped region, the first spacer, the second spacer, and the third spacer being connected and exposing a portion of the initial bit line; Performing a metallization process on the exposed initial bit line to form a bit line, wherein the material of the bit line includes a metal semiconductor compound; After forming the word line and before forming the second dielectric layer, the method further includes: forming an initial transition layer on a top surface of the second doped region away from the substrate using an epitaxial growth process, wherein the initial transition layer and the second doped region are doped with the same type of dopant ions, the dopant concentration of the dopant ions in the initial transition layer is greater than the dopant concentration in the second doped region, the dopant ions are either N-type ions or P-type ions, and an orthographic projection of the initial transition layer on the substrate covers an orthographic projection of the second doped region on the substrate; The step of performing the metallization process on the initial bit line further includes: performing the metallization process on the initial transition layer.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The step of forming the first dielectric layer includes: forming an initial first dielectric layer, wherein the initial first dielectric layer surrounds the sidewalls of the semiconductor channel, and a fourth gap exists between the initial first dielectric layers on adjacent sidewalls of the semiconductor channel on the same initial bit line; forming a first isolation layer, wherein the first isolation layer completely fills the fourth gap, and a material of the first isolation layer is different from a material of the initial first dielectric layer; Etching a portion of the initial first dielectric layer until the sidewall of the second doped region is exposed; forming a second isolation layer, wherein the second isolation layer surrounds the sidewalls of the second doped region and the sidewalls of the first isolation layer, the second isolation layer located on the sidewalls of the second doped region and the second isolation layer located on the sidewalls of the first isolation layer jointly form a through hole, the bottom of the through hole exposes the initial first dielectric layer, and the material of the second isolation layer is different from that of the initial first dielectric layer; The initial first dielectric layer exposed by the through hole and located on the sidewall of the channel region is removed, and the remaining initial first dielectric layer serves as the first dielectric layer.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The step of forming the insulating layer includes: The exposed sidewalls of the channel region are subjected to thermal oxidation treatment to form the insulating layer, and the insulating layer covers the remaining sidewall surfaces of the channel region, and a fifth spacer is provided between the insulating layer and the first isolation layer.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: The steps of forming the word line include: forming an initial word line, wherein the initial word line completely fills the fifth spacer and the through hole, and the initial word line is also located between the insulating layers on the sidewalls of the channel region adjacent to the initial bit line; The initial word line located in the through hole is removed, and the remaining initial word line serves as the word line.

14. The method for manufacturing a semiconductor structure according to claim 10, wherein: The step of forming the first dielectric layer includes: forming an initial first dielectric layer, wherein the initial first dielectric layer surrounds the sidewalls of the semiconductor channel, and a fourth gap exists between the initial first dielectric layers on adjacent sidewalls of the semiconductor channel on the same initial bit line; forming a first isolation layer, wherein the first isolation layer completely fills the fourth gap, and a material of the first isolation layer is different from a material of the initial first dielectric layer; A portion of the initial first dielectric layer is etched until the sidewalls of the second doped region and the sidewalls of the channel region are exposed, and the remaining initial first dielectric layer serves as the first dielectric layer.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein: The steps of forming the insulating layer and the second dielectric layer include: A protective layer is formed covering the sidewalls of the second doped region and the sidewalls of the channel region, and a sixth spacer is provided between the protective layer and the first isolation layer. The protective layer on the sidewalls of the channel region is the insulating layer, and the protective layer covering the sidewalls of the second doped region is the second dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: The steps of forming the word line include: forming an initial word line, wherein the initial word line completely fills the sixth space and is also located between the protection layers on the sidewalls of the semiconductor channel portion adjacent to the initial bit line; Part of the initial word line is removed, and the remaining initial word line is used as the word line, and the word line only surrounds the side wall of the insulating layer located on the side wall of the channel region.

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