Methods, apparatus, equipment and computer-readable storage media for defect detection of wafers

Abstract

This application provides a method, apparatus, device, and computer-readable storage medium for defect detection of a wafer. The wafer defect detection method includes: acquiring structural feature information of the wafer surface; dividing the wafer surface into regions based on the structural feature information, and determining structural identification information for each region; determining a defect detection strategy matching each region based on the structural identification information; and detecting the wafer based on the defect detection strategy. According to embodiments of this application, the detection sensitivity requirements of different regions on the wafer can be reconciled.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method, apparatus, device and computer-readable storage medium for defect detection of wafers. Background Technology

[0002] Currently, when inspecting wafers, related technologies typically consider the coverage of the inspection, but they do not make detailed distinctions on the surface of the wafer being inspected. This can easily lead to the following problems:

[0003] (1) For detection methods with high detection speed / efficiency, such as optical inspection, the resolution is limited by the physical limits of the detection system and cannot meet the requirements for smaller process nodes. Small defects are easily missed during the detection process. Therefore, when using this type of detection method, it may not be able to meet the detection requirements of high-order processes and may have a high false detection rate.

[0004] (2) For detection methods with low detection speed but high detection resolution, such as electron beam detection methods, since they usually use the same "detection sensitivity" to detect all detection areas on the wafer, for example, scanning the image with the same pixel size, and then using a unified algorithm and detection threshold to complete defect detection, it is difficult to reconcile the detection sensitivity requirements of different areas on the wafer, which can easily lead to problems such as the detection speed being unable to cover enough areas and the inability to obtain statistically significant sampling areas.

[0005] Therefore, how to reconcile the detection sensitivity requirements of different regions on the chip is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] This application provides a method, apparatus, device, and computer-readable storage medium for defect detection of wafers, which can reconcile the detection sensitivity requirements of different areas on the wafer.

[0007] In a first aspect, embodiments of this application provide a defect detection method for a wafer, the method comprising:

[0008] Obtain structural feature information of the wafer surface;

[0009] Based on structural feature information, the surface of the wafer is divided into regions, and the structural identification information of each region is determined.

[0010] Based on the structural identification information of different regions, determine the defect detection strategies that match different regions.

[0011] Defect detection strategies are used to inspect wafers.

[0012] Optionally, obtain structural feature information of the wafer surface, including:

[0013] Calculate the mask error enhancement factor on the surface of the wafer;

[0014] Based on the mask error enhancement factor, the structural feature information of the wafer surface is obtained.

[0015] Optionally, based on the structural identification information of different regions, a defect detection strategy matching different regions can be determined, including:

[0016] Based on the structural identification information of different regions, the detection sensitivity matching different regions is determined respectively;

[0017] Based on the detection sensitivity, defect detection strategies matching different regions are determined.

[0018] Optionally, the structural feature information includes at least one of the following:

[0019] The first piece of information used to characterize whether the surface structure of a wafer is prone to defects during the manufacturing process;

[0020] Secondary information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer;

[0021] Third information used to indicate whether the surface structure of a wafer is insensitive to the final chip performance.

[0022] Optionally, the defect detection method for the wafer also includes:

[0023] Determine the data format used when recording the design information of the chip;

[0024] Use the same format as the data format to record the structural identification information of different areas.

[0025] Optionally, based on the structural identification information of different regions, the detection sensitivity matching different regions is determined separately, including:

[0026] Based on the structural identification information of different regions, calculate the corresponding weight value for each point on the wafer;

[0027] Based on the weight values, the detection sensitivity matching different regions is determined.

[0028] Optionally, based on weight values, the detection sensitivity matched to different regions can be determined separately, including:

[0029] If the weight value is greater than the preset weight threshold, then the first target sensitivity that is greater than the preset sensitivity threshold is selected as the detection sensitivity.

[0030] If the weight value is less than the preset weight threshold, then the second target sensitivity, which is less than the preset sensitivity threshold, is selected as the detection sensitivity.

[0031] Optionally, the data format used when recording chip design information is determined, including:

[0032] Determine the marking area identifier, the type of detection equipment, the size of the detection spot, the detection algorithm parameters, and / or the automatic defect classification parameters.

[0033] Optionally, based on the structural identification information of different regions, a defect detection strategy matching different regions can be determined, including:

[0034] Determine the importance and uniqueness of each pattern on the chip in the circuit design;

[0035] Based on the structural identification information, importance information, and uniqueness information of different regions, defect detection strategies matching different regions are determined.

[0036] Optionally, the inspection equipment used to perform the defect detection method for the wafer includes optical inspection equipment and / or electron beam inspection equipment, and the inspection equipment is connected to each other via a dedicated or general-purpose transfer system.

[0037] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a dedicated material transfer channel.

[0038] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a common material transfer channel.

[0039] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0040] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a dedicated material transfer channel.

[0041] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0042] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a common material transfer channel.

[0043] Secondly, embodiments of this application provide a defect detection device for a wafer, the device comprising:

[0044] The acquisition module is used to acquire structural feature information of the wafer surface.

[0045] The segmentation module is used to divide the surface of the wafer into regions based on structural feature information, and to determine the structural identification information of different regions after segmentation.

[0046] The determination module is used to determine the defect detection strategy that matches different regions based on the structural identification information of different regions;

[0047] The inspection module is used to inspect wafers based on defect detection strategies.

[0048] Optional, the acquisition module includes:

[0049] The computing unit is used to calculate the mask error enhancement factor on the surface of the wafer;

[0050] The acquisition unit is used to acquire structural feature information of the wafer surface based on the mask error enhancement factor.

[0051] Optional, the defined modules include:

[0052] The sensitivity determination unit is used to determine the detection sensitivity that matches different regions based on the structural identification information of different regions.

[0053] The strategy determination unit is used to determine the defect detection strategy that matches different regions based on the detection sensitivity.

[0054] Optionally, the structural feature information includes at least one of the following:

[0055] The first piece of information used to characterize whether the surface structure of a wafer is prone to defects during the manufacturing process;

[0056] Secondary information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer;

[0057] Third information used to indicate whether the surface structure of a wafer is insensitive to the final chip performance.

[0058] Optionally, the defect detection device for the wafer also includes:

[0059] The format determination module is used to determine the data format used when recording the design information of the chip;

[0060] The recording module is used to record structural identification information of different areas in the same format as the data format.

[0061] Optional, the sensitivity determination unit includes:

[0062] The weight determination subunit is used to calculate the corresponding weight value for each point on the wafer based on the structural identification information of different regions.

[0063] The sensitivity determination subunit is used to determine the detection sensitivity that matches different regions based on the weight values.

[0064] Optional, a sensitivity determination subunit is used for:

[0065] If the weight value is greater than the preset weight threshold, then the first target sensitivity that is greater than the preset sensitivity threshold is selected as the detection sensitivity.

[0066] If the weight value is less than the preset weight threshold, then the second target sensitivity, which is less than the preset sensitivity threshold, is selected as the detection sensitivity.

[0067] Optional, a format determination module, used for:

[0068] Determine the marking area identifier, the type of detection equipment, the size of the detection spot, the detection algorithm parameters, and / or the automatic defect classification parameters.

[0069] Optional, determine the module, used for:

[0070] Determine the importance and uniqueness of each pattern on the chip in the circuit design;

[0071] Based on the structural identification information, importance information, and uniqueness information of different regions, defect detection strategies matching different regions are determined.

[0072] Optionally, the inspection equipment used to perform the defect detection method for the wafer includes optical inspection equipment and / or electron beam inspection equipment, and the inspection equipment is connected to each other via a dedicated or general-purpose transfer system.

[0073] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a dedicated material transfer channel.

[0074] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a common material transfer channel.

[0075] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0076] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a dedicated material transfer channel.

[0077] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0078] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a common material transfer channel.

[0079] Thirdly, embodiments of this application provide a defect detection device for a wafer, the device comprising:

[0080] The defect detection device for the wafer includes: a processor and a memory storing computer program instructions;

[0081] When the processor executes the computer program instructions, it implements the defect detection method for the wafer as described in the first aspect above.

[0082] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the defect detection method for a wafer as described in the first aspect above.

[0083] The wafer defect detection method, apparatus, device, and computer-readable storage medium of this application embodiment can acquire structural feature information of the wafer surface; then, based on the structural feature information, the wafer surface is divided into regions, and structural identification information of different regions is determined respectively; based on the structural identification information of different regions, a defect detection strategy matching the different regions is determined respectively; finally, the wafer is detected based on the defect detection strategy. In this way, different defect detection strategies can be used to detect different regions of the wafer surface, thereby reconciling the detection sensitivity requirements of different regions on the wafer. Attached Figure Description

[0084] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0085] Figure 1 This is a schematic flowchart of a defect detection method for a wafer provided in one embodiment of this application;

[0086] Figure 2 This is a schematic diagram illustrating an implementation method for a defect detection strategy provided in this application, which combines optical detection and electron beam detection with a dedicated material transfer channel for detection.

[0087] Figure 3 This is a schematic diagram illustrating an implementation method based on a defect detection strategy provided in this application, which combines optical detection and electron beam detection with a general material transfer channel for detection.

[0088] Figure 4 This is a schematic diagram illustrating an implementation method for a defect detection strategy provided in this application, which combines optical detection and multi-electron beam detection with a single-electron beam detection device and a dedicated material transfer channel.

[0089] Figure 5 A schematic diagram illustrating an implementation method for a defect detection strategy provided in this application, which combines optical detection and multi-electron beam detection with single-electron beam detection, along with a universal material transfer channel.

[0090] Figure 6 This is a schematic diagram of the structure of a wafer defect detection device provided in one embodiment of this application;

[0091] Figure 7 This is a schematic diagram of the structure of a defect detection device for a wafer provided in one embodiment of this application. Detailed Implementation

[0092] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0093] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0094] Currently, when inspecting wafers, related technologies typically consider the coverage of the inspection, but they do not make detailed distinctions on the surface of the wafer being inspected. This can easily lead to the following problems:

[0095] (1) For detection methods with high detection speed / efficiency, such as optical inspection, full coverage of the wafer surface is usually used. However, due to the physical limitations of the detection system, its resolution cannot meet the requirements for smaller process nodes. Small defects are easily missed during the detection process, which leads to problems such as the inability to meet the detection requirements of higher-order processes and the high false detection rate when using this type of detection method.

[0096] (2) For detection methods with low detection speed but high detection resolution, such as electron beam detection, sampling detection is usually used. Sampling detection refers to defining a detection area on the wafer surface and performing defect detection only within that area. When using this type of method, because it usually uses the same "detection sensitivity" to detect all detection areas on the wafer, for example, scanning the image with the same pixel size and then using a uniform algorithm and detection threshold to complete the defect detection, it is difficult to reconcile the detection sensitivity requirements of different areas on the wafer. This can easily lead to problems such as the detection speed not being able to cover enough areas and not being able to obtain statistically significant sampling areas.

[0097] For example, in practical applications, certain areas on a chip are highly sensitive to defects; even small defects can affect the chip's electrical performance. For ease of description, these areas will be referred to as "critical areas." However, some areas, such as dummy fill areas, have little impact on the chip's final performance due to defects. Defects in these areas do not affect the chip's electrical performance; these areas will be called "unimportant areas." If the same "detection sensitivity"—for example, the same pixel size and the same detection threshold—is used for defect detection across all areas of the chip, the following problems arise: In critical areas, increasing the detection sensitivity is necessary to detect small defects. This means that in uncritical areas, insignificant small defects may be reported, rendering subsequent processing of these defects—including automatic defect classification, recording, and storage—meaningless, a waste of detection resources, and a reduction in detection efficiency. Conversely, lowering the detection sensitivity reduces insignificant defects in uncritical areas but may cause small defects in critical areas to be missed. This is a more serious problem; in other words, the detection method struggles to reconcile the different sensitivity requirements of various areas on the chip.

[0098] To address the problems of the prior art, embodiments of this application provide a method, apparatus, device, and computer-readable storage medium for detecting defects in a wafer. The defect detection method for a wafer provided in this application embodiment will be described first below.

[0099] Figure 1 A schematic flowchart of a defect detection method for a wafer according to an embodiment of this application is shown. Figure 1 As shown, the method includes the following steps:

[0100] S001, Obtain structural feature information of the wafer surface.

[0101] The structural feature information may include at least one of the following:

[0102] The first piece of information used to characterize whether the surface structure of a wafer is prone to defects during the manufacturing process;

[0103] Secondary information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer;

[0104] Third information used to indicate whether the surface structure of a wafer is insensitive to the final chip performance.

[0105] In this embodiment, although the patterns covering the wafer surface vary in shape, density, and structural variation (many repeating structures, but with inconsistent repetition periods and numbers), they are all designed by the designer. Therefore, all structural features on the wafer surface can be precisely known. For example, which parts of the structure are prone to defects during manufacturing; which parts are sensitive to which types of defects; which parts are dummy fills and do not require defect detection; which parts are insensitive to the final chip performance; and which parts, due to redundancy design, will not affect the final performance even if defects occur. Based on this, before inspecting the wafer, the structural feature information of the wafer surface can be obtained to determine the corresponding defect detection strategy.

[0106] In one alternative implementation, the structural feature information of the wafer surface can be obtained through the following steps:

[0107] (1) Calculate the mask error enhancement factor on the surface of the wafer;

[0108] (2) Obtain structural feature information of the wafer surface based on the mask error enhancement factor.

[0109] In this embodiment, the mask error enhancement factor of the wafer surface can be quantified and calculated first. Then, based on the mask error enhancement factor, the structural feature information of the wafer surface can be obtained. For example, when the mask error enhancement factor is determined to be a preset first value, the wafer surface corresponding to the mask error enhancement factor is considered to be an error-prone area (hot spots). Alternatively, when the mask error enhancement factor is determined to be a preset second value, the wafer surface corresponding to the mask error enhancement factor is considered to be a "dummy fill" area, that is, an area where defect detection is not required.

[0110] The first and second preset values ​​can be determined based on actual work experience.

[0111] It should be noted that the above-described methods for obtaining structural feature information of the wafer surface are merely illustrative examples of embodiments of this application and do not impose any limitations on the embodiments of this application.

[0112] S002, Based on the structural feature information, the surface of the wafer is divided into regions, and the structural identification information of the different regions after division is determined.

[0113] In this embodiment of the application, after obtaining the structural feature information of the wafer surface, the wafer surface can be divided into regions based on the structural feature information, and the structural identification information of the different regions after division can be determined respectively.

[0114] For example, following the example given in S001, if the structural feature information of a certain part of the wafer surface is determined to be error-prone, then the area corresponding to that part can be divided into error-prone areas, and the structural identification information of that area can be determined as hot spots area, or denoted as "error-prone area".

[0115] For example, if we determine that the structural features of a certain part of the wafer surface are not sensitive to the final chip performance, then the area corresponding to that part can be divided into areas that do not need to be defect-detected, and the structural identification information of that area can be determined as a dummy fill area, or simply "area that does not need to be defect-detected".

[0116] It should be noted that the above-described methods for determining the structural identification information of different regions are merely illustrative examples of embodiments of this application and do not impose any limitations on the embodiments of this application.

[0117] In one optional implementation, after determining the structural identification information of the different regions after division, the data format used when recording the wafer's design information can also be determined; the structural identification information of the different regions is recorded using the same format as the data format. Using the same format as the data format to record the structural identification information of the different regions can also be understood as the division of the detection area being accurate to the same scale as each polygon on the wafer.

[0118] Optionally, the data format used when recording the design information of the wafer may include, but is not limited to: marking area identifiers, such as marking area ID, inspection equipment type, inspection spot size, inspection algorithm parameters, and automatic defect classification (ADC) parameters.

[0119] S003, Based on the structural identification information of different regions, determine the defect detection strategy that matches different regions.

[0120] The defect detection strategy may include information such as detection sensitivity.

[0121] In this embodiment, a weight can be calculated for each point on the wafer based on the structural identification information of different regions. Then, a defect detection strategy matching different regions can be determined according to the weight. For example, the sensitivity required for detection in different regions can be automatically selected according to the weight. For example, higher sensitivity is used for areas with high weight, and lower sensitivity is used for areas with low weight.

[0122] Alternatively, in one implementation, a comprehensive inspection plan can be developed based on the structural identification information of different regions, combined with the importance of each pattern on the chip in the circuit design and whether it is unique, so as to determine the defect detection strategy that matches different regions.

[0123] In an alternative implementation, S003 can also be achieved through the following steps:

[0124] (1) Determine the detection sensitivity that matches different regions based on the structural identification information of different regions;

[0125] (2) Determine the defect detection strategy that matches different regions based on the detection sensitivity.

[0126] S004, the wafer is inspected based on the defect detection strategy.

[0127] In this embodiment of the application, after determining the defect detection strategy that matches different regions, the wafer can be inspected based on the defect detection strategy.

[0128] The inspection equipment used to inspect wafers based on defect detection strategies can be independent inspection equipment, such as optical inspection equipment or electron beam inspection equipment. Furthermore, the inspection equipment can be connected via dedicated or general-purpose transport systems, such as fully automated overhead transportation (OHT) systems.

[0129] like Figures 2-5 The diagram shown illustrates four implementation methods for inspecting wafers using inspection equipment, as provided in this application.

[0130] in, Figure 2 This is a schematic diagram illustrating an implementation method based on a defect detection strategy provided in this application, which combines optical and electron beam detection with a dedicated material transfer channel for detection. Figure 2 As shown, the testing equipment includes one optical testing device and two electron beam testing devices. The optical testing device and the two electron beam testing devices are connected by a dedicated / proprietary material transfer channel.

[0131] Figure 3 This is a schematic diagram illustrating an implementation method based on a defect detection strategy provided in this application, which combines optical detection and electron beam detection with a general material transfer channel for detection. Figure 3 As shown, the testing equipment includes one optical testing device and two electron beam testing devices. The optical testing device and the two electron beam testing devices are connected by a general material transfer channel.

[0132] Figure 4 This diagram illustrates an implementation method for a defect detection strategy provided in this application, which combines optical inspection and multi-electron beam inspection with a single-electron beam inspection device and a dedicated material transfer channel. Figure 4 As shown, the testing equipment includes one optical testing device, one multi-electron beam testing device, and two single-electron beam testing devices. The optical testing device, the multi-electron beam testing device, and the two single-electron beam testing devices are connected to each other through a dedicated / proprietary material transfer channel.

[0133] Figure 5 This diagram illustrates an implementation method based on a defect detection strategy provided in this application, which combines optical detection with multi-electron beam detection and single-electron beam detection, along with a common material transfer channel, such as OHT. Figure 5 As shown, the testing equipment includes one optical testing device, one multi-electron beam testing device, and two single-electron beam testing devices. The optical testing device, the multi-electron beam testing device, and the two single-electron beam testing devices are connected to each other through a common material transfer channel.

[0134] Optionally, in practical applications, the detection device in this embodiment can be a comprehensive detection system with multiple detection paths, integrating multiple detection units with different capabilities, and may also include a controller. The controller can understand the capabilities of all detection units within the detection device, as well as various possible detection paths; the controller can understand the structural marking information on the surface of the wafer.

[0135] In one optional implementation, after receiving a detection task, the controller can read and analyze the structural marking information on the surface of the wafer, and then combine and optimize the corresponding defect detection scheme. Optionally, the optimized scheme can have the maximum detection productivity as the objective function.

[0136] The controller can be a specific intelligent control device or an algorithm capable of implementing control functions. When the controller is an algorithm capable of implementing control functions, the algorithm needs to optimize the allocation of various detection tasks in the system to achieve optimal detection productivity.

[0137] The wafer defect detection method according to the embodiments of this application can obtain structural feature information of the wafer surface; then, based on the structural feature information, the wafer surface is divided into regions, and structural identification information of different regions is determined respectively; based on the structural identification information of different regions, a defect detection strategy matching different regions is determined respectively; finally, the wafer is detected based on the defect detection strategy. In this way, different defect detection strategies can be used to detect different regions of the wafer surface, thereby reconciling the detection sensitivity requirements of different regions on the wafer.

[0138] On the other hand, it allows the detection process to flexibly adjust detection strategies, optimize detection execution, and adjust detection sensitivity according to the situation, thereby optimizing the overall detection productivity of defect detection.

[0139] Figure 6 A schematic diagram of the structure of a wafer defect detection device provided in an embodiment of this application is shown. Figure 6 As shown, the device includes:

[0140] Acquisition module 601 is used to acquire structural feature information of the surface of the wafer;

[0141] The partitioning module 602 is used to partition the surface of the wafer into regions based on structural feature information, and to determine the structural identification information of the different regions after partitioning.

[0142] The determination module 603 is used to determine the defect detection strategy that matches different regions based on the structural identification information of different regions;

[0143] The detection module 604 is used to inspect the wafer based on a defect detection strategy.

[0144] Optionally, module 601 includes:

[0145] The computing unit is used to calculate the mask error enhancement factor on the surface of the wafer;

[0146] The acquisition unit is used to acquire structural feature information of the wafer surface based on the mask error enhancement factor.

[0147] Optionally, module 603 includes:

[0148] The sensitivity determination unit is used to determine the detection sensitivity that matches different regions based on the structural identification information of different regions.

[0149] The strategy determination unit is used to determine the defect detection strategy that matches different regions based on the detection sensitivity.

[0150] Optionally, the structural feature information includes at least one of the following:

[0151] The first piece of information used to characterize whether the surface structure of a wafer is prone to defects during the manufacturing process;

[0152] Secondary information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer;

[0153] Third information used to indicate whether the surface structure of a wafer is insensitive to the final chip performance.

[0154] Optionally, the defect detection device for the wafer also includes:

[0155] The format determination module is used to determine the data format used when recording the design information of the chip;

[0156] The recording module is used to record structural identification information of different areas in the same format as the data format.

[0157] Optional, the sensitivity determination unit includes:

[0158] The weight determination subunit is used to calculate the corresponding weight value for each point on the wafer based on the structural identification information of different regions.

[0159] The sensitivity determination subunit is used to determine the detection sensitivity that matches different regions based on the weight values.

[0160] Optional, a sensitivity determination subunit is used for:

[0161] If the weight value is greater than the preset weight threshold, then the first target sensitivity that is greater than the preset sensitivity threshold is selected as the detection sensitivity.

[0162] If the weight value is less than the preset weight threshold, then the second target sensitivity, which is less than the preset sensitivity threshold, is selected as the detection sensitivity.

[0163] Optional, a format determination module, used for:

[0164] Determine the marking area identifier, the type of detection equipment, the size of the detection spot, the detection algorithm parameters, and / or the automatic defect classification parameters.

[0165] Optional, determine the module, used for:

[0166] Determine the importance and uniqueness of each pattern on the chip in the circuit design;

[0167] Based on the structural identification information, importance information, and uniqueness information of different regions, defect detection strategies matching different regions are determined.

[0168] Optionally, the inspection equipment used to perform the defect detection method for the wafer includes optical inspection equipment and / or electron beam inspection equipment, and the inspection equipment is connected to each other via a dedicated or general-purpose transfer system.

[0169] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a dedicated material transfer channel.

[0170] Optionally, the inspection equipment for performing the defect inspection method on the wafer includes an optical inspection device and two electron beam inspection devices, wherein the optical inspection device and the two electron beam inspection devices are connected by a common material transfer channel.

[0171] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0172] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a dedicated material transfer channel.

[0173] Optionally, if the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment, a multi-electron beam inspection equipment, and two single-electron beam inspection equipment.

[0174] The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a common material transfer channel.

[0175] Figure 6 Each module / unit in the illustrated device has the ability to implement Figure 1 The functions of each step in the process and their corresponding technical effects are described in detail here for the sake of brevity.

[0176] Figure 7 A schematic diagram of the structure of a wafer defect detection device provided in an embodiment of this application is shown.

[0177] The defect detection device for a chip may include a processor 701 and a memory 702 storing computer program instructions.

[0178] Specifically, the processor 701 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0179] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where suitable, memory 702 may include removable or non-removable (or fixed) media. Where suitable, memory 702 may be internal or external to a defect detection device for a wafer. In a particular embodiment, memory 702 may be a non-volatile solid-state memory.

[0180] In one embodiment, memory 702 may be read-only memory (ROM). In one embodiment, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0181] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any of the wafer defect detection methods in the above embodiments.

[0182] In one example, the wafer defect detection device may also include a communication interface 703 and a bus 710. Wherein, as Figure 7 As shown, the processor 701, memory 702, and communication interface 703 are connected through bus 710 and complete communication with each other.

[0183] The communication interface 703 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0184] Bus 710 includes hardware, software, or both, that couples components of a defect detection device for a wafer together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 710 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0185] Furthermore, in conjunction with the wafer defect detection method in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the wafer defect detection methods in the above embodiments.

[0186] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0187] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0188] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0189] The aspects of this application have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0190] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for defect detection in a wafer, characterized in that, include: Obtain structural feature information of the wafer surface; Based on the structural feature information, the surface of the wafer is divided into regions, and the structural identification information of the different regions after division is determined respectively; Based on the structural identification information of the different regions, a defect detection strategy matching the different regions is determined respectively; The wafer is inspected based on the aforementioned defect detection strategy, wherein... The step of obtaining the structural feature information of the wafer surface includes: Calculate the mask error enhancement factor on the surface of the wafer; Based on the mask error enhancement factor, the structural feature information of the wafer surface is obtained.

2. The defect detection method for a wafer according to claim 1, characterized in that, Based on the structural identification information of the different regions, a defect detection strategy matching the different regions is determined, including: Based on the structural identification information of the different regions, the detection sensitivity matching the different regions is determined respectively; Based on the detection sensitivity, defect detection strategies matching the different regions are determined respectively.

3. The defect detection method for a wafer according to claim 1, characterized in that, The structural feature information includes at least one of the following: First information used to characterize whether the surface structure of the wafer is prone to defects during the manufacturing process; Second information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer; Third information used to indicate whether the surface structure of the wafer is insensitive to the final chip performance.

4. The defect detection method for a wafer according to claim 1, characterized in that, The method further includes: Determine the data format used when recording the design information of the chip; The structural identification information of the different regions is recorded using the same format as the data format.

5. The defect detection method for a wafer according to claim 4, characterized in that, Based on the structural identification information of the different regions, the detection sensitivity matching the different regions is determined respectively, including: Based on the structural identification information of the different regions, a corresponding weight value is calculated for each point on the wafer; Based on the weight values, the detection sensitivity matching the different regions is determined respectively.

6. The defect detection method for a wafer according to claim 5, characterized in that, Based on the weight values, the detection sensitivity matching the different regions is determined, including: If the weight value is greater than the preset weight threshold, then the first target sensitivity, which is greater than the preset sensitivity threshold, is selected as the detection sensitivity. If the weight value is less than a preset weight threshold, then a second target sensitivity less than the preset sensitivity threshold is selected as the detection sensitivity.

7. The defect detection method for a wafer according to claim 4, characterized in that, The data format used when determining the design information of the wafer includes: Determine the marking area identifier, the type of detection equipment, the size of the detection spot, the detection algorithm parameters, and / or the automatic defect classification parameters.

8. The defect detection method for a wafer according to claim 1, characterized in that, Based on the structural identification information of the different regions, a defect detection strategy matching the different regions is determined, including: Determine the importance and uniqueness of each pattern on the chip in the circuit design; Based on the structural identification information, importance information, and uniqueness information of the different regions, a defect detection strategy matching the different regions is determined.

9. The defect detection method for a wafer according to claim 1, characterized in that, The inspection equipment used to perform the defect detection method for the wafer includes optical inspection equipment and / or electron beam inspection equipment, and the inspection equipment is connected to each other through a dedicated or general-purpose transmission system.

10. The defect detection method for a wafer according to claim 9, characterized in that, The inspection equipment for performing the defect detection method of the wafer includes one optical inspection device and two electron beam inspection devices, wherein the one optical inspection device and the two electron beam inspection devices are connected by a dedicated material transfer channel.

11. The defect detection method for a wafer according to claim 9, characterized in that, The inspection equipment for performing the defect detection method of the wafer includes one optical inspection device and two electron beam inspection devices, wherein the one optical inspection device and the two electron beam inspection devices are connected by a common material transfer channel.

12. The defect detection method for a wafer according to claim 9, characterized in that, If the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes one of the optical inspection equipment, one of the multi-electron beam inspection equipment, and two of the single-electron beam inspection equipment. The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a dedicated material transfer channel.

13. The defect detection method for a wafer according to claim 9, characterized in that, If the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes one of the optical inspection equipment, one of the multi-electron beam inspection equipment, and two of the single-electron beam inspection equipment. The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a common material transfer channel.

14. A defect detection device for a wafer, characterized in that, The device includes: The acquisition module is used to acquire structural feature information of the wafer surface. The segmentation module is used to segment the surface of the wafer into regions based on the structural feature information, and to determine the structural identification information of the different regions after segmentation. The determination module is used to determine the defect detection strategy that matches the different regions based on the structural identification information of the different regions; The detection module is used to detect the wafer based on the defect detection strategy, wherein... The acquisition module includes: a calculation unit, used to calculate the mask error enhancement factor of the surface of the wafer; The acquisition unit is used to acquire structural feature information of the wafer surface based on the mask error enhancement factor.

15. The defect detection apparatus for a wafer according to claim 14, characterized in that, The module to be determined includes: The sensitivity determination unit is used to determine the detection sensitivity that matches the different regions based on the structural identification information of the different regions. The strategy determination unit is used to determine a defect detection strategy that matches the different regions based on the detection sensitivity.

16. The defect detection apparatus for a wafer according to claim 14, characterized in that, The structural feature information includes at least one of the following: First information used to characterize whether the surface structure of the wafer is prone to defects during the manufacturing process; Second information used to indicate the types of defects that are sensitive to and / or insensitive to the surface structure of the wafer; Third information used to indicate whether the surface structure of the wafer is insensitive to the final chip performance.

17. The defect detection apparatus for a wafer according to claim 14, characterized in that, The device further includes: The format determination module is used to determine the data format used when recording the design information of the wafer; The recording module is used to record the structural identification information of the different regions in the same format as the data format.

18. The defect detection apparatus for a wafer according to claim 15, characterized in that, The sensitivity determination unit includes: The weight determination subunit is used to calculate the corresponding weight value for each point on the wafer based on the structural identification information of the different regions. The sensitivity determination subunit is used to determine the detection sensitivity that matches the different regions according to the weight values.

19. The defect detection apparatus for a wafer according to claim 18, characterized in that, The sensitivity determination subunit is used for: If the weight value is greater than the preset weight threshold, then the first target sensitivity, which is greater than the preset sensitivity threshold, is selected as the detection sensitivity. If the weight value is less than a preset weight threshold, then a second target sensitivity less than the preset sensitivity threshold is selected as the detection sensitivity.

20. The defect detection apparatus for a wafer according to claim 17, characterized in that, The format determination module is used for: Determine the marking area identifier, the type of detection equipment, the size of the detection spot, the detection algorithm parameters, and / or the automatic defect classification parameters.

21. The defect detection apparatus for a wafer according to claim 14, characterized in that, The determining module is used for: Determine the importance and uniqueness of each pattern on the chip in the circuit design; Based on the structural identification information, importance information, and uniqueness information of the different regions, a defect detection strategy matching the different regions is determined.

22. The defect detection apparatus for a wafer according to claim 14, characterized in that, The inspection equipment used to perform the defect detection method for the wafer includes optical inspection equipment and / or electron beam inspection equipment, and the inspection equipment is connected to each other through a dedicated or general-purpose transmission system.

23. The defect detection apparatus for a wafer according to claim 22, characterized in that, The inspection equipment for performing the defect detection method of the wafer includes one optical inspection device and two electron beam inspection devices, wherein the one optical inspection device and the two electron beam inspection devices are connected by a dedicated material transfer channel.

24. The defect detection apparatus for a wafer according to claim 22, characterized in that, The inspection equipment for performing the defect detection method of the wafer includes one optical inspection device and two electron beam inspection devices, wherein the one optical inspection device and the two electron beam inspection devices are connected by a common material transfer channel.

25. The defect detection apparatus for a wafer according to claim 22, characterized in that, If the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes one of the optical inspection equipment, one of the multi-electron beam inspection equipment, and two of the single-electron beam inspection equipment. The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a dedicated material transfer channel.

26. The defect detection apparatus for a wafer according to claim 22, characterized in that, If the electron beam inspection equipment includes a multi-electron beam inspection equipment and a single-electron beam inspection equipment, then the inspection equipment for performing the defect inspection method of the wafer includes one of the optical inspection equipment, one of the multi-electron beam inspection equipment, and two of the single-electron beam inspection equipment. The optical inspection device, the multi-electron beam inspection device, and the two single-electron beam inspection devices are connected by a common material transfer channel.

27. A defect detection device for wafers, characterized in that, The defect detection device for the wafer includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the defect detection method for the wafer as described in any one of claims 1-13.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the defect detection method for a wafer as described in any one of claims 1-13.

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