R-2R network automatic error elimination circuit and method for ion source control circuit

Abstract

The present invention relates to an R-2R network automatic error elimination circuit and method for an ion source control circuit, so as to solve the technical problem that the existence of an error in a gas pressure control circuit causes an ion source control to be prone to deviation and manual adjustment is inconvenient. The error circuit includes a threshold voltage unit, a positive deviation discriminator, a negative deviation discriminator, a clock unit, a positive deviation counting unit, a negative deviation counting unit, a presettable addition and subtraction counter, a counting control unit and an R-2R network unit. The method includes: 1. Starting the circuit to adjust the presettable addition and subtraction counter to a base value; 2. The deviation discrimination unit compares the received voltage signal; by adjusting the deviation discrimination unit to adjust the presettable addition and subtraction counter and the deviation counting unit to adjust the presettable addition and subtraction counter, the digital quantity of the presettable addition and subtraction counter changes until the R-2R network unit outputs the target DC voltage.

Description

Technical Field

[0001] The invention relates to an automatic error elimination circuit, and in particular to an R-2R network automatic error elimination circuit and method used in an ion source control circuit. Background Art

[0002] The gas pressure control circuit in the existing ion source control circuit works in an automatic control mode, which has a hysteresis error, that is, an error voltage. During the normal operation of the neutron tube, the internal gas pressure is in a dynamic equilibrium state, and its gas pressure is controlled by the size of the hot wire current IF. In the original circuit, the size of the hot wire current IF can only be adjusted manually. Due to the hysteresis of the adjustment, it is very inconvenient to adjust and waste time. In order to avoid the deviation of the ion source caused by the existence of the error voltage, a solution to eliminate the error is urgently needed. Summary of the invention

[0003] The purpose of the present invention is to solve the technical problem that the existence of errors in the gas pressure control circuit leads to deviations in ion source control and inconvenient manual adjustment, and proposes an R-2R network automatic error elimination circuit and method for an ion source control circuit. The automatic error elimination circuit imitates manual adjustment of the hot wire current to eliminate the automatic control hysteresis error.

[0004] The technical solution of the present invention is:

[0005] An R-2R network automatic error elimination circuit for an ion source control circuit, which is special in that it includes a threshold voltage unit, a deviation discrimination unit, a clock unit, a deviation counting unit, a presettable addition and subtraction counter, a counting control unit, an R-2R network unit and a variable resistor;

[0006] The threshold voltage unit is used to generate a positive threshold voltage and a negative threshold voltage; the deviation discrimination unit includes a positive deviation discriminator and a negative deviation discriminator;

[0007] The positive deviation discriminator is used to output a positive deviation signal when the error voltage is greater than the positive threshold voltage; the negative deviation discriminator is used to output a negative deviation signal when the error voltage is less than the negative threshold voltage; the positive threshold voltage output terminal and the negative threshold voltage output terminal of the threshold voltage unit are respectively connected to an input terminal of the positive deviation discriminator and an input terminal of the negative deviation discriminator;

[0008] The clock unit is used to generate a clock enable signal;

[0009] The deviation counting unit is used to generate a cumulative subtraction signal and a cumulative addition signal according to the positive deviation signal and the negative deviation signal output, and the deviation counting unit includes a positive deviation counting unit and a negative deviation counting unit;

[0010] The output end of the clock unit is connected to the first input end of the positive deviation counting unit and the first input end of the negative deviation counting unit respectively; the second input end of the positive deviation counting unit is connected to the output end of the positive deviation discriminator, and the output end of the positive deviation counting unit is connected to an input end of a presettable add-subtract counter; the second input end of the negative deviation counting unit is connected to the output end of the negative deviation discriminator, and the output end of the negative deviation counting unit is connected to another input end of the presettable add-subtract counter; the two output ends of the presettable add-subtract counter are respectively connected to the input end of the counting control unit and the input end of the R-2R network unit; the two output ends of the counting control unit are respectively connected to the third input end of the positive deviation counting unit and the third input end of the negative deviation counting unit;

[0011] The presettable up / down counter is used to count up by one in response to an accumulation signal, or to count down by one in response to an accumulation signal;

[0012] The counting control unit is used to output a positive deviation counting enable signal or a negative deviation counting enable signal;

[0013] The output end of the R-2R network unit is connected to a fixed end of the variable resistor, the other fixed end of the variable resistor is grounded, and the output end of the variable resistor outputs a target DC voltage.

[0014] Furthermore, the threshold voltage unit includes a plurality of voltage-dividing resistors connected in series between a positive power supply and a negative power supply; the plurality of voltage-dividing resistors connected in series are used for voltage division to obtain a positive threshold voltage and a negative threshold voltage.

[0015] Further, the positive deviation discriminator includes a first amplifier and a first positive feedback circuit;

[0016] The non-inverting input terminal of the first amplifier is used to load the error voltage, and the inverting input terminal of the first amplifier is used to load the positive threshold voltage;

[0017] The first positive feedback circuit is connected between the output terminal and the non-phase input terminal of the first amplifier;

[0018] The output end of the first amplifier is connected to the second input end of the positive deviation counting unit;

[0019] The negative deviation discriminator includes a second amplifier and a second positive feedback circuit;

[0020] The inverting input terminal of the second amplifier is used to load the error voltage, and the non-inverting input terminal of the second amplifier is used to load the negative threshold voltage;

[0021] The second positive feedback circuit is connected between the output terminal and the non-phase input terminal of the second amplifier;

[0022] The output terminal of the second amplifier is connected to the second input terminal of the negative deviation counting unit.

[0023] Furthermore, the positive deviation signal, the negative deviation signal, the clock enable signal, the positive deviation count enable signal and the negative deviation count enable signal are high level valid; the cumulative reduction signal and the cumulative addition signal are low level valid;

[0024] The positive deviation counting unit is a first NAND gate, and the negative deviation counting unit is a second NAND gate.

[0025] Furthermore, the clock unit is a self-excited multivibrator, which is used to output a high-level narrow pulse as a clock enable signal.

[0026] Further, the presettable up-and-down counter is an eight-bit binary counter having eight counting output terminals;

[0027] The presettable add-subtract counter comprises two four-bit presettable add-subtract counters connected in series; the cumulative input end of the presettable add-subtract counter is electrically connected to the output end of the positive deviation counting unit; the cumulative input end of the presettable add-subtract counter is electrically connected to the output end of the negative deviation counting unit.

[0028] Furthermore, the counting control unit comprises an OR gate and a third NAND gate connected to each other; the input ends of the OR gate and the third NAND gate are both connected to eight counting output ends;

[0029] The output terminal of the OR gate is connected to the third input terminal of the positive deviation counting unit;

[0030] The output terminal of the third NAND gate is connected to the third input terminal of the negative deviation counting unit.

[0031] Furthermore, the R-2R network unit includes eight control input terminals, and the eight control input terminals are electrically connected to eight counting output terminals of the presettable up-down counter in a one-to-one correspondence.

[0032] At the same time, the present invention also provides an R-2R network automatic error elimination method for an ion source control circuit, which is special in that the R-2R network automatic error elimination circuit for an ion source control circuit is used, and includes the following steps:

[0033] S1, start the circuit and adjust the presettable up / down counter to the preset base value;

[0034] S2, the positive deviation discriminator obtains the error voltage and the positive threshold voltage, and the negative deviation discriminator obtains the error voltage and the negative threshold voltage;

[0035] S2, a positive deviation discriminator and a negative deviation discriminator respectively compare the received voltage signals;

[0036] If the absolute value of the error voltage is less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, the negative deviation signal output by the negative deviation discriminator is 0, the positive deviation signal output by the positive deviation discriminator is 0, the second input terminal of the positive deviation counting unit and the second input terminal of the negative deviation counting unit are both blocked, the clock enable signal cannot pass, the presettable up / down counter remains unchanged, and the target DC voltage output by the R-2R network unit remains unchanged;

[0037] If the error voltage is greater than the positive threshold voltage, the negative deviation signal output by the negative deviation discriminator is 0, the negative deviation counting unit is blocked, and the clock enable signal cannot pass; the positive deviation signal output by the positive deviation discriminator is 1, the counting control unit output signal is 1, the clock enable signal passes through the positive deviation counting unit, the first input end, the second input end and the third input end of the positive deviation counting unit are all turned on, the positive deviation counting unit outputs a cumulative subtraction signal, and transmits it to the presettable add-subtraction counter, the digital value of the presettable add-subtraction counter is reduced by 1, and each output end of the changed presettable add-subtraction counter controls the R-2R network unit to generate a DC voltage. After the DC voltage is loaded on the ion source control circuit, the ion source control circuit outputs the current error voltage, compares the current error voltage with the positive threshold voltage, until the absolute value of the error voltage is less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, and returns to step S2;

[0038] If the error voltage is less than the negative threshold voltage, the positive deviation signal output by the positive deviation discriminator is 0, the positive deviation counting unit is blocked, and the clock enable signal cannot pass; the negative deviation signal output by the negative deviation discriminator is 1, the counting control unit output signal is 1, the clock enable signal passes through the negative deviation counting unit, the first input terminal, the second input terminal and the third input terminal of the negative deviation counting unit are all turned on, the negative deviation counting unit outputs a cumulative signal, and transmits it to the presettable add-subtract counter, the digital value of the presettable add-subtract counter is increased by 1, and the output terminals of the changed presettable add-subtract counter control the R-2R network unit to generate a DC voltage. After the DC voltage is loaded on the ion source control circuit, the ion source control circuit outputs the current error voltage, compares the current error voltage with the negative threshold voltage, until the absolute value of the current error voltage is less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, and returns to step S2.

[0039] Further, in step S3, if the error voltage is greater than the positive threshold voltage, the digital value of the presettable up-down counter is adjusted to zero, and the absolute value of the error voltage is still not less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, the variable resistor value is increased, the presettable up-down counter is adjusted to the preset base value, and the process returns to step S2;

[0040] If the error voltage is less than the negative threshold voltage, the digital value of the presettable add-subtract counter is adjusted to increase to the preset maximum value. If the absolute value of the error voltage is still not less than the absolute value of the positive threshold voltage and the negative threshold voltage, the variable resistance value is increased, the presettable add-subtract counter is adjusted to the preset base value, and the process returns to step S2.

[0041] Beneficial effects of the present invention:

[0042] 1. The present invention adjusts the output voltage V through an automatic error elimination circuit 0 , the output voltage V 0 It acts on the ion source control circuit, adjusts the voltage and then adjusts the hot wire current IF, which saves the time of manual adjustment, prevents lagging adjustment, and also makes the operation of the neutron tube more stable.

[0043] 2. Both the positive deviation discriminator and the negative deviation discriminator contain positive feedback circuits to enhance the voltage discrimination capability of the deviation discrimination unit.

[0044] 3. The high-level narrow pulse of the clock enable signal output by the clock unit is compared with the square wave with a duty cycle close to 50%. If the output of the deviation discrimination unit flips, the deviation counting unit will not output multiple pulses continuously, thus ensuring the accuracy of the circuit.

[0045] 4. The automatic error elimination method of the present invention automatically eliminates the hysteresis error in the ion source control circuit by comparing the error voltage with the positive threshold voltage and the negative threshold voltage. Compared with manual adjustment, it has strong real-time performance and high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of an embodiment of an R-2R network automatic error elimination circuit for use in an ion source control circuit of the present invention;

[0047] Figure 2 A connection circuit diagram of a threshold voltage unit, a deviation identification unit, a deviation counting unit, and a clock unit in an embodiment of the present invention;

[0048] Figure 3 A connection circuit diagram of a presettable addition and subtraction counter and a counting control unit in an embodiment of the present invention;

[0049] Figure 4 It is a connection circuit diagram of an R-2R network unit in an embodiment of the present invention;

[0050] Figure 5 Schematic diagram of the principle of a 4-data-bit R-2R network in an embodiment of the present invention.

[0051] The reference numerals are as follows:

[0052] 1-positive deviation discriminator, 2-negative deviation discriminator, 3-positive deviation counting unit, 4-negative deviation counting unit, 5-clock unit, 6-four-bit presettable add-subtract counter, 7-OR gate, 8-third NAND gate, 9-R-2R network unit. DETAILED DESCRIPTION

[0053] See also Figure 1-Figure 4 This embodiment provides an R-2R network automatic error elimination circuit for an ion source control circuit, the automatic error elimination circuit includes a threshold voltage unit, a deviation discrimination unit, a deviation counting unit, a clock unit 5, a presettable addition and subtraction counter, a counting control unit and an R-2R network unit 9; wherein, Figure 2 b1, b2, b3, and b4 in Figure 3 b1, b2, b3, and b4 are connected accordingly; Figure 3 c1, c2, c3, c4, c5, c6, c7, c8 in are respectively Figure 4 The c1, c2, c3, c4, c5, c6, c7, and c8 in it are connected correspondingly.

[0054] The threshold voltage unit is configured to generate a positive threshold voltage and a negative threshold voltage; the threshold voltage unit includes a plurality of series-connected voltage-dividing resistors connected between a positive power supply and a negative power supply, and the plurality of series-connected voltage-dividing resistors are used to divide the voltage to obtain a positive threshold voltage and a negative threshold voltage; the positive power supply is connected to a first filter circuit, and the negative power supply is connected to a second filter circuit; the first filter circuit includes a capacitor C1, one end of the capacitor C1 is connected to the positive power supply, and the other end is connected to GND; the second filter circuit includes a capacitor C4, one end of the capacitor C4 is connected to the negative power supply, and the other end is connected to GND.

[0055] The deviation discriminator unit includes a positive deviation discriminator 1 and a negative deviation discriminator 2; the positive deviation discriminator 1 is configured to output a positive deviation signal when the error voltage is greater than the positive threshold voltage, and the positive deviation signal is high level valid; the positive deviation discriminator 1 includes a first amplifier and a first positive feedback circuit, wherein R34 and R35 amplify the signal through the resistance difference; the non-inverting input terminal of the first amplifier is used to load the error voltage, and the inverting input terminal of the first amplifier is used to load the positive threshold voltage; the first positive feedback circuit includes an output terminal and a non-inverting input terminal connected to the first amplifier. The positive deviation discriminator 1 is connected to the positive pole of the power supply, and R3 and C5 are used for power supply filtering; the negative deviation discriminator 2 is connected to the negative pole of the power supply, and R4 and C6 are used for power supply filtering; R30 and R31 are respectively connected to the output terminals of the positive deviation discriminator 1 and the negative deviation discriminator 2, and have a voltage stabilizing effect.

[0056] The negative deviation discriminator 2 is configured to output a negative deviation signal when the error voltage is less than the negative threshold voltage, and the negative deviation signal is valid at a high level; the negative deviation discriminator 2 includes a second amplifier and a second positive feedback circuit, wherein R32 and R33 amplify the signal through a resistance difference; the inverting input terminal of the second amplifier is used to load the error voltage, and the non-inverting input terminal of the second amplifier is used to load the negative threshold voltage; the second positive feedback circuit connects the output terminal and the non-inverting input terminal of the second amplifier.

[0057] The clock unit 5 is configured to generate a clock enable signal, which is valid at a high level. Preferably, the clock unit 5 is a self-excited multivibrator for outputting a high-level narrow pulse as the clock enable signal.

[0058] The deviation counting unit includes a positive deviation counting unit 3 and a negative deviation counting unit 4, which are respectively a first NAND gate and a second NAND gate; the positive deviation counting unit 3 is configured to respond to a positive deviation signal, a clock enable signal and a positive deviation counting enable signal, and output a cumulative signal, and the cumulative signal is valid at a low level; the negative deviation counting unit 4 is configured to respond to a negative deviation signal, a clock enable signal and a negative deviation counting enable signal, and output an accumulated signal, and the accumulated signal is valid at a low level.

[0059] The output end of the clock unit 5 is connected to the first input end of the positive deviation counting unit 3 and the first input end of the negative deviation counting unit 4 respectively; the second input end of the positive deviation counting unit 3 is connected to the output end of the positive deviation discriminator 1, and the output end of the positive deviation counting unit 3 is connected to an input end of a presettable add-subtract counter; the second input end of the negative deviation counting unit 4 is connected to the output end of the negative deviation discriminator 2, and the output end of the negative deviation counting unit 4 is connected to another input end of the presettable add-subtract counter; the two output ends of the presettable add-subtract counter are respectively connected to the input end of the counting control unit and the input end of the R-2R network unit 9; the two output ends of the counting control unit are respectively connected to the third input end of the positive deviation counting unit 3 and the third input end of the negative deviation counting unit 4.

[0060] The presettable add-subtract counter is configured to count up by one in response to the accumulation signal, and count down by one in response to the accumulation signal; specifically, the presettable add-subtract counter includes two four-bit presettable add-subtract counters 6 connected in series, forming an eight-bit binary counter with eight counting output terminals; the accumulation input terminal of the presettable add-subtract counter is electrically connected to the output terminal of the positive deviation counting unit 3; the accumulation input terminal of the presettable add-subtract counter is electrically connected to the output terminal of the negative deviation counting unit 4. A reset switch is connected to the presettable add-subtract counter.

[0061] The counting control unit is electrically connected to the output end of the presettable adding and subtracting counter; the counting control unit includes an OR gate 7 and a third NAND gate 8 which are connected to each other, and the input ends of the OR gate 7 and the third NAND gate 8 are both connected to eight counting output ends; the output end of the OR gate 7 is connected to the third input end of the positive deviation counting unit 3, and is used to output a positive deviation counting enable signal when the count of the presettable adding and subtracting counter is not zero; the output end of the third NAND gate 8 is connected to the third input end of the negative deviation counting unit 4, and is used to output a negative deviation counting enable signal when the count of the presettable adding and subtracting counter has not reached a maximum value, and the positive deviation counting enable signal and the negative deviation counting enable signal are valid at a high level.

[0062] The R-2R network unit 9 is configured to output a target DC voltage under the control of each output terminal of the presettable addition and subtraction counter; specifically, the R-2R network unit 9 includes eight control input terminals, and the eight control input terminals are electrically connected to the eight counting output terminals of the presettable addition and subtraction counter in a one-to-one correspondence; the output terminal of the R-2R network unit 9 is connected to a fixed terminal of the variable resistor, the other fixed terminal of the variable resistor is grounded, and the output terminal of the variable resistor outputs the target DC voltage.

[0063] Taking the output voltage Vo of the R-2R network automatic error elimination circuit used in the ion source control circuit as 127mV as an example, the principle of the error elimination circuit is specifically explained.

[0064] The basic principle is: the gas pressure control circuit in the ion source control circuit inputs an error voltage ΔV to the error elimination circuit of this embodiment, and after power-on or pressing the reset switch K, the output voltage Vo of the R-2R network unit 9 is reset to the base value, which is 127mV.

[0065] When |ΔV|<20mV, the up-down counter can be preset to not increase or decrease, and Vo remains unchanged.

[0066] When ΔV<-20mV, the up-down counter can be preset to add 1 every cycle, and Vo increases by 1mV. When it increases to 255mV, it will no longer increase.

[0067] When ΔV>20mV, the up-down counter can be preset to decrease by 1 after each cycle, and Vo decreases by 1mV. When it decreases to 0mV, it will no longer decrease.

[0068] Vo changes back and forth between 0 and 255 mV, but not in a cycle. By additionally adjusting the hot wire current IF of the gas pressure control circuit in the ion source control circuit based on Vo, ΔV is adjusted to |ΔV|<20 mV.

[0069] See also Figure 2In this embodiment, a positive threshold voltage of +20mV is constructed by a positive power supply, a series-connected voltage-dividing resistor R5 and a voltage-dividing resistor R6, and the positive threshold voltage is connected to the inverting input terminal of the positive deviation discriminator 1; a negative threshold voltage of -20mV is constructed by a negative power supply, a series-connected voltage-dividing resistor R7 and a voltage-dividing resistor R8, and the negative threshold voltage is connected to the non-inverting input terminal of the negative deviation discriminator 2.

[0070] The clock unit 5 is a self-excited multivibrator of model NE555, which outputs positive narrow pulses with a period of about 3.5 seconds, which are added to the positive deviation counting unit 3 and the negative deviation counting unit 4 as clock enable signals.

[0071] Two 4-bit presettable add-subtract counters 6 of model 40193 are connected in series to form an 8-bit binary add-subtract counter according to the user manual. U4 is the lower 4 bits, U5 is the upper 4 bits, D0-D6 is connected to VD, and D7 is connected to 0, that is, the input data value is 127. Due to the energy storage function of R9 and C7, the counter is automatically preset to 127 after the circuit is powered on; Q0-Q7 drives the 8-bit R-2R network, and the digital quantity D is converted into an analog voltage signal; the required DC voltage Vo is output by the variable resistor RP1.

[0072] The digital quantity D starts from the base value 127 and is increased or decreased by ΔV control as follows:

[0073] If |ΔV|<20mV, the negative deviation signal output by the negative deviation discriminator 2 is 0, the positive deviation signal output by the positive deviation discriminator 1 is 0, the two NAND gates of the positive deviation counting unit 3 and the negative deviation counting unit 4 are blocked, the clock cannot pass, and the outputs of the positive deviation counting unit 3 and the negative deviation counting unit 4 remain at a high level. The preset up / down counter does not increase or decrease, and the digital quantity D remains at 127.

[0074] When ΔV>+20mV, the positive deviation signal output by the positive deviation discriminator 1 is 1, and the negative deviation signal output by the negative deviation discriminator 2 is 0. The clock can pass through the first NAND gate of the positive deviation counting unit 3, but still cannot pass through the second NAND gate of the negative deviation counting unit 4. If the output of OR gate 7 is 1 (only when the digital quantity D=0, the output of OR gate 7 is 0), then the clock unit 5 passes through the first NAND gate of the positive deviation counting unit 3 and becomes a pull-down pulse. The CPD of the presettable add-subtract counter jumps up, and the presettable add-subtract counter decreases by 1. As long as ΔV>+20mV, the presettable add-subtract counter keeps decreasing until the digital quantity D=0, and the output of OR gate 7 is 0, blocking the first NAND gate of the positive deviation counting unit 3, and the digital quantity D remains 0; if the digital quantity D is 0, ΔV>+20mV still holds, then it is necessary to increase the variable resistor to increase the voltage adjustment range.

[0075] When ΔV<-20mV, the positive deviation signal output by the positive deviation discriminator 1 is 0, the first NAND gate of the positive deviation counting unit 3 is blocked, the negative deviation signal output by the negative deviation discriminator 2 is 1, and the second NAND gate of the negative deviation counting unit 4 receives the negative deviation signal. If the output of the third NAND gate 8 is 1 (only when the digital quantity D=255 and all eight bits are 1, the output of the third NAND gate 8 is 0), the second NAND gate of the negative deviation counting unit 4 is released, the clock passes, and is added to the CPU of the presettable add-subtract counter, which is also a pull-down pulse. The presettable add-subtract counter adds 1, jumps up again, and adds 1 again. As long as ΔV<-20mV, the count is added. When the digital quantity D=255 is added, the third NAND gate 8 outputs 0, blocking the second NAND gate of the negative deviation counting unit 4, and the digital quantity D remains 255; if the digital quantity D is 255, ΔV<-20mV still holds true, then it is necessary to increase the variable resistor to increase the voltage adjustment range.

[0076] The digital value D can only change between 0 and 255 and cannot cycle.

[0077] The digital quantity D can be increased by 127 or decreased by 127 based on the base value of 127, which is a large enough range to eliminate the hysteresis error under the automatic control mode.

[0078] The R-2R network unit 9 has a characteristic that the input resistance is 2R from each node to the left and right sides. Thus, according to the power superposition principle, the current contributed in the output resistance (2R adjacent to the high bit) when each data bit is 1 (i.e. Vo) can be calculated, and then the contribution of each data bit can be added up.

[0079] like Figure 5 As shown, taking four data bits as an example, the current contributed by each data bit output end of the R-2R network is shown in Table 1:

[0080] Table 1

[0081] Q0 Q1 Q2 Q3 Io 1 0 0 0 VD / 3R×1 / 2^4 0 1 0 0 VD / 3R×1 / 2^3 0 0 1 0 VD / 3R×1 / 2^2 0 0 0 1 VD / 3R×1 / 2

[0082] In the above table, VD is the voltage when the presettable up / down counter data output terminal (Q) is "high". For CMOS circuits, when the power supply voltage is VD, the voltage when Q is high ≈ VD. So the total current is:

[0083] Io=VD / 3R(Q0 / 2^4+1 / 2^3Q1+1 / 2^2Q2+1 / 2Q3)

[0084] =(VD / 2^8×3R)D

[0085] Vo=(VD / 384)D

[0086] The above formula shows that the total output voltage Vo of the R-2R network is only related to the number of binary digits, D value and VD, and has nothing to do with the resistance R. As a series, for an 8-bit R-2R network, when D=1, VD=15V, Vo=39mV; when D=127, Vo=4.961V.

[0087] The constant current source of the air pressure control circuit needs a voltage of 200 to 300 mV. Therefore, the output resistor "2R" of the R-2R network is made into a 9K resistor and a 1K multi-turn potentiometer in series. At this time, the output voltage of the potentiometer is up to 496 mV; corresponding to a change of 1 in the digital quantity D, the output voltage increment of the potentiometer is 496 / 127 = 3.9 mV.

Claims

1. An R-2R network automatic error elimination circuit used in an ion source control circuit, characterized in that: It includes a threshold voltage unit, a deviation identification unit, a clock unit (5), a deviation counting unit, a presettable addition and subtraction counter, a counting control unit, an R-2R network unit (9) and a variable resistor; The threshold voltage unit is used to generate a positive threshold voltage and a negative threshold voltage; the deviation discrimination unit comprises a positive deviation discriminator (1) and a negative deviation discriminator (2); The positive deviation discriminator (1) is used to output a positive deviation signal when the error voltage is greater than the positive threshold voltage; the negative deviation discriminator (2) is used to output a negative deviation signal when the error voltage is less than the negative threshold voltage; the positive threshold voltage output end and the negative threshold voltage output end of the threshold voltage unit are respectively connected to an input end of the positive deviation discriminator (1) and an input end of the negative deviation discriminator (2); The clock unit (5) is used to generate a clock enable signal; The deviation counting unit is used to generate a cumulative subtraction signal and a cumulative addition signal according to the positive deviation signal and the negative deviation signal output, and the deviation counting unit comprises a positive deviation counting unit (3) and a negative deviation counting unit (4); The output end of the clock unit (5) is respectively connected to the first input end of the positive deviation counting unit (3) and the first input end of the negative deviation counting unit (4); the second input end of the positive deviation counting unit (3) is connected to the output end of the positive deviation discriminator (1), and the output end of the positive deviation counting unit (3) is connected to an input end of a presettable add-subtract counter; the second input end of the negative deviation counting unit (4) is connected to the output end of the negative deviation discriminator (2), and the output end of the negative deviation counting unit (4) is connected to another input end of the presettable add-subtract counter; the two output ends of the presettable add-subtract counter are respectively connected to the input end of the counting control unit and the input end of the R-2R network unit (9); the two output ends of the counting control unit are respectively connected to the third input end of the positive deviation counting unit (3) and the third input end of the negative deviation counting unit (4); The presettable up / down counter is used to count up by one in response to an accumulation signal, or to count down by one in response to an accumulation signal; The counting control unit is used to output a positive deviation counting enable signal or a negative deviation counting enable signal; The output end of the R-2R network unit (9) is connected to a fixed end of the variable resistor, the other fixed end of the variable resistor is grounded, and the output end of the variable resistor outputs a target DC voltage.

2. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 1, characterized in that: The threshold voltage unit includes a plurality of voltage-dividing resistors connected in series between a positive power supply and a negative power supply; the plurality of voltage-dividing resistors connected in series are used for voltage division to obtain a positive threshold voltage and a negative threshold voltage.

3. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 2, characterized in that: The positive deviation discriminator (1) comprises a first amplifier and a first positive feedback circuit; The non-inverting input terminal of the first amplifier is used to load the error voltage, and the inverting input terminal of the first amplifier is used to load the positive threshold voltage; The first positive feedback circuit is connected between the output terminal and the non-phase input terminal of the first amplifier; The output end of the first amplifier is connected to the second input end of the positive deviation counting unit (3); The negative deviation discriminator (2) comprises a second amplifier and a second positive feedback circuit; The inverting input terminal of the second amplifier is used to load the error voltage, and the non-inverting input terminal of the second amplifier is used to load the negative threshold voltage; The second positive feedback circuit is connected between the output terminal and the non-phase input terminal of the second amplifier; The output end of the second amplifier is connected to the second input end of the negative deviation counting unit (4).

4. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 3, characterized in that: The positive deviation signal, negative deviation signal, clock enable signal, positive deviation count enable signal and negative deviation count enable signal are high level valid; the cumulative reduction signal and cumulative addition signal are low level valid; The positive deviation counting unit (3) is a first NAND gate, and the negative deviation counting unit (4) is a second NAND gate.

5. The R-2R network automatic error elimination circuit for use in an ion source control circuit according to any one of claims 1 to 4, characterized in that: The clock unit (5) is a self-excited multivibrator, used for outputting a high-level narrow pulse as a clock enable signal.

6. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 5, characterized in that: The presettable up / down counter is an eight-bit binary counter having eight counting output terminals; The presettable add-subtract counter comprises two four-bit presettable add-subtract counters (6) connected in series; the cumulative input end of the presettable add-subtract counter is electrically connected to the output end of the positive deviation counting unit (3); and the cumulative input end of the presettable add-subtract counter is electrically connected to the output end of the negative deviation counting unit (4).

7. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 6, characterized in that: The counting control unit comprises an OR gate (7) and a third NAND gate (8) connected to each other; input ends of the OR gate (7) and the third NAND gate (8) are both connected to eight counting output ends; The output end of the OR gate (7) is connected to the third input end of the positive deviation counting unit (3); The output end of the third NAND gate (8) is connected to the third input end of the negative deviation counting unit (4).

8. The R-2R network automatic error elimination circuit used in the ion source control circuit according to claim 7, characterized in that: The R-2R network unit (9) comprises eight control input terminals, which are respectively connected to eight counting output terminals of a presettable up / down counter in a one-to-one correspondence.

9. A method for automatically eliminating errors in an R-2R network in an ion source control circuit, characterized in that: The R-2R network automatic error elimination circuit used in an ion source control circuit according to any one of claims 1 to 8 comprises the following steps: S1, start the circuit and adjust the presettable up / down counter to the preset base value; S2, the positive deviation discriminator (1) obtains the error voltage and the positive threshold voltage, and the negative deviation discriminator (2) obtains the error voltage and the negative threshold voltage; S3, the positive deviation discriminator (1) and the negative deviation discriminator (2) respectively compare the received voltage signals; If the absolute value of the error voltage is smaller than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, the negative deviation signal output by the negative deviation discriminator (2) is 0, the positive deviation signal output by the positive deviation discriminator (1) is 0, the second input end of the positive deviation counting unit (3) and the second input end of the negative deviation counting unit (4) are both blocked, the clock enable signal cannot pass, the presettable up / down counter remains unchanged, and the target DC voltage output by the R-2R network unit (9) remains unchanged; If the error voltage is greater than the positive threshold voltage, the negative deviation signal output by the negative deviation discriminator (2) is 0, the negative deviation counting unit (4) is blocked, and the clock enable signal cannot pass; the positive deviation signal output by the positive deviation discriminator (1) is 1, the counting control unit output signal is 1, the clock enable signal passes through the positive deviation counting unit (3), the positive deviation counting unit (3) outputs a cumulative subtraction signal and transmits it to the presettable add-subtraction counter, the presettable add-subtraction counter digital quantity is reduced by 1, and each output end of the presettable add-subtraction counter after the change controls the R-2R network unit (9) to generate a DC voltage, and after the DC voltage is loaded on the ion source control circuit, the ion source control circuit outputs the current error voltage, compares the current error voltage with the positive threshold voltage, until the absolute value of the error voltage is less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, and returns to step S2; If the error voltage is less than the negative threshold voltage, the positive deviation signal output by the positive deviation discriminator (1) is 0, the positive deviation counting unit (3) is blocked, and the clock enable signal cannot pass; the negative deviation signal output by the negative deviation discriminator (2) is 1, the counting control unit output signal is 1, the clock enable signal passes through the negative deviation counting unit (4), the negative deviation counting unit (4) outputs an accumulation signal and transmits it to the presettable add-subtract counter, the presettable add-subtract counter digital quantity is increased by 1, and each output end of the presettable add-subtract counter after the change controls the R-2R network unit (9) to generate a DC voltage, and after the DC voltage is loaded on the ion source control circuit, the ion source control circuit outputs the current error voltage, compares the current error voltage with the negative threshold voltage, until the absolute value of the current error voltage is less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, and returns to step S2.

10. The R-2R network automatic error elimination method for an ion source control circuit according to claim 9, characterized in that: In step S3, if the error voltage is greater than the positive threshold voltage, the digital value of the presettable up / down counter is adjusted to zero, and the absolute value of the error voltage is still not less than the absolute values ​​of the positive threshold voltage and the negative threshold voltage, the variable resistor value is increased, the presettable up / down counter is adjusted to the preset base value, and the process returns to step S2; If the error voltage is less than the negative threshold voltage, the digital value of the presettable add-subtract counter is adjusted to increase to the preset maximum value. If the absolute value of the error voltage is still not less than the absolute value of the positive threshold voltage and the negative threshold voltage, the variable resistance value is increased, the presettable add-subtract counter is adjusted to the preset base value, and the process returns to step S2.

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