A power-down protection circuit for a flash chip

Abstract

The application discloses a power-off protection circuit of a flash chip, and relates to the technical field of electronic circuits, comprising: a main power supply control module, which is used for providing a main power supply and a first bias current and controlling power transmission; a bias current generation module, which is used for copying the first bias current; a voltage sampling module, which is used for sampling the voltage of the main power supply; a voltage comparison module, which is used for power-off judgment and controlling a logic delay control module to delay output of a level signal; a signal self-locking module, which is used for self-locking control of power supply of a standby power supply control module; and a reset module, which is used for controlling the signal self-locking module to reset. The power-off protection circuit of the flash chip samples the voltage of power provided by the main power supply control module and judges power-off, so as to avoid repeated switching control of the power supply due to power voltage power-off fluctuation, and to adopt the logic delay control module to delay and keep the standby power supply control module working.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically a power-down protection circuit for a flash chip. Background Technology

[0002] Flash chips are a type of memory chip that allows data to be modified through specific programs. Currently, there are two main types of flash chips: NOR flash and NAND flash. Both are non-volatile flash memory technologies, characterized by large capacity and fast read / write speeds. Although existing flash chips possess electronically erasable programmable (EEPROM) capabilities, ensuring data is not lost due to power outages, this also results in a lack of related power-off protection functions. When power is quickly restored after a power outage, the flash chip can still malfunction, leading to error timing. Furthermore, it may fail to function properly after a complete power failure, reducing its efficiency. Therefore, improvements are needed. Summary of the Invention

[0003] This invention provides a power-down protection circuit for a flash chip to solve the problems mentioned in the background art.

[0004] According to an embodiment of the present invention, a power-down protection circuit for a flash chip is provided. The power-down protection circuit for the flash chip includes: a main power control module, a charging and discharging module, a bias current generation module, a voltage sampling module, a voltage comparison module, a logic delay control module, a flash chip module, a signal self-locking module, a backup power control module, and a reset module.

[0005] The main power control module is used to provide main power and first bias current, and to receive signals from the logic delay control module and control the transmission of main power.

[0006] The bias current generation module is connected to the main power control module, the voltage comparison module and the logic delay control module, and is used to copy the first bias current and provide a second bias current to the voltage comparison module and the logic delay control module.

[0007] The voltage sampling module is connected to the main power control module and is used to sample the voltage of the main power supply provided by the main power control module and output a voltage sampling signal.

[0008] The voltage comparison module is connected to the power sampling module and is used to receive the voltage sampling signal and the second bias current and perform power-down judgment through the voltage comparison circuit, and to output a power-down signal.

[0009] The logic delay control module, connected to the voltage sampling module and the voltage comparison module, is used to receive the power-down signal and the second bias current, and output high-level and low-level signals through a delay trigger circuit.

[0010] The flash chip module is connected to the main power control module and is used to receive the high-level signal and low-level signal through the flash circuit to determine the power failure status of the main power control module and output a reset signal.

[0011] The reset module is connected to the flash chip module and is used to transmit the reset signal through a transistor circuit.

[0012] The signal self-locking module is connected to the logic delay control module and the reset module. It is used to perform high-level self-locking control on the high-level signal output by the logic delay control module through the signal self-locking circuit, and to receive the reset signal transmitted by the reset module and stop the signal self-locking.

[0013] The backup power control module is connected to the flash chip module and the signal self-locking module, and is used to provide backup power, receive signals output by the signal self-locking module, and control the transmission of backup power.

[0014] The charging and discharging module is connected to the flash chip module, the backup power control module, and the main power control module, and is used to store the power provided by the backup power control module and the main power control module and to provide brief power supply control when the power is switched.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The power-down protection circuit of the flash chip of the present invention uses a bias current generation module, a voltage sampling module, and a voltage comparison module to sample the voltage of the power supplied by the main power control module and determine the power failure, thereby improving the detection accuracy of the input voltage. At the same time, the logic delay control module performs delay signal holding control to avoid repeated power switching control due to power voltage fluctuations. In conjunction with the charging and discharging module, it avoids the probability of flash chip errors during short power switching, thereby improving the safety of the flash chip. In the event of a power failure, it will seamlessly control the backup power control module to perform self-locking power supply. After the power supply is restored, the main power control module will be restored to supply power to the flash chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic block diagram of a power-down protection circuit for a flash chip provided as an example of the present invention;

[0018] Figure 2 A circuit diagram of a power-down protection circuit for a flash chip provided as an example of the present invention;

[0019] Figure 3 The connection circuit diagram of the signal self-locking module provided for an example of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1, please refer to Figure 1 A power-down protection circuit for a flash chip includes: a main power control module 1, a charging and discharging module 2, a bias current generation module 3, a voltage sampling module 4, a voltage comparison module 5, a logic delay control module 6, a flash chip module 7, a signal self-locking module 8, a backup power control module 9, and a reset module 10.

[0022] Specifically, the main power control module 1 is used to provide main power and first bias current, and to receive signals from the logic delay control module 6 and control the transmission of main power.

[0023] The bias current generation module 3 is connected to the main power control module 1, the voltage comparison module 5 and the logic delay control module 6, and is used to copy the first bias current and provide a second bias current to the voltage comparison module 5 and the logic delay control module 6.

[0024] Voltage sampling module 4 is connected to the main power control module 1 and is used to sample the voltage of the main power supply provided by the main power control module 1 and output a voltage sampling signal.

[0025] Voltage comparison module 5 is connected to the power sampling module and is used to receive the voltage sampling signal and the second bias current and perform power-down judgment through the voltage comparison circuit, and is used to output a power-down signal.

[0026] The logic delay control module 6, connected to the voltage sampling module 4 and the voltage comparison module 5, is used to receive the power-down signal and the second bias current, and output high-level and low-level signals through a delay trigger circuit.

[0027] The flash chip module 7 is connected to the main power control module 1 and is used to receive the high-level signal and low-level signal through the flash circuit to determine the power failure status of the main power control module 1 and to output a reset signal.

[0028] The reset module 10 is connected to the flash chip module 7 and is used to transmit the reset signal through a transistor circuit.

[0029] The signal self-locking module 8 is connected to the logic delay control module 6 and the reset module 10. It is used to perform high-level self-locking control on the high-level signal output by the logic delay control module 6 through the signal self-locking circuit, and to receive the reset signal transmitted by the reset module 10 and stop the signal self-locking.

[0030] The backup power control module 9 is connected to the flash chip module 7 and the signal self-locking module 8, and is used to provide backup power, receive the signal output by the signal self-locking module 8 and control the transmission of backup power.

[0031] The charging and discharging module 2 is connected to the flash chip module 7, the backup power control module 9, and the main power control module 1. It is used to store the power provided by the backup power control module 9 and the main power control module 1 and to provide brief power supply control when the power is switched.

[0032] In a specific embodiment, the main power control module 1 can employ a main power supply circuit and a discharge control circuit, with the discharge control module transmitting main power to the flash chip module 7; the charge / discharge module 2 can employ a polarized capacitor circuit for short-term charge / discharge control; the bias current generation module 3 can employ a current mirror circuit for copying and transmitting bias current; the voltage sampling module 4 can employ a resistor voltage divider circuit to sample the power of the main power control module 1; and the voltage comparison module 5 can employ a voltage comparison circuit composed of five sets of transistors, used to compare the signal sampled by the voltage sampling module 4 with the set voltage. The system compares the signal against a predetermined power threshold. The logic delay control module 6 can use a delay trigger circuit to delay the output signal. The flash chip module 7 uses a flash circuit for data storage, which will not be elaborated here. The signal self-locking module 8 can use a signal self-locking circuit to self-lock the input level signal. The backup power control module 9 can use a backup power circuit and a discharge control circuit, with the discharge control circuit controlling the transmission of backup power. The reset module 10 can use a transistor control circuit to transmit the reset signal output by the flash chip module 7 and perform reset control on the signal self-locking module 8.

[0033] Example 2, based on Example 1, please refer to... Figure 2 and Figure 3 The main power control module 1 includes a main power supply device, a sixth resistor R6, a first control transistor M1, a first switching transistor VT1, a first power supply VCC1, a fourth resistor R4, and a first diode D1; the flash chip module 7 includes a flash chip.

[0034] Specifically, the first end of the main power supply device is connected to the drain of the first control transistor M1 and the gate of the first control transistor M1 and the collector of the first switching transistor VT1 through the sixth resistor R6. The base of the first switching transistor VT1 is connected to the cathode of the first diode D1 and the first power supply VCC1 through the fourth resistor R4. The anode of the first diode D1 is connected to the logic delay control module 6. The emitter of the first switching transistor VT1 and the ground terminal of the flash chip are both grounded. The source of the first control transistor M1 is connected to the power supply terminal of the flash chip.

[0035] In a specific embodiment, the first control transistor M1 can be an N-channel enhancement-mode MOSFET, controlled by the sixth resistor R6 and the first switch transistor VT1; the first switch transistor VT1 can be an NPN transistor, controlled by the level signal output by the logic delay control module 6; the flash chip is used as a memory chip, and the specific model is not limited.

[0036] Furthermore, the bias current generating module 3 includes a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, and a tenth power transistor Q10;

[0037] Specifically, the drain of the first power transistor Q1 is connected to the second terminal of the main power supply device, the gate of the first power transistor Q1 is connected to the gate of the second power transistor Q2, the drain of the second power transistor Q2 is connected to the drain of the third power transistor Q3, the gate of the third power transistor Q3, the voltage comparison module 5, and the gate of the tenth power transistor Q10, the source of the third power transistor Q3 and the source of the tenth power transistor Q10 are connected to the first terminal of the main power supply device, the drain of the tenth power transistor Q10 is connected to the logic delay control module 6, and the sources of the first power transistor Q1 and the second power transistor Q2 are both grounded.

[0038] In a specific embodiment, the first power transistor Q1 and the second power transistor Q2 form a current mirror circuit, and the third power transistor Q3 and the tenth power transistor Q10 form a current mirror circuit. Both are used to copy and transmit the first bias current to improve the signal processing accuracy. The first power transistor Q1 and the second power transistor Q2 can be depletion-type P-channel MOSFETs, and the third power transistor Q3 and the tenth power transistor Q10 can be depletion-type N-channel MOSFETs.

[0039] Furthermore, the voltage sampling module 4 includes a first resistor R1, a second resistor R2, a third resistor R3, and a ninth power transistor Q9;

[0040] Specifically, the first end of the first resistor R1 is connected to the first end of the main power supply device, the second end of the first resistor R1 is connected to one end of the third resistor R3 and the drain of the ninth power transistor Q9 through the second resistor R2, the other end of the third resistor R3 and the source of the ninth power transistor Q9 are both grounded, and the gate of the ninth power transistor Q9 is connected to the logic delay control module 6.

[0041] In a specific embodiment, the first resistor R1, the second resistor R2, and the third resistor R3 form a resistor voltage divider circuit to sample the voltage of the electrical energy output by the main power supply device; the ninth power transistor Q9 can be a depletion-type P-channel MOS transistor.

[0042] Furthermore, the voltage comparison module 5 includes a fourth power transistor Q4, a fifth power transistor Q5, a sixth power transistor Q6, a seventh power transistor Q7, an eighth power transistor Q8, and a power threshold.

[0043] Specifically, the gate and source of the fourth power transistor Q4 are respectively connected to the gate of the third power transistor Q3 and the first terminal of the main power supply device. The drain of the fourth power transistor Q4 is connected to the source of the fifth power transistor Q5 and the source of the eighth power transistor Q8. The drain and gate of the sixth power transistor Q6 are both connected to the drain of the fifth power transistor Q5 and the gate of the seventh power transistor Q7. The gate of the fifth power transistor Q5 is connected to the charge threshold. The drain of the seventh power transistor Q7 is connected to the drain of the eighth power transistor Q8. The gate of the eighth power transistor Q8 is connected to the second terminal of the first resistor R1. The sources of the sixth power transistor Q6 and the seventh power transistor Q7 are both grounded.

[0044] In a specific embodiment, the fourth power transistor Q4 can be a depletion-type N-channel MOSFET, which, together with the third power transistor Q3, forms a current mirror circuit to transmit the first bias current; the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 form a voltage comparator circuit, wherein the fifth power transistor Q5 and the eighth power transistor Q8 can both be depletion-type N-channel MOSFETs, and the sixth power transistor Q6 and the seventh power transistor Q7 can be depletion-type P-channel MOSFETs.

[0045] Furthermore, the logic delay control module 6 includes an eleventh power transistor Q11 and a delay trigger U1;

[0046] Specifically, the gate of the eleventh power transistor Q11 is connected to the drain of the seventh power transistor Q7, the drain of the eleventh power transistor Q11 is connected to the input of the delay trigger U1 and the drain of the tenth power transistor Q10, the source of the eleventh power transistor Q11 is grounded, and the output of the delay trigger U1 is connected to the first IO terminal of the flash chip, the anode of the first diode D1 and the gate of the ninth power transistor Q9.

[0047] In a specific embodiment, the eleventh power transistor Q11 can be a depletion-type P-channel enhancement-type MOS transistor; the delay trigger U1 can be a Schmitt trigger for delay trigger control.

[0048] Furthermore, the charging and discharging module 2 includes a fifth resistor R5 and a first capacitor C1;

[0049] Specifically, the first end of the fifth resistor R5 is connected to the source of the first power transistor Q1 and the power supply terminal of the flash chip, and the second end of the fifth resistor R5 is connected to the ground terminal through the first capacitor C1.

[0050] In a specific embodiment, the first capacitor C1 is used for short-term power supply during power switching, and the fifth resistor R5 is used for voltage division control.

[0051] Furthermore, the backup power control module 9 includes a backup power device, a second switching transistor VT2, a second control transistor M2, and a second diode D2;

[0052] Specifically, the backup power supply is connected to the collector of the second switching transistor VT2 and the drain of the second control transistor M2. The emitter of the second switching transistor VT2 and the gate of the second control transistor M2 are connected to the signal self-locking module 8. The source of the second power transistor Q2 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the power supply terminal of the flash chip. The base of the second switching transistor VT2 is connected to the base of the first switching transistor VT1.

[0053] In a specific embodiment, the second control transistor M2 is an N-channel enhancement-mode MOS transistor used to provide power to the flash chip; the second switch transistor VT2 is an NPN transistor used to control the operation of the signal self-locking module 8.

[0054] Furthermore, the signal self-locking module 8 includes a fourth diode D4, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a third diode D3, a fourth switch VT4, and a fifth switch VT5.

[0055] Specifically, the anode of the fourth diode D4 is connected to the emitter of the second switching transistor VT2. One end of the twelfth resistor R12 and the emitter of the fourth switching transistor VT4 are both connected to the backup power supply device and the reset module 10. The cathode of the fourth diode D4 is connected to one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, and is connected to ground through the fifteenth resistor R15. The other end of the fourteenth resistor R14 is connected to the base of the fifth switching transistor VT5. The collector of the fifth switching transistor VT5 is connected to the other end of the twelfth resistor R12, and is connected to the base of the fourth switching transistor VT4 through the tenth resistor R10. The collector of the fourth switching transistor VT4 is connected to the other end of the thirteenth resistor R13 and the anode of the third diode D3, and is connected to one end of the ninth resistor R9, the emitter of the fifth switching transistor VT5, and ground through the eleventh resistor R11. The cathode of the third diode D3 is connected to the other end of the ninth resistor R9 and the gate of the second control transistor M2.

[0056] In a specific embodiment, the fourth switch can be a PNP transistor, and the fifth switch VT5 can be an NPN transistor, forming a transistor self-locking circuit.

[0057] Furthermore, the reset module 10 includes a seventh resistor R7, an eighth resistor R8, and a third switch VT3;

[0058] Specifically, one end of the seventh resistor R7 is connected to the second IO terminal of the flash chip and connected to the ground terminal through the eighth resistor R8. The other end of the seventh resistor R7 is connected to the base of the third switch VT3. The emitter of the third switch VT3 is connected to the ground terminal, and the collector of the third switch VT3 is connected to the emitter of the fourth switch VT4.

[0059] In a specific embodiment, the third switch can be an NPN transistor, used to reset the fourth switch VT4 so as to stop the self-locking control of the fourth switch VT4 and the fifth switch VT5.

[0060] This invention discloses a power-down protection circuit for a flash chip. A main power supply and a first bias current are provided by a main power supply unit. A current mirror circuit composed of first power transistors Q1, second power transistors Q2, third power transistors Q3, fourth power transistors Q4, and tenth power transistors Q10 replicates the input first bias current and provides a second bias current to a voltage comparison module and a logic delay control module 6. At this time, the power supply is normal. A sixth resistor R6 triggers the first control transistor M1 to conduct, enabling the main power supply unit to provide power to the flash chip. The first resistor R1, second resistor R2, and third resistor R3 detect the power input to the flash chip from the main power supply unit and transmit it to the eighth power transistor Q8. Power-down detection, i.e., undervoltage detection, is performed by combining the power threshold through the fifth power transistor Q5, sixth power transistor Q6, seventh power transistor Q7, eighth power transistor Q8, and eleventh power transistor Q11. When the power output from the main power supply is lower than the turn-on power of the first control transistor M1, the first control transistor M1 will be turned off, and the main power supply will be unable to supply power to the flash chip. When a power failure is detected, the delay trigger U1 outputs a high-level signal after a delay, triggering the first switch transistor VT1 and the second switch transistor VT2 to turn on, causing the fourth switch transistor VT4 and the fifth switch transistor VT5 to self-lock and control the second power transistor Q2 to turn on. At this time, the backup power supply is connected to provide power to the flash chip. During the switching period, the first capacitor C1 discharges to ensure seamless power supply to the flash chip. When the main power supply returns to normal, the delay trigger U1 will output a low level, the first switch transistor VT1 will turn on, and the flash outputs a reset signal to control the third switch transistor VT3 to turn on and the fourth switch transistor VT4 to turn off, causing the second power transistor Q2 to turn off, and the backup power supply to stop supplying power.

[0061] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0062] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A power-off protection circuit of a flash chip, characterized in that, the power-off protection circuit of the flash chip comprises a main power supply control module, a charge-discharge module, a bias current generation module, a voltage sampling module, a voltage comparison module, a logic delay control module, a flash chip module, a signal self-locking module, a backup power supply control module, and a reset module; the main power supply control module is configured to provide a main power supply and a first bias current, and to receive a signal from the logic delay control module and control the main power supply transmission; the bias current generation module is connected with the main power supply control module, the voltage comparison module, and the logic delay control module, and is configured to copy the first bias current and provide a second bias current for the voltage comparison module and the logic delay control module; the voltage sampling module is connected with the main power supply control module, and is configured to sample the voltage of the main power supply provided by the main power supply control module and output a voltage sampling signal; the voltage comparison module is connected with the voltage sampling module, and is configured to receive the voltage sampling signal and the second bias current, and perform power-off judgment through a voltage comparison circuit, and output a power-off signal; the logic delay control module is connected with the voltage sampling module and the voltage comparison module, and is configured to receive the power-off signal and the second bias current, and output a high-level signal and a low-level signal through a delay trigger circuit, the flash chip module is connected with the main power supply control module, and is configured to receive the high-level signal and the low-level signal through a flash circuit, judge the power-off condition of the main power supply control module, and output a reset signal; the reset module is connected with the flash chip module, and is configured to transmit the reset signal through a transistor circuit; the signal self-locking module is connected with the logic delay control module and the reset module, and is configured to perform high-level self-locking control on the high-level signal output by the logic delay control module through a signal self-locking circuit, receive the reset signal transmitted by the reset module, and stop the signal self-locking; the backup power supply control module is connected with the flash chip module and the signal self-locking module, and is configured to provide a backup power supply, receive a signal output by the signal self-locking module, and control the backup power supply transmission; the charge-discharge module is connected with the flash chip module, the backup power supply control module, and the main power supply control module, and is configured to store the power supply provided by the backup power supply control module and the main power supply control module, and perform short power supply control when the power supply is switched.

2. The power-down protection circuit for a flash chip of claim 1, wherein, the main power supply control module comprises a main power supply device, a sixth resistor, a first control tube, a first switch tube, a first power supply, a fourth resistor, and a first diode; and the flash chip module comprises a flash chip. The first end of the main power supply device is connected with the drain of the first control tube and the gate of the first control tube and the collector of the first switch tube through the sixth resistor, the base of the first switch tube is connected with the cathode of the first diode and the first power supply through the fourth resistor, the anode of the first diode is connected with the logic delay control module, the emitter of the first switch tube and the ground terminal of the flash chip are grounded, and the source of the first control tube is connected with the power terminal of the flash chip.

3. The power-down protection circuit for a flash chip of claim 2, wherein, The bias current generation module comprises a first power tube, a second power tube, a third power tube and a tenth power tube. The drain of the first power tube is connected with the second end of the main power supply device, the gate of the first power tube is connected with the gate of the second power tube, the drain of the second power tube is connected with the drain of the third power tube, the gate of the third power tube, the voltage comparison module and the gate of the tenth power tube, the source of the third power tube and the source of the tenth power tube are connected with the first end of the main power supply device, the drain of the tenth power tube is connected with the logic delay control module, and the source of the first power tube and the source of the second power tube are grounded.

4. The power-down protection circuit for a flash chip of claim 3, wherein, The voltage sampling module comprises a first resistor, a second resistor, a third resistor and a ninth power tube. The first end of the first resistor is connected with the first end of the main power supply device, the second end of the first resistor is connected with one end of the third resistor and the drain of the ninth power tube through the second resistor, the other end of the third resistor and the source of the ninth power tube are grounded, and the gate of the ninth power tube is connected with the logic delay control module.

5. The power-down protection circuit for a flash chip of claim 4, wherein, The voltage comparison module comprises a fourth power tube, a fifth power tube, a sixth power tube, a seventh power tube, an eighth power tube and an electric quantity threshold value. The gate and source of the fourth power tube are connected with the gate of the third power tube and the first end of the main power supply device respectively, the drain of the fourth power tube is connected with the source of the fifth power tube and the source of the eighth power tube, the drain and gate of the sixth power tube are connected with the drain of the fifth power tube and the gate of the seventh power tube, the gate of the fifth power tube is connected with the electric quantity threshold value, the drain of the seventh power tube is connected with the drain of the eighth power tube, the gate of the eighth power tube is connected with the second end of the first resistor, and the source of the sixth power tube and the source of the seventh power tube are grounded.

6. The power-down protection circuit for a flash chip of claim 5, wherein, The logic delay control module comprises an eleventh power tube and a delay flip-flop. The gate of the eleventh power tube is connected with the drain of the seventh power tube, the drain of the eleventh power tube is connected with the input end of the delay flip-flop and the drain of the tenth power tube, the source of the eleventh power tube is grounded, and the output end of the delay flip-flop is connected with the first IO terminal of the flash chip, the anode of the first diode and the gate of the ninth power tube.

7. The power-down protection circuit for a flash chip of claim 3, wherein, The charge and discharge module comprises a fifth resistor and a first capacitor. The first end of the fifth resistor is connected with the source of the first power tube and the power terminal of the flash chip, and the second end of the fifth resistor is connected with the ground terminal through the first capacitor.

8. The power-down protection circuit for a flash chip of claim 7, wherein, The standby power supply control module comprises a standby power supply device, a second switch tube, a second control tube and a second diode. The standby power supply device is connected with the collector of the second switch tube and the drain of the second control tube, the emitter of the second switch tube and the gate of the second control tube are connected with the signal self-locking module, the source of the second power tube is connected with the anode of the second diode, the cathode of the second diode is connected with the power supply end of the flash chip, and the base of the second switch tube is connected with the base of the first switch tube.

9. The power-down protection circuit for a flash chip of claim 8, wherein, The signal self-locking module comprises a fourth diode, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third diode, a fourth switch tube and a fifth switch tube. The anode of the fourth diode is connected with the emitter of the second switch tube, one end of the twelfth resistor and the emitter of the fourth switch tube are connected with the standby power supply device and the reset module, the cathode of the fourth diode is connected with one end of the thirteenth resistor and one end of the fourteenth resistor and connected with the ground end through the fifteenth resistor, the other end of the fourteenth resistor is connected with the base of the fifth switch tube, the collector of the fifth switch tube is connected with the other end of the twelfth resistor and connected with the base of the fourth switch tube through the tenth resistor, the collector of the fourth switch tube is connected with the other end of the thirteenth resistor and the anode of the third diode and connected with one end of the ninth resistor, the emitter of the fifth switch tube and the ground end through the eleventh resistor, and the cathode of the third diode is connected with the other end of the ninth resistor and the gate of the second control tube.

10. The power-down protection circuit for a flash chip of claim 9, wherein, The reset module comprises a seventh resistor, an eighth resistor and a third switch tube. One end of the seventh resistor is connected with the second IO end of the flash chip and connected with the ground end through the eighth resistor, the other end of the seventh resistor is connected with the base of the third switch tube, the emitter of the third switch tube is connected with the ground end, and the collector of the third switch tube is connected with the emitter of the fourth switch tube.

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