Device, method, electronic device and medium for testing BMC serial port bandwidth

Abstract

The present invention provides an apparatus, method, electronic device, and medium for testing the bandwidth of a BMC serial port. The apparatus includes: an FPGA board and a terminal device; the terminal device is configured to send a test bit stream for testing the BMC serial port to the FPGA board; the FPGA board is configured to obtain a master control CPU core and multiple test CPU cores after receiving the test bit stream; the terminal device is further configured to set test configuration information and send it to the master control CPU core; the master control CPU core is configured to parse the test configuration information to determine a test task and target test CPU cores for executing the test task; each target test CPU core is configured to control its corresponding device under test to execute the test task according to the test task to obtain a test result; the master control CPU core is configured to receive the test results of each target test CPU core and send them to the terminal device; and the terminal device is configured to display the test results based on the correspondence between the device under test and the test result. The apparatus is designed to accurately test the performance limits of multiple BMC serial ports operating simultaneously.

Description

Technical Field

[0001] The present invention relates to the technical field of BMC serial port bandwidth testing, and in particular to a device, method, electronic equipment and medium for testing the bandwidth of a BMC serial port. Background Art

[0002] The server's BMC chip has multiple serial ports (typically 12), which connect to the server. Multiple serial ports share system resources, and their simultaneous operation can affect each other's communication capabilities. Therefore, determining the serial port performance of the BMC chip is crucial for designing a reliable BMC system for servers.

[0003] Currently, testing the performance of BMC serial ports typically involves using a computer with a serial port card. This method is relatively reliable for testing the bandwidth of a single BMC serial port. However, when testing the performance of multiple BMC serial ports operating simultaneously, due to the inherent limitations of the test equipment, this method can hog system resources, preventing the test equipment from measuring the maximum performance of multiple BMCs operating simultaneously. This results in inaccurate test results. Summary of the Invention

[0004] In view of this, the present invention provides a device, method, electronic device and medium for testing the bandwidth of a BMC serial port, aiming to accurately test the performance limit of multiple BMC serial ports working simultaneously.

[0005] In a first aspect of an embodiment of the present invention, a device for testing BMC serial port bandwidth is provided, the device comprising: an FPGA board and a terminal device;

[0006] The terminal device is used to send a test bit stream for testing the BMC serial port to the FPGA board;

[0007] The FPGA board is configured to obtain a master CPU core and multiple test CPU cores after receiving the test bit stream; the master CPU core performs data transmission with the multiple test CPU cores respectively; and each of the multiple test CPU cores performs data transmission with its corresponding device under test respectively;

[0008] The terminal device is further configured to set test configuration information and send the test configuration information to the main control CPU core;

[0009] The master CPU core is used to parse the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and send the test task to each target test CPU core;

[0010] Each target test CPU core among the multiple test CPU cores is used to control the device under test corresponding to each target test CPU core to execute the test task according to the test task to obtain a test result, wherein the device under test is a BMC serial port;

[0011] The master CPU core is used to receive the test results of each target test CPU core and send them to the terminal device;

[0012] The terminal device is used to display the test results according to the corresponding relationship between the device to be tested and the test results.

[0013] Optionally, the main control CPU core further includes a start-test instruction sending unit;

[0014] The start test instruction sending unit is used to send a start test instruction after each target test CPU core sends the received test task to the corresponding device under test;

[0015] The target test CPU cores are further configured to control the devices to be tested corresponding to the target test CPU cores to execute the test tasks upon receiving the start test instruction according to the test tasks, so as to obtain test results.

[0016] Optionally, the main control CPU core and the multiple test CPU cores respectively transmit data in a manner including CAN data transmission and GPIO data transmission;

[0017] The master CPU core sends the test task to each target test CPU core via the CAN data transmission;

[0018] After each target test CPU core receives the test task, the start test instruction sending unit sends the start test instruction through the GPIO data transmission.

[0019] Optionally, in the case where the test task in the test configuration information includes multiple test tasks, the master CPU core is further used to parse the test configuration information to determine each test task in the test configuration information and a target test CPU core that executes each test task respectively, and send each test task to its corresponding target test CPU core;

[0020] The target test CPU core that executes each test task is used to control the device under test corresponding to itself to execute the test task according to the test task received by itself, so as to obtain a test result.

[0021] Optionally, the GPIO data transmission is configured as an interrupt input.

[0022] Optionally, each of the target test CPU cores is configured to send the test results obtained by executing the test task on the corresponding device under test to the master control CPU core;

[0023] The main control CPU core is used to send the received test results to the terminal device that generates the test bit stream.

[0024] In a second aspect of an embodiment of the present invention, a method for testing BMC serial port bandwidth is provided, the method comprising:

[0025] Send the test bit stream of the BMC serial port to the FPGA board through the terminal device;

[0026] After receiving the test bit stream, the FPGA board obtains a master CPU core and multiple test CPU cores; wherein the master CPU core performs data transmission with the multiple test CPU cores respectively; each of the multiple test CPU cores performs data transmission with its corresponding device under test respectively;

[0027] Setting configuration information through the terminal device and sending the test configuration information to the main control CPU core;

[0028] The master CPU core parses the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and sends the test task to each target test CPU core;

[0029] According to the test task, each target test CPU core controls the device under test corresponding to each target test CPU core to execute the test task to obtain a test result, wherein the device under test is a BMC serial port;

[0030] The master CPU core receives the test results of each target test CPU core and sends them to the terminal device;

[0031] The terminal device displays the test result according to the corresponding relationship between the device to be tested and the test result.

[0032] Optionally, the method further includes:

[0033] After each target test CPU core sends the received test task to the corresponding device under test, the master control CPU core sends a start test instruction;

[0034] According to the test task, the target test CPU cores control the devices under test corresponding to the target test CPU cores to execute the test tasks to obtain test results, including:

[0035] According to the test task, when the target test CPU cores receive the start test instruction, the devices under test corresponding to the target test CPU cores are controlled to execute the test task to obtain a test result.

[0036] Optionally, the data connection and transmission methods between the main control CPU core and the multiple test CPU cores include CAN data transmission and GPIO data transmission; the main control CPU core sends the test task through the CAN data transmission, and the main control CPU core sends the start test instruction through the GPIO data transmission, wherein the GPIO data transmission is configured as an interrupt input.

[0037] Optionally, when the test task in the test configuration information includes multiple test tasks, the master control CPU core parses the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and sends the test task to each target test CPU core; according to the test task, each target test CPU core controls the device under test corresponding to each target test CPU core to execute the test task to obtain a test result, including:

[0038] The main control CPU core parses the test configuration information to determine the test tasks in the test configuration information and the target test CPU core that executes the test tasks respectively; the target test CPU core that executes the test tasks respectively controls the corresponding device under test to execute the test task according to the test task it receives to obtain the test result.

[0039] Optionally, the method further includes:

[0040] Each target test CPU core sends the test results obtained by executing the test task on the corresponding device under test to the main control CPU core;

[0041] The main control CPU core sends the received test results to the terminal device that generates the test bit stream.

[0042] In a third aspect of an embodiment of the present invention, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0043] Memory for storing computer programs;

[0044] The processor is configured to implement the steps of the method for testing the BMC serial port bandwidth as described in the second aspect of the present invention when executing the program stored in the memory.

[0045] In a fourth aspect of the embodiments of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method for testing the BMC serial port bandwidth as described in the second aspect of the present invention is implemented.

[0046] Compared with the prior art, the present invention has the following advantages:

[0047] An embodiment of the present invention provides a device for testing the bandwidth of a BMC serial port. The terminal device's test software includes a test bitstream for testing the BMC serial port. This test bitstream is then distributed to an FPGA board via the terminal device's test software. After the FPGA board downloads the test bitstream, the FPGA board immediately obtains a test framework for testing the BMC serial port, including a master CPU core and multiple test CPU cores. The test bitstream includes a test program. After the test framework is successfully constructed, each of the multiple test CPU cores also obtains a test program for testing the BMC serial port. After the test framework is constructed on the FPGA board, test configuration information is configured via the terminal device's test software and sent to the master CPU core. The master CPU core parses the received test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task. The master CPU core then sends the test task to each target test CPU core. Upon receiving the test task, each target test CPU core controls its corresponding BMC serial port to execute the test task, thereby obtaining a test result. After obtaining the test results, they are sent to the main control CPU core, which then returns them to the terminal device. The terminal device displays the test results based on their correspondence with the BMC serial ports and uses statistical test results to determine the maximum operating performance of multiple BMC serial ports operating simultaneously. This prevents the impact of current test equipment performance on test accuracy and enables accurate testing of the maximum performance of multiple BMC serial ports operating simultaneously.

[0048] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0050] Figure 1 A schematic diagram of the structure of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention;

[0051] Figure 2 Another structural diagram of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention;

[0053] Figure 4 A flowchart of a CPU core test method for testing BMC serial port bandwidth provided by an embodiment of the present invention;

[0054] Figure 5 This is a workflow diagram of the main control CPU core in a method for testing BMC serial port bandwidth provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings.

[0056] Before explaining the present invention, let's first explain its background. BMC is a small monitoring system independent of the server system. Its function is to facilitate remote management, monitoring, installation, and restart of the server. The BMC is a chip integrated into the motherboard (it can also be plugged into the motherboard through various means such as PCIE). It appears externally as a standard RJ45 network port with a dedicated IP address. Routine maintenance requires only accessing the IP:PORT login management page using a browser. Server clusters generally use BMC commands for large-scale unattended operation.

[0057] The server's BMC chip has multiple serial ports (generally 12), which are connected to the server. Multiple serial ports share system resources, and their communication capabilities will affect each other. Clearly testing the BMC chip's serial port performance is conducive to designing a reliable server BMC system solution. Therefore, it is particularly important to understand the communication capabilities of the BMC chip's serial port. Currently, the method for testing the performance of the BMC serial port is to use a computer plus a serial port card to test the BMC serial port performance. However, due to the continuous increase in the communication rate of the BMC serial port, the consumption of system resources in this testing method is also increasing. As a result, the performance of the test equipment in this testing method can no longer meet the requirements for testing the maximum working performance of the existing multiple BMC serial ports working simultaneously. In view of this, the present invention proposes a new BMC serial port bandwidth testing device to meet the requirements for testing the maximum working performance of multiple serial ports working simultaneously with the current BMC serial port with increasing communication rate.

[0058] Figure 1 A schematic diagram of the structure of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention. Figure 1 As shown, the device includes: an FPGA board and a terminal device, Figure 1 The PHY in the terminal device is a terminal device; the terminal device is used to send a test bit stream for testing the BMC serial port to the FPGA board; the FPGA board is used to obtain a master CPU core and multiple test CPU cores after receiving the test bit stream, Figure 1 MB0 is the main control CPU core. Figure 1 MB1-MB12 in the test CPU core is the test CPU core; the master CPU core transmits data with the multiple test CPU cores respectively; each test CPU core in the multiple test CPU cores transmits data with its corresponding device under test respectively; the terminal device is also used to set test configuration information and send the test configuration information to the master CPU core; the master CPU core is used to parse the test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task, and send the test task to the target test CPU cores; the target test CPU cores in the multiple test CPU cores are used to control the device under test corresponding to each target test CPU core to execute the test task according to the test task to obtain the test result, and the device under test is a BMC serial port; the master CPU core is used to receive the test results of the target test CPU cores and send them to the terminal device; the terminal device is used to display the test result according to the correspondence between the device under test and the test result. Figure 1 The RS232 shown in the figure are the serial ports of the BMC chip.

[0059] In an embodiment of the present invention, an FPGA board and a terminal device are provided in an apparatus for testing the bandwidth of a BMC serial port. The terminal device is configured to send a test bit stream for testing the BMC serial port to the FPGA board.

[0060] Specifically, the terminal device in the BMC serial port bandwidth test apparatus is equipped with test software. This test software includes a built-in test bitstream for testing the BMC serial port. The test bitstream for testing the BMC serial port is sent to the FPGA board via the terminal device. After downloading the test bitstream, the FPGA board immediately obtains a test framework consisting of a master CPU core and multiple test CPU cores. Each test CPU core in this test framework also receives a test program. The master CPU core is responsible for overall coordination, while the test CPU cores are responsible for testing the specific serial port performance of the BMC. One test CPU core corresponds to one serial port of each BMC.

[0061] Preferably, since the BMC chip has a maximum of 12 serial ports, the number of test CPU cores in the test framework is preferably 12. It should be understood that this is only a preferred embodiment, and the number of test CPU cores can also be set to other numbers according to actual application conditions, and no specific limitation is made here. At the same time, the MicroBlaze CPU core is a RISC processor soft core that can be embedded in an FPGA. It has the characteristics of fast running speed, low resource consumption, and strong configurability. Therefore, in the present invention, a master CPU core and multiple test CPU cores each use an independent MicroBlaze CPU core. It should be understood that this is only a preferred embodiment, and a master CPU core and multiple test CPU cores in the present invention can also use other CPU cores, and no specific limitation is made here.

[0062] In an embodiment of the present invention, the main control CPU core is connected to multiple test CPU cores respectively for data transmission. A preferred connection method is CAN connection. The main control CPU core is connected to each test CPU core respectively through CAN connection to transmit data, or transmits data through shared memory. Since each test CPU core works independently of each other, its peripheral serial ports do not affect each other. Each test CPU core in the multiple test CPU cores transmits data with its corresponding device under test respectively. A preferred connection method is UART connection. The test CPU core is connected to its corresponding device under test through a UART connection. Among them, the device under test is the serial port of the BMC chip. A test CPU core in the present invention corresponds to a serial port in the BMC chip, and the test CPU core and the serial port in the BMC chip are in a one-to-one correspondence.

[0063] After the FPGA completes the construction of a test framework consisting of a master CPU core and multiple test CPU cores, the terminal device is also used to set test configuration information and send this test configuration information to the master CPU core. The master CPU core controls the test CPU core based on this test configuration information to execute the test task on the device under test. The test configuration information includes the test task, the test CPU core that executes the test task, the test duration, and the test mode. The test mode includes the receive mode, the transmit mode, and the receive-transmit mode. The terminal device and the FPGA board are connected via a network, and other buses can also be used for communication.

[0064] The main control CPU core is used to parse the test configuration information to determine the test task in the test configuration information and the various target test CPU cores connected to the device under test that needs to execute the test task. After parsing and obtaining the test task and the various target test CPU cores that execute the test task, the main control CPU core sends the test task to the various target test CPU cores that execute the test task. Each of the target test CPU cores in the multiple test CPU cores is used to control the device under test connected to itself to execute the test task through the test program according to the received test task to obtain the test result. The device under test is the BMC serial port. Among them, the test configuration information includes the test task and the BMC serial port that executes the test task. The test task includes at least the test duration and the test mode. The test module includes the receiving mode, the sending mode and the receiving and transmitting mode. Among them, since the BMC serial port corresponds one to one with the test CPU core, when the BMC serial port that executes the test task is determined, the target test CPU core that executes the test task is also determined.

[0065] For example, the multiple test CPU cores include MB1 to MB12. The master CPU core parses the test configuration information and determines that test task A is assigned. The target test CPU cores to execute test task A are MB1, MB2, MB3, MB4, and MB6. After obtaining the parsed results, the master CPU core sends the parsed test task A to the test CPU cores MB1, MB2, MB3, MB4, and MB6. The test CPU cores MB1, MB2, MB3, MB4, and MB6 execute the test task on their connected devices under test, obtaining their respective test results.

[0066] In the present invention, the main control CPU core also includes a start test instruction sending unit; the start test instruction sending unit is used to send a start test instruction after each target test CPU core sends the received test task to its corresponding device under test; each target test CPU core is also used to control the device under test corresponding to each target test CPU core to execute the test task according to the test task when receiving the start test instruction to obtain a test result.

[0067] In an embodiment of the present invention, it is necessary to test the extreme working performance of multiple BMC serial ports working simultaneously. Therefore, it is particularly important to accurately control the time when multiple BMC serial ports work simultaneously. Since each target test CPU core needs to send the test task to its respective device under test after receiving the test task. If a startup test instruction is directly added to the test task, due to the data transmission delay when the master CPU core transmits the test task to each device under test, the time when different devices under test receive the test task will be deviated, and this will cause the starting time when each BMC serial port works simultaneously to be deviated, thereby causing the accuracy of the final test result that characterizes the extreme working performance of multiple BMC serial ports working simultaneously to be affected to a certain extent. In order to solve this problem, the present invention sends the test task and the startup test instruction for starting the test task separately. After each target test CPU core sends the received test task to its corresponding device under test, the master CPU core sends the startup test instruction to control each target test CPU core to start the test task for each device under test at the same time through the test program.

[0068] Specifically, the master control CPU core also includes a start-test instruction sending unit. This start-test instruction sending unit is used to send a start-test instruction to each target test CPU core via a CAN connection after each target test CPU core sends the received test task to its corresponding device under test. After the devices under test are ready to execute the test task, each target test CPU core controls its respective device under test to execute the test task simultaneously through the test program. This improves the accuracy of the simultaneous start of the test task, thereby making the final test results that characterize the extreme working performance of multiple BMC serial ports working simultaneously more accurate.

[0069] In the present invention, the methods of data transmission between the main control CPU core and the multiple test CPU cores include CAN data transmission and GPIO data transmission; the main control CPU core sends the test task to the respective target test CPU cores through the CAN data transmission; after the respective target test CPU cores receive the test task, the start test instruction sending unit sends the start test instruction through the GPIO data transmission.

[0070] In the embodiment of the present invention, since the CAN connection requires an address in data transmission, there will still be a certain time deviation in the startup test instructions received by each target test CPU core, which will lead to a certain deviation in the startup time of multiple BMC serial ports working simultaneously. As a result, the final test results characterizing the extreme working performance of multiple BMC serial ports working simultaneously will still be subject to the problem of insufficient accuracy caused by non-synchronous startup testing. Figure 2 Another structural diagram of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention is as follows Figure 2 As shown, in order to further solve this problem, the present invention performs data transmission through two data transmission methods. On the basis of the method in which the main control CPU core is connected to each test CPU core through CAN, a GPIO (General Purpose Input Output) connection is added, that is, the main control CPU core is connected to each test CPU core through two connection methods. GPIO is similar to a time synchronization system. Sending a start test instruction through the GPIO connection can enable each target test CPU core to receive the start test instruction more synchronously. Therefore, the present invention sends the test task through the CAN connection method. After each target test CPU core sends the received test task to its corresponding device under test, and the devices under test are ready to execute the test task, the start test instruction is sent to each target test CPU core through the GPIO (General Purpose Input Output) connection to control each device under test to start the test task more accurately and simultaneously, so that the final test result can more accurately characterize the extreme working performance of multiple BMC serial ports working simultaneously.

[0071] Specifically, the master CPU core sends the test task to each target test CPU core that executes the test task via CAN data transmission. After each target test CPU core receives the test task and sends it to its corresponding device under test, so that the device under test is ready to execute the test task, the master CPU core's start test instruction sending unit then sends a start test instruction via GPIO data transmission to control each target test CPU core to simultaneously start executing the test task.

[0072] In the present invention, when the test task in the test configuration information includes multiple test tasks, the main control CPU core is also used to parse the test configuration information to determine the various test tasks in the test configuration information and the target test CPU cores that respectively execute the various test tasks, and send the various test tasks to their respective corresponding target test CPU cores; the target test CPU cores that respectively execute the various test tasks are used to control the corresponding device under test to execute the test task according to the test task received by themselves to obtain the test results.

[0073] In embodiments of the present invention, the present invention aims to increase the diversity of testing tasks so that test results can more accurately reflect the extreme performance of multiple BMC serial ports operating simultaneously in actual applications. A first aspect of the present invention provides a novel BMC serial port bandwidth testing device that not only achieves the extreme performance of multiple BMC serial ports simultaneously executing the same test task, but also enables multiple BMC serial ports to simultaneously execute different test tasks to obtain test results, thereby more accurately reflecting the extreme performance of multiple BMC serial ports operating simultaneously in actual applications.

[0074] Specifically, the test configuration information includes multiple different test tasks. The master control CPU core parses the test configuration information to obtain the multiple test tasks included in the test configuration information, identifies the corresponding target test CPU core to execute each test task, and sends each test task to its corresponding target test CPU core. Each target test CPU core, based on the received test task, controls its corresponding device under test (DUT) through the test program to execute the test task, thereby obtaining test results.

[0075] For example, multiple test CPU cores include MB1 to MB12, and the main control CPU core parses the test configuration information to determine the test tasks B, C, and D included therein, where the target test CPU cores for executing test task B are MB1 and MB2, the target test CPU cores for executing test task C are MB3 and MB4, and the target test CPU cores for executing test task D are MB5 and MB6.

[0076] The master CPU core sends test task B to target test CPU cores MB1 and MB2 via CAN connection, the master CPU core sends test task C to target test CPU cores MB3 and MB4 via CAN connection, and the master CPU core sends test task D to target test CPU cores MB5 and MB6 via CAN connection.

[0077] After receiving test task B, the target test CPU cores MB1 and MB2 send test task B to their corresponding devices under test. After receiving test task C, the target test CPU cores MB3 and MB4 send test task C to their corresponding devices under test. After receiving test task D, the target test CPU cores MB5 and MB6 send test task D to their corresponding devices under test.

[0078] After each device under test receives the test task it needs to execute, the start test instruction sending unit in the main control CPU core sends a start test instruction to the target test CPU cores MB1 to MB6 through the GPIO connection to control the devices under test corresponding to the target test CPU cores MB1 to MB6 to execute their respective test tasks.

[0079] In the present invention, the GPIO data transmission is configured as an interrupt input.

[0080] In an embodiment of the present invention, in order to improve the accuracy of each target test CPU synchronously receiving the start test instruction, the present invention configures GPIO data transmission as an interrupt input mode.

[0081] In the present invention, each target test CPU core is used to send the test results obtained by the corresponding device under test executing the test task to the main control CPU core; the main control CPU core is used to send the received test results to the terminal device that generates the test bit stream.

[0082] In an embodiment of the present invention, after each target test CPU core controls its corresponding device under test to complete a test task, it obtains its own test result. After obtaining the test result, each target test CPU core is configured to send the obtained test result to the master control CPU core. After receiving the test result, the master control CPU core performs statistical analysis on it to obtain a final test result, and then sends the final test result to the terminal device that generates the test bitstream.

[0083] In an embodiment of the present invention, Figure 3 Schematic diagram of a device for testing BMC serial port bandwidth provided by an embodiment of the present invention. Figure 2 and Figure 3 As shown, an embodiment of the present invention provides a device for testing the bandwidth of a BMC serial port, which includes a terminal device and an FPGA board. Figure 3 The PHY in this example represents a terminal device, such as a network-connected PC, server, or embedded device. This terminal device contains test software that transmits a test bitstream for testing the BMC serial port to the FPGA. After the FPGA downloads the test bitstream, the FPGA receives a test framework consisting of a master CPU core and multiple test CPU cores.

[0084] Specifically, the engineering personnel select the test bit stream of the BMC serial port through the test software of the terminal device and send it to the FPGA board. After the FPGA board downloads the test bit stream, it immediately obtains a test framework including a main control CPU core and multiple test CPU cores. Each test CPU core in the test framework also obtains a test program. The main control CPU core is responsible for overall coordination work, and the test CPU core is responsible for the specific serial port working performance test of the BMC. One test CPU core corresponds to one serial port of the BMC. After completing the construction of the test framework, the terminal device sends the test configuration information set by the test software to the main control CPU core through the test software. The main control CPU core parses the test configuration information to obtain the test tasks included in the test configuration information and the various target test CPU cores connected to the device under test that needs to execute the test task, and sends the test task to each target test CPU core through the main control CPU core. Among them, the target test CPU core represents the test CPU core that currently needs to execute the test task among the test CPU cores. Each target test CPU core receives a test task and, based on the test task received, controls the corresponding device to be tested to execute the test task through the test program to obtain a test result. In the embodiment of the present invention, the device to be tested is a BMC serial port. After each target test CPU core completes the test task, the test result is sent to the master CPU core. The master CPU core analyzes and counts the received test results to obtain a final test result that characterizes the extreme working performance of multiple BMC serial ports working simultaneously. The final test result and the test results of each target test CPU core are sent to the terminal device. The terminal device displays the test result based on the correspondence between the device to be tested and the test result, and displays the final test result that characterizes the extreme working performance of multiple BMC serial ports working simultaneously.

[0085] In an embodiment of the present invention, the test configuration information includes a test task and a test CPU core that executes the test task. The test task includes at least a test duration and a test mode. The test mode includes a receive mode, a transmit mode, and a receive-transmit mode. The terminal device and the FPGA board are connected via a network, but other buses may also be used for communication.

[0086] In the embodiment of the present invention, the main function of the FPGA board in the final test framework is to use 13 independent MicroBlaze CPU cores, the architecture is as follows: Figure 2 As shown in the figure, the main control CPU core MB0 (MicroBlaze) is responsible for overall coordination, while the test CPU cores MB1-MB12 are responsible for specific BMC serial port performance testing. The MicroBlaze embedded soft core is a RISC processor soft core that can be embedded in an FPGA. It has the advantages of fast operation, low resource consumption, and strong configurability.

[0087] An embodiment of the present invention provides a device for testing the bandwidth of a BMC serial port. The test bit stream used to test the BMC serial port is developed in advance by engineering personnel based on the configuration of the BMC serial port and is built into the test software of the terminal device. When it is necessary to test a device to be tested such as a BMC serial port, the test bit stream is selected by the terminal device and sent to the FPGA board of the present invention. After the FPGA board downloads the test bit stream, a test framework for BMC serial port testing is immediately constructed, and then subsequent test operations are performed through the test framework. The subsequent test operations are the same as the implementation process in the above-mentioned embodiment and will not be repeated here.

[0088] At the same time, the device for testing the bandwidth of a BMC serial port provided by an embodiment of the present invention is not only applicable to testing the BMC serial port, but also applicable to other devices to be tested that are different from the BMC serial port. Specifically, through the device for testing the bandwidth of a BMC serial port provided by the present invention, an engineering staff first develops a corresponding test bit stream in advance based on the configuration of the other device to be tested that is different from the BMC serial port, and builds it into the test software of the terminal device. When it is necessary to perform a test task on the other device to be tested that is different from the BMC serial port, the terminal device selects the test bit stream for testing the other device to be tested that is different from the BMC serial port from the test software, and sends it to the FPGA board. After the FPGA board receives the test bit stream, it immediately constructs a test framework for testing the other device to be tested that is different from the BMC serial port. Then, the test configuration information is set through the test software of the terminal device, and sent to the test framework in the FPGA board, so that the test framework performs the corresponding test task based on the test configuration information.

[0089] An embodiment of the present invention provides a device for testing the bandwidth of a BMC serial port. The terminal device's test software includes a test bitstream for testing the BMC serial port. This test bitstream is then distributed to an FPGA board via the terminal device's test software. After the FPGA board downloads the test bitstream, the FPGA board immediately obtains a test framework for testing the BMC serial port, including a master CPU core and multiple test CPU cores. The test bitstream includes a test program. After the test framework is successfully constructed, each of the multiple test CPU cores also obtains a test program for testing the BMC serial port. After the test framework is constructed on the FPGA board, test configuration information is configured via the terminal device's test software and sent to the master CPU core. The master CPU core parses the received test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task. The master CPU core then sends the test task to each target test CPU core. Upon receiving the test task, each target test CPU core controls its corresponding BMC serial port to execute the test task, thereby obtaining a test result. After obtaining the test results, they are sent to the main control CPU core, which then returns them to the terminal device. The terminal device displays the test results based on their correspondence with the BMC serial ports and uses statistical test results to determine the maximum operating performance of multiple BMC serial ports operating simultaneously. This prevents the impact of current test equipment performance on test accuracy and enables accurate testing of the maximum performance of multiple BMC serial ports operating simultaneously.

[0090] In a second aspect of an embodiment of the present invention, a method for testing the bandwidth of a BMC serial port is provided, the method comprising: sending a test bit stream for testing the BMC serial port to an FPGA board through a terminal device; after receiving the test bit stream, the FPGA board obtains a main control CPU core and multiple test CPU cores; wherein, the main control CPU core performs data transmission with the multiple test CPU cores respectively; each of the multiple test CPU cores performs data transmission with its corresponding device under test respectively; setting configuration information through the terminal device, and sending the test configuration information to the main control CPU core; the main control CPU core performs data transmission with the multiple test CPU cores respectively; The PU core parses the test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task, and sends the test task to the target test CPU cores; according to the test task, the target test CPU cores control the devices under test corresponding to the target test CPU cores to execute the test task to obtain test results, where the devices under test are BMC serial ports; the master CPU core receives the test results of the target test CPU cores and sends them to the terminal device; the terminal device displays the test results based on the correspondence between the devices under test and the test results.

[0091] In an embodiment of the present invention, the terminal device in the apparatus for testing BMC serial port bandwidth provided by the present invention is equipped with test software. The test software includes a built-in test bitstream for testing the BMC serial port. The test bitstream for testing the BMC serial port is sent to the FPGA board via the terminal device. After downloading the test bitstream, the FPGA board immediately obtains a test framework including a master CPU core and multiple test CPU cores. Each test CPU core in the test framework also obtains a test program. The master CPU core is responsible for overall coordination, while the test CPU core is responsible for testing the specific serial port performance of the BMC. One test CPU core corresponds to one serial port of each BMC.

[0092] In an embodiment of the present invention, the main control CPU core is connected to multiple test CPU cores respectively for data transmission. A preferred connection method is CAN connection. The main control CPU core is connected to each test CPU core respectively through CAN connection to transmit data, or transmits data through shared memory. Since each test CPU core works independently of each other, its peripheral serial ports do not affect each other. Each test CPU core in the multiple test CPU cores transmits data with its corresponding device under test respectively. A preferred connection method is UART connection. The test CPU core is connected to its corresponding device under test through a UART connection. Among them, the device under test is the serial port of the BMC chip. A test CPU core in the present invention corresponds to a serial port in the BMC chip, and the test CPU core and the serial port in the BMC chip are in a one-to-one correspondence.

[0093] After the FPGA completes the construction of the test framework, which includes a master CPU core and multiple test CPU cores, the terminal device sends the test configuration information set by the test software to the master CPU core. The master CPU core parses the test configuration information to determine the test task in the test configuration information and the target test CPU cores connected to the device under test that need to perform the test task. After parsing and obtaining the test task and the target test CPU cores that perform the test task, the master CPU core sends the test task to the target test CPU cores that perform the test task. Based on the received test task, each target test CPU core controls the device under test connected to it through the test program to execute the test task and obtain the test results. The device under test is the BMC serial port.

[0094] In the present invention, the method also includes: after each target test CPU core sends the received test task to its corresponding device under test, the master CPU core sends a start test instruction; according to the test task, the each target test CPU core controls the device under test corresponding to each target test CPU core to execute the test task to obtain the test result, including: according to the test task, when each target test CPU core receives the start test instruction, the each target test CPU core controls the device under test corresponding to each target test CPU core to execute the test task to obtain the test result.

[0095] In an embodiment of the present invention, it is necessary to test the extreme working performance of multiple BMC serial ports working simultaneously. Therefore, it is particularly important to accurately control the time when multiple BMC serial ports work simultaneously, and since each target test CPU core needs to send the test task to its respective device under test after receiving the test task. If a startup test instruction is directly added to the test task, due to the data transmission delay when the master CPU core transmits the test task to each device under test, the time when different devices under test receive the test task will be deviated, and this will cause the starting time when each BMC serial port works simultaneously to be deviated, thereby causing the accuracy of the final test result that characterizes the extreme working performance of multiple BMC serial ports working simultaneously to be affected to a certain extent. In order to solve this problem, the present invention sends the test task and the startup test instruction for starting the test task separately. After each target test CPU core sends the received test task to its corresponding device under test, the master CPU core sends the startup test instruction to control each target test CPU core to simultaneously start the test task for its respective task under test.

[0096] Specifically, the master CPU core parses the test configuration information to determine the test task in the test configuration information and the various target test CPU cores that execute the test task, and sends the test task obtained by parsing to the various target test CPU cores that execute the test task. Each target test CPU core will receive the test task and send the received test task to its corresponding device under test. After the devices under test are ready to execute the test task, the master CPU core will send a start test instruction to each target test CPU core via the CAN connection. After receiving the start test instruction, each target test CPU core controls its own device under test to execute the test task at the same time, thereby improving the accuracy of starting to execute the test task at the same time, thereby making the final test result that characterizes the extreme working performance of multiple BMC serial ports working at the same time more accurate.

[0097] In the present invention, the data connection and transmission methods between the main control CPU core and the multiple test CPU cores include CAN data transmission and GPIO data transmission; the main control CPU core sends the test task through the CAN data transmission, and the main control CPU core sends the start test instruction through the GPIO data transmission, wherein the GPIO data transmission is configured as an interrupt input.

[0098] In an embodiment of the present invention, because the CAN connection requires an address during data transmission, this will result in a certain time deviation between the startup test instructions received by each target test CPU core, resulting in a certain deviation in the startup time of multiple BMC serial ports operating simultaneously. As a result, the final test results representing the ultimate performance of multiple BMC serial ports operating simultaneously will still be subject to the problem of insufficient accuracy caused by the lack of synchronous startup testing. To further address this problem, the present invention uses two data transmission methods for data transmission. On the basis of the method of CAN connection between the main control CPU core and each test CPU core, a GPIO (General Purpose Input Output) connection is added. In other words, the main control CPU core is connected to each test CPU core separately through two connection methods. GPIO is similar to a time synchronization system. Sending the startup test instruction through this GPIO connection allows each target test CPU core to receive the startup test instruction more synchronously. Therefore, the present invention sends test tasks between the main control CPU core and the target test CPU core through a CAN connection. After each target test CPU core sends the received test task to its corresponding device under test, and the devices under test are ready to execute the test task, a start test instruction is sent to each target test CPU core through a GPIO (General Purpose Input Output) connection to control each device under test to start the test task more accurately and simultaneously, so that the final test result can more accurately characterize the extreme working performance of multiple BMC serial ports working simultaneously.

[0099] Specifically, the master CPU core sends the test task to each target test CPU core that executes the test task via CAN data transmission. After each target test CPU core receives the test task and sends it to its corresponding device under test, preparing the device under test to execute the test task, the master CPU core then sends a start test instruction via GPIO data transmission to control each target test CPU core to simultaneously start executing the test task.

[0100] In an embodiment of the present invention, in order to improve the accuracy of each target test CPU synchronously receiving the start test instruction, the present invention configures GPIO data transmission as an interrupt input mode.

[0101] In the present invention, when the test task in the test configuration information includes multiple test tasks, the main control CPU core parses the test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task, and sends the test task to the target test CPU cores; according to the test task, the target test CPU cores control the devices under test corresponding to the target test CPU cores to execute the test task to obtain test results, including: the main control CPU core parses the test configuration information to determine the test tasks in the test configuration information and the target test CPU cores that execute the test tasks respectively; the target test CPU cores that execute the test tasks respectively control the devices under test corresponding to themselves to execute the test tasks according to the test tasks received by themselves to obtain test results.

[0102] In an embodiment of the present invention, the present invention aims to increase the diversity of test work so that the test results can more accurately reflect the extreme working performance of multiple BMC serial ports working simultaneously in actual applications. The test tasks in the test configuration information of the present invention can include multiple different test tasks.

[0103] Specifically, the test configuration information can include multiple different test tasks. The master control CPU core parses the test configuration information to identify each test task, then determines the target test CPU core that will execute each test task. The master control CPU core then sends each test task to its corresponding target test CPU core. Each target test CPU core then controls its corresponding device under test (DUT) to execute the test task based on the received test task, using the test program, to obtain test results.

[0104] For example, multiple test CPU cores include MB1 to MB12, and the main control CPU core parses the test configuration information to determine that the test tasks E, F, and G are included, where the target test CPU cores for executing test task E are MB7 and MB8, the target test CPU cores for executing test task F are MB9 and MB10, and the target test CPU cores for executing test task G are MB11 and MB12.

[0105] The master CPU core sends test task E to target test CPU cores MB7 and MB8 via CAN connection, the master CPU core sends test task F to target test CPU cores MB9 and MB10 via CAN connection, and the master CPU core sends test task G to target test CPU cores MB11 and MB12 via CAN connection.

[0106] After receiving test task E, the target test CPU cores MB7 and MB8 send test task E to their corresponding devices under test. After receiving test task F, the target test CPU cores MB9 and MB10 send test task F to their corresponding devices under test. After receiving test task G, the target test CPU cores MB11 and MB12 send test task G to their corresponding devices under test.

[0107] After each device under test receives the test task it needs to execute, the start test instruction sending unit in the main control CPU core sends the start test instruction to the target test CPU cores MB7 to MB12 through the GPIO connection to control the devices under test corresponding to the target test CPU cores MB7 to MB12 to execute their respective test tasks.

[0108] In the present invention, the method further includes: each target test CPU core sends the test results obtained by executing the test task by the corresponding device under test to the master CPU core; the master CPU core sends the received test results to the terminal device that generates the test bit stream.

[0109] In an embodiment of the present invention, after each target test CPU core controls its corresponding device under test to complete a test task, it obtains its own test result. After obtaining the test result, each target test CPU core sends the obtained test result to the master control CPU core. After receiving the test result, the master control CPU core performs statistical analysis on it to obtain a final test result, which it then sends to the terminal device that generates the test bitstream.

[0110] In an embodiment of the present invention, Figure 4 A flowchart of a CPU core test method for testing BMC serial port bandwidth provided by an embodiment of the present invention; Figure 5 The flowchart of the main control CPU core in the method for testing the BMC serial port bandwidth provided by the embodiment of the present invention is as follows. Figure 5As shown, the working process of the master CPU core is to initialize itself before the previous test task is completed and the next test task starts, and then prepare to execute the next test task; first, it parses the test configuration information to determine the test task and the target test CPU core that executes the test task, and then sends the test task to the target test CPU core; after the target test CPU core receives the test task and sends it to its corresponding device under test, the master CPU core sends a start test instruction through GPIO to notify each target test CPU core to control the execution of the test task, and after receiving the test results sent by each target test CPU core, it parses and counts the test results to obtain the final test results, and uploads the final test results to the terminal device. Figure 4 As shown, the working process of the test CPU core is to initialize itself before the previous test task is completed and the next test task starts, and then prepare to execute the next test task; when the test CPU core is the target test CPU core that needs to execute the test task, it receives the test task sent by the main control CPU core, and sends the received test task to the device under test to notify the device under test to prepare to execute the test task. After all target test CPU cores send the test tasks to their corresponding devices under test, they receive the start test instruction sent by the main control CPU core. According to the start test instruction, each target test CPU core synchronously controls its corresponding device under test to execute the test task at the same time. After the test task is completed, it counts its own test results and sends the test results to the main control CPU core.

[0111] An embodiment of the present invention provides a method for testing the bandwidth of a BMC serial port. The terminal device's test software includes a test bitstream for testing the BMC serial port. This test bitstream is then distributed to an FPGA board via the terminal device's test software. After the FPGA board downloads the test bitstream, the FPGA board immediately obtains a test framework for testing the BMC serial port, including a master CPU core and multiple test CPU cores. The test bitstream includes a test program. After the test framework is successfully constructed, each of the multiple test CPU cores also obtains a test program for testing the BMC serial port. After the test framework is constructed on the FPGA board, test configuration information is configured via the terminal device's test software and sent to the master CPU core. The master CPU core parses the received test configuration information to determine the test task in the test configuration information and the target test CPU cores that execute the test task. The master CPU core then sends the test task to each target test CPU core. Upon receiving the test task, each target test CPU core controls its corresponding BMC serial port to execute the test task, thereby obtaining a test result. After obtaining the test results, they are sent to the main control CPU core, which then returns them to the terminal device. The terminal device displays the test results based on their correspondence with the BMC serial ports and uses statistical test results to determine the maximum operating performance of multiple BMC serial ports operating simultaneously. This prevents the impact of current test equipment performance on test accuracy and enables accurate testing of the maximum performance of multiple BMC serial ports operating simultaneously.

[0112] In a third aspect of an embodiment of the present invention, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0113] Memory for storing computer programs;

[0114] The processor is configured to implement the steps of a method for testing the BMC serial port bandwidth provided by the second aspect of the present invention when executing a program stored in the memory.

[0115] In a fourth aspect of the embodiments of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method for testing the BMC serial port bandwidth as described in any of the above embodiments is implemented.

[0116] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state disk (SSD)).

[0117] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0118] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A device for testing BMC serial port bandwidth, characterized in that: The device comprises: an FPGA board and a terminal device; The terminal device is used to send a test bit stream for testing the BMC serial port to the FPGA board; The FPGA board is configured to obtain a master CPU core and multiple test CPU cores after receiving the test bit stream; the master CPU core performs data transmission with the multiple test CPU cores respectively; and each of the multiple test CPU cores performs data transmission with its corresponding device under test respectively; The terminal device is further configured to set test configuration information and send the test configuration information to the main control CPU core; The master CPU core is used to parse the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and send the test task to each target test CPU core; Each target test CPU core among the multiple test CPU cores is used to control the device under test corresponding to each target test CPU core to execute the test task according to the test task to obtain a test result, wherein the device under test is a BMC serial port; The master CPU core is used to receive the test results of each target test CPU core and send them to the terminal device; The terminal device is used to display the test results according to the corresponding relationship between the device to be tested and the test results.

2. The device for testing the BMC serial port bandwidth according to claim 1, wherein: The main control CPU core also includes a start-up test instruction sending unit; The start test instruction sending unit is used to send a start test instruction after each target test CPU core sends the received test task to the corresponding device under test; The target test CPU cores are further configured to control the devices to be tested corresponding to the target test CPU cores to execute the test tasks upon receiving the start test instruction according to the test tasks, so as to obtain test results.

3. The device for testing the BMC serial port bandwidth according to claim 2, wherein: The manner in which the master CPU core performs data transmission with the multiple test CPU cores comprises CAN data transmission and GPIO data transmission; The master CPU core sends the test task to each target test CPU core via the CAN data transmission; After each target test CPU core receives the test task, the start test instruction sending unit sends the start test instruction through the GPIO data transmission.

4. The device for testing the BMC serial port bandwidth according to claim 2, wherein: In the case where the test task in the test configuration information includes multiple test tasks, the master CPU core is further used to parse the test configuration information to determine each test task in the test configuration information and a target test CPU core that executes each test task respectively, and send each test task to the corresponding target test CPU core; The target test CPU core that executes each test task is used to control the device under test corresponding to itself to execute the test task according to the test task received by itself, so as to obtain a test result.

5. The device for testing BMC serial port bandwidth according to claim 3, characterized in that: The GPIO data transmission is configured as an interrupt input.

6. The device for testing the BMC serial port bandwidth according to claim 1, wherein: Each target test CPU core is used to send the test results obtained by executing the test task on the corresponding device under test to the main control CPU core; The main control CPU core is used to send the received test results to the terminal device that generates the test bit stream.

7. A method for testing BMC serial port bandwidth, characterized in that: The method comprises: Send the test bit stream of the BMC serial port to the FPGA board through the terminal device; After receiving the test bit stream, the FPGA board obtains a master CPU core and multiple test CPU cores; wherein the master CPU core performs data transmission with the multiple test CPU cores respectively; each of the multiple test CPU cores performs data transmission with its corresponding device under test respectively; Setting test configuration information through the terminal device and sending the test configuration information to the main control CPU core; The master CPU core parses the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and sends the test task to each target test CPU core; According to the test task, each target test CPU core controls the device under test corresponding to each target test CPU core to execute the test task to obtain a test result, wherein the device under test is a BMC serial port; The master CPU core receives the test results of each target test CPU core and sends them to the terminal device; The terminal device displays the test result according to the corresponding relationship between the device to be tested and the test result.

8. A method for testing BMC serial port bandwidth according to claim 7, characterized in that: The method further comprises: After each target test CPU core sends the received test task to the corresponding device under test, the master control CPU core sends a start test instruction; According to the test task, the target test CPU cores control the devices under test corresponding to the target test CPU cores to execute the test tasks to obtain test results, including: According to the test task, when the target test CPU cores receive the start test instruction, the devices under test corresponding to the target test CPU cores are controlled to execute the test task to obtain a test result.

9. A method for testing BMC serial port bandwidth according to claim 8, characterized in that: The data connection and transmission methods between the main control CPU core and the multiple test CPU cores include CAN data transmission and GPIO data transmission; the main control CPU core sends the test task through the CAN data transmission, and the main control CPU core sends the start test instruction through the GPIO data transmission, wherein the GPIO data transmission is configured as an interrupt input.

10. The method for testing the BMC serial port bandwidth according to claim 8, wherein: In a case where the test task in the test configuration information includes multiple test tasks, the master CPU core parses the test configuration information to determine the test task in the test configuration information and each target test CPU core that executes the test task, and sends the test task to each target test CPU core; According to the test task, each target test CPU core controls the device under test corresponding to each target test CPU core to perform the test task to obtain a test result, including: The master control CPU core parses the test configuration information to determine each test task in the test configuration information and a target test CPU core to execute each test task respectively; The target test CPU core that executes each test task controls its corresponding device under test to execute the test task according to the test task it receives, so as to obtain a test result.

11. The method for testing the BMC serial port bandwidth according to claim 7, wherein: The method further comprises: Each target test CPU core sends the test results obtained by executing the test task on the corresponding device under test to the main control CPU core; The main control CPU core sends the received test results to the terminal device that generates the test bit stream.

12. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; The processor is configured to implement the steps of the method for testing the BMC serial port bandwidth as described in any one of claims 7 to 11 when executing the program stored in the memory.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, a method for testing the BMC serial port bandwidth as described in any one of claims 7 to 11 is implemented.

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