Semiconductor memory device

Abstract

One embodiment of the present invention provides a high-speed semiconductor memory device. The semiconductor memory device of one embodiment includes: a plurality of memory cell arrays, each including a first memory cell and a first word line connected to the first memory cell; a first wiring electrically connected to a plurality of first word lines corresponding to the plurality of memory cell arrays; a driving circuit electrically connected to the first wiring; a plurality of second wirings electrically connected to the first wirings via the driving circuit; a voltage generating circuit having a plurality of output terminals corresponding to the plurality of second wirings; and a plurality of first circuits corresponding to the plurality of memory cell arrays. The voltage generating circuit is electrically connected to the plurality of first word lines via a first current path including the plurality of second wirings, the driving circuit, and the first wirings. Additionally, the voltage generating circuit is electrically connected to the plurality of first word lines via a second current path including the plurality of second wirings and the plurality of first circuits but not including the driving circuit.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-102806 (filed on June 21, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known to include: a plurality of memory cell arrays, comprising a first memory cell and a first word line connected to the first memory cell; and a voltage generation circuit electrically connected to a plurality of first word lines corresponding to the plurality of memory cell arrays. Summary of the Invention

[0005] One embodiment of the present invention provides a high-speed semiconductor memory device.

[0006] One embodiment of a semiconductor memory device includes: a plurality of memory cell arrays, each including a first memory cell and a first word line connected to the first memory cell; a first wiring electrically connected to a plurality of first word lines corresponding to the plurality of memory cell arrays; a driving circuit electrically connected to the first wiring; a plurality of second wirings electrically connected to the first wirings via the driving circuit; a voltage generating circuit having a plurality of output terminals corresponding to the plurality of second wirings; and a plurality of first circuits corresponding to the plurality of memory cell arrays. The voltage generating circuit is electrically connected to the plurality of first word lines via a first current path including the plurality of second wirings, the driving circuit, and the first wirings. Additionally, the voltage generating circuit is electrically connected to the plurality of first word lines via a second current path including the plurality of second wirings and the plurality of first circuits but not including the driving circuit. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0008] Figure 2 This is a schematic side view showing an example of the configuration of the memory system 10 in this embodiment.

[0009] Figure 3 This is a schematic top view representing this configuration example.

[0010] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0011] Figure 5 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0012] Figure 6 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0013] Figure 7 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0014] Figure 8 This is a schematic top view of a memory die (MD).

[0015] Figure 9 This is a schematic top view of a memory die (MD).

[0016] Figure 10 It is Figure 8 A schematic top view shown in enlarged form.

[0017] Figure 11 This is a schematic 3D diagram representing a portion of a memory die (MD).

[0018] Figure 12 yes Figure 11 A schematic enlarged view of part A shown.

[0019] Figure 13 (a) to (c) are schematic diagrams used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0020] Figure 14 It is a schematic cross-sectional view used to illustrate the readout action.

[0021] Figure 15 It is a timing diagram used to explain the reading action.

[0022] Figure 16 It is a flowchart used to explain the write operation.

[0023] Figure 17 It is a schematic cross-sectional view used to illustrate the programming actions contained in the write operation.

[0024] Figure 18 [] is a schematic cross-sectional view used to illustrate the verification actions contained in the write operation.

[0025] Figure 19 It is a timing diagram used to illustrate the write operation.

[0026] Figure 20 It is a flowchart used to explain the erasure action.

[0027] Figure 21 It is a schematic cross-sectional view used to illustrate the erase voltage supply operation included in the erase operation.

[0028] Figure 22 It is a schematic cross-sectional view used to illustrate the verification actions included in the erasure operation.

[0029] Figure 23 It is a timing diagram used to illustrate the erasure action.

[0030] Figure 24 This is a schematic top view of the memory die MD' of the comparative example.

[0031] Figure 25 This is a schematic circuit diagram representing a portion of a memory die MD'.

[0032] Figure 26 This is a schematic circuit diagram representing a portion of a memory die MD'.

[0033] Figure 27 It is a schematic timing diagram used to illustrate other readout actions.

[0034] Figure 28 It is a schematic timing diagram used to illustrate other readout actions.

[0035] Figure 29 It is a schematic timing diagram used to illustrate other readout actions.

[0036] Figure 30 This is a schematic circuit diagram illustrating a portion of a memory die (MD) according to another embodiment. Detailed Implementation

[0037] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Also, sometimes the same symbols are used to denote common parts in multiple embodiments, and descriptions are omitted.

[0038] Additionally, in this specification, when "semiconductor memory device" is mentioned, it sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0039] Furthermore, in this specification, when referring to the first component as "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor can still be "electrically connected" to the third transistor.

[0040] Additionally, in this specification, when it is mentioned that the first component is "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0041] Furthermore, in this specification, when it is mentioned that a circuit or the like "connects" two wirings, it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0042] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0043] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. The first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0044] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a component as a lower surface or lower end, it refers to the surface or end of that component on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that component on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0045] [First Implementation]

[0046] [Memory System 10]

[0047] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0048] The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host computer 20. The memory system 10 may be, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes multiple memory dies (MDs) for storing user data, and a controller die (CD) connected to the multiple memory dies and the host computer 20. The controller die (CD) may include, for example, a processor and RAM (Random Access Memory), and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compression), and wear leveling.

[0049] Figure 2 This is a schematic side view showing an example of the configuration of the memory system 10 in this embodiment. Figure 3 This is a schematic top view illustrating this configuration example. For ease of explanation, Figure 2 and Figure 3 A portion of the composition has been omitted.

[0050] like Figure 2 As shown, the memory system 10 of this embodiment includes a mounting substrate (MSB), multiple memory dies (MDs) stacked on the MSB, and a controller die (CD) stacked on the memory dies. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the MSB, and other regions are bonded to the lower surface of the memory die MDs via adhesive or the like. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the memory die MDs, and other regions are bonded to the lower surface of other memory die MDs or controller die CDs via adhesive or the like. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the controller die CD.

[0051] like Figure 3 As shown, the mounting substrate MSB, multiple memory dies MD, and controller die CD each have multiple pad electrodes P arranged along the X direction. The multiple pad electrodes P disposed on the mounting substrate MSB, multiple memory dies MD, and controller die CD are interconnected via bonding lines B.

[0052] also, Figure 2 and Figure 3 The configuration shown is for illustrative purposes only; the actual configuration can be adjusted accordingly. For example, Figure 2 and Figure 3In the example shown, a controller die CD is stacked on multiple memory dies MD, and these are connected by bonding wires B. In this configuration, the multiple memory dies MD and controller die CD are contained within a single package. However, the controller die CD may also be contained within a different package than the memory dies MD. Furthermore, the multiple memory dies MD and controller die CD may also be interconnected via through electrodes or the like, instead of bonding wires B.

[0053] [Circuit configuration of a memory die (MD)]

[0054] Figure 4 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figures 5-7 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0055] also, Figure 4 The diagram shows multiple control terminals. These control terminals can be represented as control terminals corresponding to high-level signals (positive logic signals), control terminals corresponding to low-level signals (negative logic signals), or control terminals corresponding to both high-level and low-level signals. Figure 4 In the original text, the symbol for the control terminal corresponding to a low-level signal includes an overline (high line). In this specification, the symbol for the control terminal corresponding to a low-level signal includes a forward slash (" / "). Furthermore, Figure 4 The example provided illustrates the situation, and the specific configuration can be adjusted accordingly. For instance, some or all high-level signals can be set to low-level signals, or some or all low-level signals can be set to high-level signals.

[0056] [Circuit Structure]

[0057] like Figure 4 As shown, the memory die MD includes a memory module MM and peripheral circuitry PC.

[0058] [Circuit configuration of memory module MM]

[0059] The memory module MM has plane groups PG0 and PG1. Plane group PG0 has storage planes MP0 to MP7. Plane group PG1 has storage planes MP8 to MP15. Storage planes MP0 to MP15 each have a memory cell array MCA, a line decoder RD, a sense amplifier module SAM, and a cache memory CM.

[0060] [Circuit configuration of a memory cell array (MCA)]

[0061] like Figure 5As shown, the memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to a sense amplifier module (SAM) via a bit line (BL). The other end of each memory string (MS) is connected to a source line driver (not shown) via a common source line (SL).

[0062] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory transistors), a source-side selection transistor (STS), and a source-side selection transistor (STSb). Hereinafter, the drain-side selection transistor (STD), the source-side selection transistor (STS), and the source-side selection transistor (STSb) are sometimes simply referred to as selection transistors (STD, STS, STSb).

[0063] A memory cell (MC) is a field-effect transistor comprising a semiconductor layer functioning as a channel region, a gate insulating film containing a charge storage film, and a gate electrode. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. The memory cell (MC) stores one or more bits of data. Furthermore, multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) function as the gate electrodes of the memory cells (MCs) contained in all memory strings (MS) within a memory block (BLK).

[0064] Select transistors (STD, STS, STSb) are field-effect transistors that possess a semiconductor layer, a gate insulating film, and a gate electrode, all functioning as channel regions. The gate electrodes of the select transistors (STD, STS, STSb) are connected to select gate lines (SGD, SGS, SGSb), respectively. The drain-side select gate line SGD is correspondingly assigned to the string assembly SU and functions as the gate electrode of the drain-side select transistor STD contained in all memory strings MS within a single string assembly SU. The source-side select gate line SGS functions as the gate electrode of the source-side select transistor STS contained in all memory strings MS within a memory block BLK. The source-side select gate line SGSb functions as the gate electrode of the source-side select transistor STSb contained in all memory strings MS within a memory block BLK.

[0065] [Circuit configuration of the line decoder RD]

[0066] For example, such as Figure 6 As shown, the line decoder RD has multiple block decoding components blkd, multiplexer MUX, planar decoding component plnd, and equalizer EQ.

[0067] The block decoding component blkd is configured to correspond to multiple memory blocks BLK in the memory cell array MCA. The block decoding component blkd has multiple transistors T BLK The plurality of transistors T BLK The transistor T is configured to correspond to the multiple word lines WL and select gate lines (SGD, SGS, SGSb) in the memory block BLK. BLK For example, a field-effect type NMOS (N-channel metal oxide semiconductor) transistor.

[0068] transistor T BLK The drain electrode is connected to the word line WL or the select gate line (SGD, SGS, SGSb). Transistor T BLK The source electrode is connected to wiring CGL. Wiring CGL is electrically connected to all memory blocks BLK contained in the memory cell array MCA. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple BLKSEL signal supply lines are provided, corresponding to the block decoding component blkd. Additionally, the BLKSEL signal supply lines are connected to all transistors T in the block decoding component blkd. BLK .

[0069] The output terminals of the multiplexer MUX are connected to wiring CGL. The input terminals of the multiplexer MUX are electrically connected to wiring CG. Figure 6 In the example, this refers to wiring CG1C. The number of wiring CGs is less than the number of wiring CGLs. The multiplexer MUX, based on the input address signal and the control signal from the sequencer SQC, connects wiring CGs to one or more wiring CGLs respectively.

[0070] In addition, for example, such as Figure 4 As shown, the memory die MD can also have wirings CG0A, CG1A, CG0B, CG1B, CG0C, CG1C, CG0D, and CG1D as wirings CG. Additionally, wiring CG0A can be electrically connected to memory planes MP0 and MP4. Figure 4 All memory blocks (BLK) contained in storage planes MP8 and MP12. Wiring CG1A can be electrically connected to all memory blocks (BLK) contained in storage planes MP8 and MP12. Wiring CG1B ( Figure 4Wiring CG0B can be electrically connected to all memory blocks BLK contained in storage planes MP9 and MP13. Wiring CG0C can be electrically connected to all memory blocks BLK contained in storage planes MP2 and MP6. Wiring CG1C can be electrically connected to all memory blocks BLK contained in storage planes MP10 and MP14. Wiring CG1D can be electrically connected to all memory blocks BLK contained in storage planes MP11 and MP15. Wiring CG0D can be electrically connected to all memory blocks BLK contained in storage planes MP3 and MP7.

[0071] For example, such as Figure 7 As illustrated, a wiring CG can contain n0 (n0 is a positive integer) + 1 wiring CGs. WS n1 (n1 is a positive integer) + 1 wiring CG WU 3 wiring CG SG and 1 wiring CG SRC Wiring CG WS For example, during read and write operations, it can be combined with the word line WL for selection. S The conductive wiring CGL or its nearby wiring CGL is conductive. Wiring CG WU For example, during read and write operations, it can be used with n0+1 non-select word lines WL. U Conductive. Additionally, wiring CG. WS and wiring CG WU For example, during the erase operation, the wiring CGL, which is connected to the WL line, can be connected. Wiring CG SG For example, during read, write, and erase operations, the drain-side select gate line SGD corresponding to the selected memory cell MC, multiple drain-side select gate lines SGD not corresponding to the selected memory cell MC, or the source-side select gate lines SGS and SGSb can be turned on. Wiring CG SRC For example, it can be connected to the source line SL during read, write, and erase operations.

[0072] Planar decoding component plnd( Figure 6 The planar decoding component plnd is configured to correspond to the memory cell array MCA. It has multiple transistors T. PLN The plurality of transistors T PLN With wiring CG ( Figure 6 In the example, this corresponds to the wiring CG1C. Transistor T PLN For example, a field-effect NMOS transistor.

[0073] transistor T PLN The drain electrode of transistor T is connected to the input terminal of the multiplexer MUX. PLN The source electrode is connected to the wiring CG ( Figure 6 In the example, this is wiring CG1C. Transistor T PLN The gate electrode is connected to the signal supply line PLNSEL. Multiple signal supply lines PLNSEL are provided corresponding to the planar decoding component plnd. Additionally, the signal supply lines PLNSEL are connected to all transistors T in the planar decoding component plnd. PLN .

[0074] For example, such as Figure 7 As shown, the equalizer EQ includes a node 201 and a plurality of transistors 202-205, 211, 212, 221-225, 231, 232, 241, 242, 251, and 252 electrically connected to the node 201. The plurality of transistors 202-205, 211, 212, 221-225, 231, 232, 241, 242, 251, and 252 are, for example, field-effect type NMOS transistors. Alternatively, for example, transistors 202-205, 212, 222-225, 232, 242, and 252 may also be, for example, enhancement-mode transistors. Additionally, for example, transistors 211, 221, 231, 241, and 251 may also be, for example, depletion-mode transistors.

[0075] Transistor 202 and n0+1 wiring CG WS A corresponding n0+1 configuration is set. The drain electrodes of transistor 202 are respectively connected to wiring CG. WS The source electrodes of transistor 202 are all connected to node 201. The gate electrodes of transistor 202 are connected to any one of the n0+1 signal lines G_CGEQ. The n0+1 signal lines G_CGEQ are electrically independent of each other.

[0076] Transistor 203 and n1+1 wiring CG WU A corresponding n1+1 configuration is set. The drain electrodes of transistor 203 are respectively connected to wiring CG. WU The source electrode of transistor 203 is commonly connected to node 201. The gate electrode of transistor 203 is commonly connected to a single signal line G_CGUEQ.

[0077] Transistor 204 and 3 wiring CG SG Three are configured accordingly. The drain electrodes of transistor 204 are respectively connected to wiring CG. SG The source electrode of transistor 204 is commonly connected to node 201. The gate electrode of transistor 204 is connected to any one of the three signal lines G_SGEQ. The three signal lines G_SGEQ are electrically independent of each other.

[0078] Transistor 205 and 1 wiring CG SRC One is configured accordingly. The drain electrode of transistor 205 is connected to wiring CG.SRC The source electrode of transistor 205 is connected to node 201. The gate electrode of transistor 205 is connected to signal line G_SRCEQ.

[0079] Transistors 211 and 212 are located at node 201 and pad electrode P. VCC On the current path between them. Bonding pad electrode P VCC It is a reference Figure 2 and Figure 3 This describes a portion of the multiple solder pad electrodes P. Regarding solder pad electrodes P... VCC Supply voltage V CC The gate electrodes of transistors 211 and 212 are respectively connected to signal line S. 11 S 12 .

[0080] Transistors 221 and 222 are located at node 201 and voltage supply line L VDD On the current path between them. The gate electrodes of transistors 221 and 222 are respectively connected to signal line S. 21 S 22 .

[0081] Transistors 221 and 223 are located at node 201 and pad electrode P VSS The current path 226 between them does not include transistors 224 and 225. Additionally, transistors 221, 224, and 225 are located between node 201 and the pad electrode P. VSS The current path 227 between them. Current path 227 does not include transistor 223. Pad electrode P VSS It is a reference Figure 2 and Figure 3 This describes a portion of the multiple solder pad electrodes P. Regarding solder pad electrodes P... VSS Supply ground voltage V SS (Power supply voltage). The gate electrodes of transistors 223, 224, and 225 are respectively connected to signal line S. 23 S 24 S REF .

[0082] Transistors 231 and 232 are located at node 201 and voltage supply line L VG1 On the current path between them. The gate electrodes of transistors 231 and 232 are respectively connected to signal line S. 31 S 32 .

[0083] Transistors 241 and 242 are located at node 201 and voltage supply line L VG2 On the current path between them. The gate electrodes of transistors 241 and 242 are respectively connected to signal line S. 41 S42 .

[0084] Transistors 251 and 252 are located at node 201 and voltage supply line L VG3 On the current path between them. The gate electrodes of transistors 251 and 252 are respectively connected to signal line S. 51 S 52 .

[0085] [Circuit configuration of the Sensing Amplifier Module (SAM)]

[0086] Sensing Amplifier Module SAM ( Figure 4 For example, it has multiple bit lines BL ( Figure 5 The system comprises multiple sense amplifier modules. Each sense amplifier module includes a sense circuit connected to the bit line BL, a voltage transmission circuit connected to the bit line BL, and a latch circuit connected to both the sense circuit and the voltage transmission circuit. The sense circuit includes a sense transistor that is switched on based on the voltage or current of the bit line BL, and a wiring that charges or discharges based on the on / off state of the sense transistor. The latch circuit latches "1" or "0" data based on the voltage of the wiring. The voltage transmission circuit connects the bit line BL to either of the two voltage supply lines based on the data latched in the latch circuit. The sense amplifier module SAM is connected to the sequencer SQC.

[0087] [Circuit configuration of the cache memory CM]

[0088] Cache memory CM ( Figure 4 It includes multiple latch circuits connected to the latch circuit within the sense amplifier module (SAM). The data contained in these multiple latch circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0089] Additionally, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address stored in the address register ADR. The switching circuit, based on the output signal of the decoding circuit, enables the latch circuit corresponding to the column address to be connected to the bus DB.

[0090] [Circuit configuration of the peripheral circuit PC]

[0091] For example, such as Figure 4 As shown, the peripheral circuit PC includes a driver module DRVM, a voltage generation circuit VG, and a sequencer SQC. Additionally, the peripheral circuit PC includes a register module RM. Furthermore, the peripheral circuit PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0092] The driver module DRVM may, for example, have eight driver components corresponding to wirings CG0A, CG1A, CG0B, CG1B, CG0C, CG1C, CG0D, and CG1D. These eight driver components, for example, connect wiring CG to any one of the voltage supply lines based on the input address signal and the control signal from the sequencer SQC. Furthermore, Figure 4 The example shown is the voltage supply line L. VDD L VG1 L VG2 L VG3 As a voltage supply line.

[0093] The voltage generation circuit VG, for example, includes multiple voltage generation components. These components generate voltages of a specific magnitude during read, write, and erase operations, and transmit these voltages via the voltage supply line L. VDD L VG1 L VG2 L VG3 Output. The voltage generating component can be, for example, a boost circuit such as a charge pump circuit, or a buck circuit such as a regulator. The buck circuit and boost circuit are respectively connected to the supply power voltage V. CC and grounding voltage V SS The voltage supply line. The voltage supply line is, for example, connected to a reference... Figure 2 , Figure 3 The pad electrode P is described.

[0094] The sequencer SQC outputs internal control signals to the memory module MM, driver module DRVM, and voltage generation circuit VG based on the instruction data stored in the instruction register CMR. Additionally, the sequencer SQC appropriately outputs status data indicating its own state to the status register STR.

[0095] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is essentially disabled. Conversely, during the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is enabled. Furthermore, the RY / / BY terminal is, for example, determined by a reference... Figure 2 , Figure 3 The pad electrode P described above is used to achieve this.

[0096] The register module RM includes, for example, the address register ADR which latches address data, the instruction register CMR which latches instruction data, and the status register STR which latches status data.

[0097] The input / output control circuit (I / O) includes data input / output terminals DQ0-DQ7, dual-state toggle signal input / output terminals DQS and / DQS, and comparators connected to the data input / output terminals DQ0-DQ7, as well as output circuits such as an OCD (Off-Chip Driver) circuit. Additionally, the I / O circuit includes shift registers and buffer circuits connected to the input and output circuits. The input circuit, output circuit, shift register, and buffer circuit are each connected to the supplied power supply voltage V. CCQ and grounding voltage V SS The terminals. Data input / output terminals DQ0~DQ7, dual-state thixotropic signal input / output terminals DQS, / DQS, and the supplied power supply voltage V. CCQ The terminals, for example, are referenced. Figure 2 , Figure 3 The pad electrode P is described above. Data input via data input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR based on internal control signals from the logic circuit CTR. Conversely, data output via data input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit based on internal control signals from the logic circuit CTR.

[0098] The logic circuit CTR receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O based on the external control signals. Furthermore, the external control terminals / CEn, CLE, ALE, / WE, / RE, RE are, for example, connected via a reference... Figure 2 , Figure 3 The pad electrode P described above is used to achieve this.

[0099] [Construction of Memory Die (MD)]

[0100] Figure 8 and Figure 9 This is a schematic top view of a memory die (MD). Figure 8 The wiring CG is schematically shown in the diagram. Figure 9 The voltage supply line L is schematically shown in the diagram. VG1 L VG2 L VG3 . Figure 10 It is Figure 8 A schematic top view shown in enlarged form. Figure 11 This is a schematic 3D diagram representing a portion of a memory die (MD). Figure 12 yes Figure 11A schematic enlarged view of part A shown.

[0101] like Figure 8 As shown, the memory die MD includes a semiconductor substrate 100. In the illustrated example, four columns are arranged along the X direction on the semiconductor substrate 100, each column containing four memory cell array regions R arranged along the Y direction. MCA Additionally, on one side from the X direction (e.g., Figure 8 Between the first and second columns (counting from the negative X-axis), the peripheral circuit area R is located. PC2 Similarly, the peripheral circuit region R is located between the 3rd and 4th columns counting from one side in the X direction. PC2 Additionally, a peripheral circuit region R is provided at the end of the semiconductor substrate 100 in the Y direction. PC1 .

[0102] [Structure of semiconductor substrate 100]

[0103] The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, for example, N-type well regions containing N-type impurities such as phosphorus (P), P-type well regions containing P-type impurities such as boron (B), semiconductor substrate regions without N-type and P-type well regions, and insulating regions are provided. The N-type well regions, P-type well regions, and semiconductor substrate regions function as part of multiple transistors and multiple capacitors constituting a peripheral circuit PC.

[0104] [Storage cell array region R] MCA [Construction]

[0105] In the illustrated example, the region R closest to the peripheral circuit is... PC1 The four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP0 to MP3. Additionally, it is located at a distance R from the surrounding circuit area. PC1 The second closest four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP4 through MP7. Additionally, it is located at a distance of R from the surrounding circuit area. PC1 The third and fourth closest memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP8 to MP11. Additionally, it is located at a distance R from the surrounding circuit area. PC1 The fourth nearest four memory cell array regions R MCAThe internal structure, starting from one side in the X direction, functions as part of storage planes MP12 to MP15.

[0106] like Figure 10 As shown, in the storage cell array region R MCA It sets up multiple storage blocks (BLKs) arranged along the X direction. For example, such as Figure 11 As shown, the memory block BLK includes a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120. In addition, an inter-block structure ST is provided between two adjacent memory blocks BLK in the X direction.

[0107] The conductive layer 110 is a generally plate-shaped conductive layer extending in the Y direction. The conductive layer 110 may comprise a barrier conductive film such as titanium nitride (TiN) or a laminated film of a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0108] A conductive layer 111 is disposed below the conductive layer 110. The conductive layer 111 may be, for example, a barrier conductive film such as titanium nitride (TiN) or a laminated film of a metal film such as tungsten (W). In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 111 and the conductive layer 110.

[0109] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 5 The gate electrodes of the plurality of source-side select transistors STSb connected to the source-side select gate line SGSb function. The conductive layer 111 is electrically independent in each memory block BLK.

[0110] Additionally, one or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 serve as the source-side selected gate line (SGS). Figure 5 The gate electrodes of the plurality of source-side select transistors STS connected to the source-side select gate line SGS function.

[0111] Additionally, multiple conductive layers 110 located above the conductive layer 110 serve as word lines WL ( Figure 5 ) and multiple memory cells MC connected to the word line WL Figure 5 The gate electrode of the ) functions. The plurality of conductive layers 110 are electrically independent in each memory block BLK.

[0112] Additionally, one or more conductive layers 110 located above the conductive layer 110 serve as drain-side selected gate lines (SGDs) and multiple drain-side selected transistors (STDs) connected to the drain-side selected gate lines (SGDs). Figure 5 The gate electrode of the ) functions. Between two adjacent conductive layers 110 in the X direction, an inter-string insulating layer SHE of silicon oxide (SiO2) or the like is disposed. The plurality of conductive layers 110 are respectively disposed in each string assembly SU( Figure 5 (Independent electrical properties)

[0113] Furthermore, at the Y-direction ends of the plurality of conductive layers 110, connection portions for multiple contacts CC are provided. The plurality of contacts CC extend in the Z-direction and are connected at their lower ends to the conductive layers 110. The contacts CC may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0114] Semiconductor pillars 120 are arranged in a specific pattern in the X and Y directions. Semiconductor pillars 120 serve as a memory string (MS). Figure 5 The semiconductor pillar 120 functions as a channel region of multiple memory cells (MC) and selection transistors (STD, STS, STSb) contained within it. The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has, for example, a generally bottomed cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. Furthermore, the outer peripheral surfaces of the semiconductor pillar 120 are each surrounded by a conductive layer 110, and the conductive layer 110 is oriented towards the semiconductor pillar 120.

[0115] At the upper end of the semiconductor pillar 120, an impurity region 121 containing N-type impurities such as phosphorus (P) is provided. The impurity region 121 is connected to the bit line BL extending in the X direction via contacts Ch and Cb.

[0116] The lower end of the semiconductor pillar 120 is connected to the P-type well region of the semiconductor substrate 100 via a semiconductor layer 122 comprising monocrystalline silicon (Si) or the like. The semiconductor layer 122 functions as a channel region for the source-side select transistor STSb. The outer peripheral surface of the semiconductor layer 122 is surrounded by a conductive layer 111 and faces the conductive layer 111. An insulating layer 123, such as silicon oxide, is disposed between the semiconductor layer 122 and the conductive layer 111.

[0117] The gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor pillar 120.

[0118] For example, such as Figure 12As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor pillar 120 in the Z direction.

[0119] also, Figure 12 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0120] For example, such as Figure 11 As shown, the inter-block structure ST includes a conductive layer 140 extending in the Z and Y directions, and an insulating layer 141 disposed on the X-direction side of the conductive layer 140. The conductive layer 140 is connected to an N-type impurity region disposed in the P-type well region of the semiconductor substrate 100. The conductive layer 140 may, for example, comprise a barrier conductive film such as titanium nitride (TiN) and a laminated film of a metal film such as tungsten (W). The conductive layer 140 serves, for example, as a source line SL ( Figure 5 It plays a part of the function.

[0121] [Storage cell array region R] MCA [Construction of areas other than]

[0122] like Figure 8 As shown, in the Y direction, it is related to each memory cell array region R MCA The line decoder region R is set at an adjacent position. RD In the line decoder region R RD Multiple block decoding components blkd are configured. Figure 6 ) and wiring CGL ( Figure 6 Additionally, in the X direction, it is related to each memory cell array region R. MCA The sensing amplifier module area R is located at an adjacent position. SAM In the sensing amplifier module region R SAM The sensor amplifier module SAM is set up. Figure 4 ).

[0123] In the peripheral circuit region R PC2 Multiple wirings are configured, arranged along the X direction and extending in the Y direction. For example, such as Figure 8 As shown, a portion of the plurality of wirings functions as part of the wiring CG. Additionally, for example, as... Figure 9As shown, a portion of the plurality of wirings serves as the voltage supply line L. VG1 L VG2 L VG3 Part of it performs its function. Additionally, in the X direction, it interacts with the surrounding circuit region R. PC2 Each memory cell array region R MCA The equalizer area R is set at an adjacent position. EQ In the equalizer region R EQ The equalizer (EQ) is set. Figure 6 Each equalizer region R EQ The equalizer (EQ) in the middle is connected to the voltage supply line L. VG1 L VG2 L VG3 .

[0124] In the peripheral circuit region R PC1 The driver module DRVM and voltage generation circuit VG are located here. Additionally, in the peripheral circuit area R... PC1 Multiple wirings are installed. For example, such as Figure 8 As shown, a portion of the plurality of wirings functions as part of the wiring CG. Additionally, for example, as... Figure 9 As shown, a portion of the plurality of wirings serves as the voltage supply line L. VG1 L VG2 L VG3 It plays a part of the function.

[0125] in addition, Figure 9 The example shown is related to the voltage supply line L. VG1 The corresponding voltage generation component vg1 and voltage supply line L VG2 The corresponding voltage generating component vg2 and voltage supply line L VG3 The corresponding voltage generation component vg3 is a component of the voltage generation circuit VG. For example, during a write operation, the voltage generation component vg1 generates the following programming voltage V. PGM And output it. Additionally, for example, during the erase operation, the following erase voltage V is generated. ERA And output it. The voltage generation component vg2, for example, generates the following read-through voltage V during the read operation. READ And then output it. Additionally, for example, during a write operation, the following write pass voltage V is generated. PASS and read the voltage V READ And output them. The voltage generation component vg3, for example, generates the following readout voltage V during the readout operation. CGR And output it. Additionally, the voltage generation component vg3, for example, generates the following verification voltage V during a write operation. VFY And output it.

[0126] In addition, voltage supply line L VG1 L VG2 L VG3 The wiring resistance of [the wire] is sufficiently small compared to the wiring resistance of [the wire] CG. Additionally, the voltage supply line L... VG1 L VG2 L VG3 The wiring width is greater than the wiring width of wiring CG. Additionally, the voltage supply line L... VG1 L VG2 L VG3 The number of lines is less than the number of lines in the CG wiring.

[0127] [Threshold voltage of memory cell MC]

[0128] Next, refer to Figure 13 The threshold voltage of the memory cell MC is explained.

[0129] Figure 13 (a) is a schematic histogram used to illustrate the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 13 (b) is a table showing an example of the relationship between the threshold voltage of the storage cell MC that records 3 bits of data and the recorded data. Figure 13 (c) is another example of the relationship between the threshold voltage of the storage cell MC that records 3 bits of data and the recorded data.

[0130] exist Figure 13 In example (a), the threshold voltage of the memory cell MC is controlled to eight states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Additionally, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA And less than the verification voltage V VFYB Additionally, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB And less than the verification voltage V VFYC Similarly, the threshold voltages of memory cells MC controlled in states C through F are respectively greater than the verification voltage V. VFYC ~Verification voltage V VFYF And less than the verification voltage V VFYD ~Verification voltage V VFYG Additionally, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG And less than the readout voltage V READ .

[0131] in addition, Figure 13In example (a), a readout voltage V is set between the threshold distribution corresponding to state Er and the threshold distribution corresponding to state A. CGAR Additionally, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBR Similarly, readout voltages V are set between the threshold distributions corresponding to state B and state C, and between the threshold distributions corresponding to state F and state G. CGBR ~Read the voltage V CGGR .

[0132] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erase state). The memory cell MC corresponding to the Er state is assigned, for example, the data "111".

[0133] Additionally, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er. For example, data "101" is assigned to the memory cell MC corresponding to state A.

[0134] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. The memory cell MC corresponding to state B is assigned, for example, the data "001".

[0135] Similarly, states C through G in the figure correspond to threshold voltages that are higher than those corresponding to states B through F. Data such as “011”, “010”, “110”, “100”, and “000” are assigned to the memory cells MC corresponding to the distribution.

[0136] In addition, when conducting Figure 13 (b) In the example of such an allocation, the data of the lower bit can be read using one readout voltage V. CGDR To determine the data of the median bit, it can be determined based on the three readout voltages V. CGAR V CGCR V CGFR To determine this, the data of the higher-order bit can be determined based on the three readout voltages V. CGBR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-3-3 encoding.

[0137] In addition, the number of bits, the number of states, and the data allocation corresponding to each state recorded in the storage unit MC can be changed appropriately.

[0138] For example, when conducting Figure 13 (c) In the example of such an allocation, the data of the lower bit can be read from one read voltage V. CGDRTo determine the data of the median bit, it can be determined based on the two readout voltages V. CGBR V CGFR To determine this, the data of the higher-order bit can be determined based on the four readout voltages V. CGAR V CGCR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-2-4 encoding.

[0139] [Read the action]

[0140] Next, the read operation of the semiconductor memory device in this embodiment will be described.

[0141] Figure 14 It is a schematic cross-sectional view used to illustrate the reading action. Figure 15 It is a timing diagram used to explain the reading action.

[0142] Furthermore, in this specification, the word line WL that will sometimes be the object of the action is referred to as the selection word line WL. S The word lines WL other than these are called non-selective word lines WL. U Additionally, in this specification, the multiple storage units MC contained in the string component SU, which are the objects of the action, are connected to the select word line WL. S The following explanation uses a connection memory cell MC (sometimes referred to as a "selection memory cell MC") to perform a read operation as an example. Additionally, in the following explanation, this configuration containing multiple selection memory cells MCs is sometimes referred to as a selection page PG.

[0143] At the time point t100 of the read-out action, for example, as Figure 15 As shown, the voltage at terminals RY / / BY is in the "L" state.

[0144] At the time point t101 of the readout action, select the word line WL. S and non-selective word line WL U Supply readout voltage V READ This turns all memory cells (MC) on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG Voltage V SG It has such a size that an electronic channel is formed in the channel region of the selection transistor (STD, STS, STSb), thereby causing the selection transistor (STD, STS, STSb) to be in the ON state.

[0145] At the time point t102 of the readout action, select the word line WL. S Supply a specific readout voltage V CGR Specific readout voltage VCGR It is a reference Figure 13 The reading voltage V is explained. CGAR ~V CGGR Any voltage in. Thus, for example, as Figure 14 As shown, some of the selected storage units (MCs) are in the ON state, while the remaining selected storage units (MCs) are in the OFF state.

[0146] Furthermore, at time t102, signal line S 51 S 52 The voltage rises from the "L" state to the "H" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path becomes conductive.

[0147] Additionally, at time t102, for example, the voltage V supplied to the bit line BL is... DD Additionally, for example, a voltage V is supplied to the source line SL. SRC Voltage V SRC For example, it has a ground voltage V SS The same magnitude. Voltage V SRC For example, it could also be slightly greater than the ground voltage V. SS And sufficiently smaller than voltage V DD The voltage.

[0148] At the time points t103 to t104 of the readout action, for example, Figure 15 As shown, a sensing action is performed to acquire data representing the state of the storage unit MC. The sensing action is performed, for example, through the sensing amplifier module SAM (…). Figure 4 This is used to detect the on / off state of the storage unit MC.

[0149] At the time point t105 of the readout action, select the word line WL. S Supply another readout voltage V CGR (Refer to Figure 13 The reading voltage V is explained. CGAR ~V CGGR (Any voltage in the system). As a result, some of the selected memory cells MC become on, and the remaining selected memory cells MC become off.

[0150] At the time points t106 to t107 of the readout action, for example, Figure 15 As shown, a sensing action is performed to obtain data representing the state of the storage unit MC.

[0151] At the time point t107 of the readout action, select the word line WL. S and non-selective word line WLU Supply readout voltage V READ This turns all memory cells (MC) on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG This turns the selector transistors (STD, STS, STSb) on.

[0152] Furthermore, at time t107, signal line S 51 S 52 The voltage drops from the "H" state to the "L" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path is cut off.

[0153] At the time point t108 of the readout action, select the word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0154] At the time point t109 of the readout action, the voltage at terminal RY / / BY becomes "H".

[0155] Furthermore, during the read operation, AND and OR operations are performed on the data representing the state of the storage unit MC to calculate the data recorded in the storage unit MC. This data is then transferred to the cache memory CM. Figure 4 )

[0156] [Write action]

[0157] Next, the write operation of the semiconductor memory device in this embodiment will be described.

[0158] Figure 16 It is a flowchart used to explain the write operation. Figure 17 It is a schematic cross-sectional view used to illustrate the programming actions contained in the write operation. Figure 18 It is a schematic cross-sectional view used to illustrate the verification actions contained in the write operation. Figure 19 It is a timing diagram used to illustrate the write operation.

[0159] Furthermore, the following explanation will use the example of performing a write operation on multiple selected memory cells MC corresponding to the selected page PG.

[0160] At the time point t120 of the write operation, for example, Figure 19 As shown, the voltage at terminals RY / / BY is in the "L" state.

[0161] In step S101, for example, as Figure 16 As shown, the number of iterations n W Set to 1. Number of loops n W This is a variable representing the number of times the loop is written. This action, for example, is in... Figure 19 The operation is performed at time t120. Additionally, for example, user data written to the storage unit MC is latched into the sense amplifier module SAM.

[0162] In step S102, a programming action is performed. The programming action involves selecting the word line WL. S The action of increasing the threshold voltage of the memory cell MC by supplying a programming voltage. This action, for example, occurs in... Figure 19 The execution will take place from time point t121 to time point t126.

[0163] At programming time point t121, for example, the bit line BL of the selection memory cell MC that is to be adjusted for threshold voltage among multiple selection memory cells MC. W Supply voltage V SRC For the bit line BL of the selection memory cell MC that is connected to multiple selection memory cells MC without threshold voltage adjustment P Supply voltage V DD Hereinafter, the memory cell MC that requires threshold voltage adjustment among multiple selectable memory cells is sometimes referred to as the "write memory cell MC", and the memory cell MC that does not require threshold voltage adjustment is referred to as the "disable memory cell MC".

[0164] At time t122 ​​of the programming action, select word line WL S and non-selective word line WL U Supply write through voltage V PASS Additionally, a gate line SGD supply voltage V is selected on the drain side. SGD Write through voltage V PASS It can have the same as the reference ( Figure 13 The reading is obtained through voltage V. READ The same magnitude can also be greater than the read voltage V. READ Voltage V SGD It has the following magnitude, that is, it is smaller than the reference. Figure 14 and Figure 15 The voltage V is explained SG Furthermore, the drain-side selection transistor STD is turned on or off based on the voltage of the bit line BL.

[0165] At time t124 of the programming action, select word line WL S Supply programming voltage V PGM Programming voltage VPGM Greater than the write pass voltage V PASS .

[0166] Here, for example, such as Figure 17 As shown, for the connection to bit line BL W The channel supply voltage V of the semiconductor pillar 120 SRC In such a semiconductor pillar 120 with select word line WL S A relatively large electric field is generated between them. As a result, electrons in the channels of semiconductor pillar 120 pass through tunnel insulating film 131 ( Figure 12 ) Penetrating the charge storage membrane 132 ( Figure 12 This leads to an increase in the threshold voltage for writing to the memory cell MC.

[0167] On the other hand, connected to bit line BL P The channel of the semiconductor pillar 120 becomes electrically floating, and the potential of this channel is controlled by the non-select word line WL. U The voltage rises to the write voltage V due to capacitive coupling. PASS Left and right. In such a semiconductor pillar 120 and select word line WL S Between them, only an electric field smaller than any of the aforementioned electric fields is generated. Therefore, electrons in the channels of semiconductor pillar 120 will not penetrate into charge storage film 132. Figure 12 Therefore, the threshold voltage of the memory cell MC will not increase.

[0168] Furthermore, at time t124, signal line S 31 S 32 The voltage rises from the "L" state to the "H" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG1 The current path becomes conductive.

[0169] At time t125 of the programming action, select word line WL. S and non-selective word line WL U Supply write through voltage V PASS .

[0170] Furthermore, at time t125, signal line S 31 S 32 The voltage drops from the "H" state to the "L" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG1 The current path is cut off.

[0171] At time t126 of the programming action, select word line WL S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0172] In step S103 ( Figure 16 In the process, the verification action is performed.

[0173] At the verification point t131, for example, as Figure 19 As shown, select word line WL S and non-selective word line WL U Supply readout voltage V READ This turns all memory cells (MC) on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG This turns the selector transistors (STD, STS, STSb) on.

[0174] At time t132 of the verification action, select word line WL. S Supply a specific verification voltage V VFY Specific verification voltage V VFY It is a reference Figure 13 The verification voltage V is explained. VFYA ~V VFYG Any voltage in. Thus, for example, as Figure 18 As shown, some of the selected storage units (MCs) are in the ON state, while the remaining selected storage units (MCs) are in the OFF state.

[0175] Furthermore, at time t132, signal line S 51 S 52 The voltage rises from the "L" state to the "H" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path becomes conductive.

[0176] Additionally, at time t132, for example, the voltage V supplied to the bit line BL is... DD At this time, for example, a voltage V can also be supplied to the bit line BL connected to the memory cell MC corresponding to a specific state. DD Supply voltage V to other bit lines BL SRC .

[0177] During the verification of actions at time points t133 to t134, for example, Figure 19 As shown, a sensing action is performed to obtain data representing the state of the storage unit MC.

[0178] During the verification actions from time points t137 to t139, the storage units MC in other states are processed in the same way as those from time points t132 to t134.

[0179] During the verification actions from time point t142 to time point t144, the storage units MC in other states are processed in the same way as those from time point t132 to time point t134.

[0180] At time t148 of the verification action, select word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0181] Furthermore, at time t148, signal line S 51 S 52 The voltage drops from the "H" state to the "L" state. Subsequently, the select word line WL... S The voltage generation circuit VG is connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path is cut off.

[0182] The acquired data is then transmitted to a counter circuit (not shown). The counter circuit counts the number of memory cells MC whose threshold voltage has reached the target value, or the number of memory cells MC whose threshold voltage has not yet reached the target value.

[0183] In addition, Figure 19 The example shows the selection word line WL during the verification action. S Supply three verification voltages V VFY Examples. However, in the verification action, the selection word line WL... S The supplied verification voltage V VFY The number of types can be 2 or less, or 4 or more, and can also be determined based on the number of loops n. W And change.

[0184] In step S104 ( Figure 16 In step S105, the result of the verification action is determined. For example, referring to the counter circuit, if the number of memory cells MC whose threshold voltage has not reached the target value is above a fixed number, the verification is determined to be FAIL, and the process proceeds to step S107. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is below a fixed number, the verification is determined to be PASS, and the process proceeds to step S107.

[0185] In step S105, the number of iterations n is determined. W Has a specific number N been reached?W When the specified number N is not reached. W When the specified number of times N has been reached, proceed to step S106. W Then proceed to step S108.

[0186] In step S106, the number of iterations n W Add 1, proceed to step S102. Additionally, in step S106, for example, the programming voltage V... PGM A specific voltage ΔV is applied. Therefore, the programmed voltage V is... PGM As the number of loops n W It increases with the increase of .

[0187] In step S107, the status data indicating that the write operation has been completed normally is stored in the status register STR. Figure 4 The write operation ends. Additionally, the status data is output to the controller's bare die CD via a status read operation. Figure 1 ).

[0188] In step S108, the status data indicating that the write operation has not ended properly is stored in the status register STR. Figure 4 In the ), the write operation ends.

[0189] [Erase action]

[0190] Next, the erasure operation of the semiconductor memory device in this embodiment will be described.

[0191] Figure 20 It is a flowchart used to explain the erasure action. Figure 21 It is a schematic cross-sectional view used to illustrate the erase voltage supply operation included in the erase operation. Figure 22 It is a schematic cross-sectional view used to illustrate the erasure verification action included in the erasure action. Figure 23 It is a timing diagram used to illustrate the erasure action.

[0192] Furthermore, the following explanation will use the example of performing an erase operation on the storage block BLK that becomes the action object.

[0193] At the time point t156 of the erasure action, for example, as Figure 23 As shown, the voltage at terminals RY / / BY is in the "L" state.

[0194] In step S201, for example, as Figure 20 As shown, the number of iterations n E Set to 1. Number of loops n E This is a variable representing the number of times the erase loop has been executed. This action, for example, occurs in... Figure 23 The execution will take place at time t156.

[0195] In step S202, the erase voltage supply operation is performed. The erase voltage supply operation is as follows: a ground voltage V is supplied to the word line WL. SS An erase voltage is supplied to at least one of the source line SL and the bit line BL to reduce the threshold voltage of the memory cell MC. This action is, for example, in... Figure 23 The execution will take place from time point t161 to time point t162.

[0196] At the moment t161 when the voltage supply is removed, for example, when the ground voltage V is supplied to the word line WL. SS Additionally, a gate line SGD supply voltage V is selected on the drain side. SG ', Select gate line SGS supply voltage V to the source side SG Voltage V SG 'It has the magnitude to which it turns the drain-side select transistor STD off. Voltage V' SG "It has such a degree that a hole channel is formed in the channel region of the source-side select transistor STS, thereby making the source-side select transistor STS turn on."

[0197] Additionally, at the time t161 of the erase voltage supply operation, an erase voltage V is supplied to the source line SL. ERA Erasure voltage V ERA Greater than the write pass voltage V PASS Erasure voltage V ERA For example, it could be related to the programming voltage V. PGM The same magnitude can also be greater than the programming voltage V. PGM .

[0198] Here, for example, such as Figure 21 As shown, a ground voltage V is supplied to the word line WL. SS The erase voltage V is supplied to the channel of semiconductor pillar 120 via the source line SL. ERA Therefore, a relatively large electric field is generated between the semiconductor pillar 120 and the word line WL. Consequently, the charge storage film 132 ( Figure 12 Electrons in the tunnel insulating membrane 131 ( Figure 12 It penetrates into the channel of semiconductor pillar 120. As a result, the threshold voltage of the memory cell MC decreases.

[0199] Furthermore, at time t161, signal line S 31 S 32 The voltage rises from the "L" state to the "H" state. Subsequently, the source line SL and the voltage generation circuit VG are connected via node 201 ( Figure 7 ) and voltage supply line L VG1 The current path becomes conductive.

[0200] At the time t162 of the voltage supply cutoff operation, a voltage V is supplied to the source line SL. SRC .

[0201] Furthermore, at time t162, signal line S 31 S 32 The voltage drops from the "H" state to the "L" state. Subsequently, the source line SL and the voltage generation circuit VG are connected via node 201 ( Figure 7 ) and voltage supply line L VG1 The current path is cut off.

[0202] In step S203 ( Figure 20 In the process, the verification process is erased.

[0203] At the time point t163 of the verification action being erased, for example, as Figure 22 As shown, the erase verification voltage V is supplied to the word line WL. VFYEr Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG This turns the selector transistors (STD, STS, STSb) on.

[0204] Furthermore, at time t163, signal line S 51 S 52 The voltage rises from the "L" state to the "H" state. Subsequently, the word line WL and the voltage generation circuit VG are connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path becomes conductive.

[0205] Additionally, at time t163, for example, bit line BL is charged. At this time, for example, a voltage V is supplied to at least a portion of bit line BL. DD Alternatively, a voltage V can be supplied to a portion of the bit lines BL. SRC .

[0206] Additionally, at time points t163 to t164 during the erasure verification action, a sensing action is performed to obtain data representing the state of the storage unit MC.

[0207] At the time t164 of the erase verification operation, a ground voltage V is supplied to the word line WL and the select gate lines (SGD, SGS, SGSb). SS .

[0208] Furthermore, at time t164, signal line S 51 S 52 The voltage drops from the "H" state to the "L" state. Subsequently, the word line WL and the voltage generation circuit VG are connected via node 201 ( Figure 7 ) and voltage supply line L VG3 The current path is cut off.

[0209] The acquired data is then transmitted to a counter circuit (not shown). The counter circuit counts the number of memory cells MC whose threshold voltage has reached the target value, or the number of memory cells MC whose threshold voltage has not yet reached the target value.

[0210] In step S204 ( Figure 20 In step S205, the result of the erase verification operation is determined. For example, referring to the counter circuit, if the number of memory cells MC whose threshold voltage has not reached the target value is above a fixed number, the verification is determined to be FAIL, and the process proceeds to step S205. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is below a fixed number, the verification is determined to be PASS, and the process proceeds to step S207.

[0211] In step S205, the number of iterations n is determined. E Has a specific number N been reached? E Before reaching a specific number N. E Proceed to step S206. After reaching a specific number N... E Proceed to step S208.

[0212] In step S206, the number of iterations n E Add 1, proceed to step S202. Additionally, in step S206, for example, the erase voltage V... ERA A specific voltage ΔV is applied. Therefore, the erasure voltage V is... ERA As the number of loops n E It increases with the increase of .

[0213] In step S207, the status data indicating that the erasure operation has been completed normally is stored in the status register STR. Figure 4 The erasure operation ends in the controller's CD. Additionally, the status data is output to the controller's CD via a status read operation. Figure 1 ).

[0214] In step S208, the status data indicating that the erasure operation has not ended properly is stored in the status register STR. Figure 4 In the process of erasing, the erasure action ends.

[0215] [Comparative Example]

[0216] Next, refer to Figures 24-26 The comparative example semiconductor memory device will be described. Figure 24 This is a schematic top view of the memory die MD' of the comparative example. Figure 25 and Figure 26 This is a schematic circuit diagram representing a portion of a memory die MD'.

[0217] like Figure 24 As illustrated, in the memory die MD', the voltage supply line L VG1 L VG2 L VG3 Only set in the peripheral circuit area R PC1 Within the range, but not set in the surrounding circuit area R PC2 .

[0218] like Figure 25 As illustrated, the memory die MD' has an equalizer EQ' but not an equalizer EQ. The equalizer EQ' is not set on the current path between the word line WL and the voltage generation circuit VG.

[0219] like Figure 26 As illustrated, the equalizer EQ' does not have the features shown in the reference. Figure 7 The transistors described are 224, 225, 231, 232, 241, 242, 251, and 252.

[0220] During the read operation of the memory die MD', the select word line WL is selected via the current path including the wiring CG and the driver module DRVM. S Supply readout voltage V CGR .

[0221] During the programming operation of the memory die MD', the select word line WL is selected via the current path including the wiring CG and the driver module DRVM. S Supply programming voltage V PGM .

[0222] During the verification process of the memory die MD', the select word line WL is selected via the current path that includes the wiring CG and the driver module DRVM. S Supply verification voltage V VFY .

[0223] [Action Speed]

[0224] like Figure 24 As illustrated, the memory die MD' has an array region R with 16 memory cells. MCA The corresponding 16-cell memory array (MCA). In Figure 24In the example, storage plane MP2 is positioned relatively close to the driver module DRVM. Therefore, the wiring resistance in the wiring CG between storage plane MP2 and driver module DRVM is relatively small. On the other hand, storage plane MP15 is positioned relatively far from the driver module DRVM. Therefore, the wiring resistance in the wiring CG between storage plane MP15 and driver module DRVM is relatively large.

[0225] Here, for example, when performing a read operation, programming operation, verification operation, erase voltage supply operation, or erase verification operation (hereinafter referred to as "read operation, etc.") on the storage plane MP2, the selection word line WL is selected from the beginning. S Word line WL or source line SL (hereinafter referred to as "select word line WL") S (etc.) supply readout voltage V CGR Verify voltage V VFY Programming voltage V PGM ,Eraser voltage V ERA Or erase the verification voltage V VFYEr (Hereinafter referred to as "readout voltage V") CGR Waiting) to select word line WL S The voltage converges to the readout voltage V. CGR The waiting time is relatively short. On the other hand, when performing read operations on the storage plane MP15, the time from the start of selecting the word line WL... S Wait for the supply of readout voltage V CGR Wait until you select the word line WL S The voltage converges to the readout voltage V. CGR The waiting time is relatively long.

[0226] Furthermore, in the memory die MD', read operations are sometimes performed simultaneously or in parallel on multiple memory planes MP. Here, for example, when performing a read operation on one memory plane MP, the voltage drop in the wiring CG is relatively small because the current flowing through it is relatively small. Therefore, from the start of the select word line WL... S Wait for the supply of readout voltage V CGR Wait until you select the word line WL S The voltage converges to the readout voltage V. CGR The waiting time is relatively short. On the other hand, when performing read operations on multiple memory planes (MP), the voltage drop in the wiring CG is relatively large because the current flowing through it is relatively large. Therefore, from the start of selecting the word line WL... S Wait for the supply of readout voltage V CGR Wait until you select the word line WL S The voltage converges to the readout voltage V. CGR The waiting time is relatively long.

[0227] Here, in order to properly perform read operations and other actions regardless of the location and number of the selected storage planes MP, it is advisable to ensure that the timing and other conditions in the read operations meet the latest possible conditions. However, in this case, it can sometimes be difficult to achieve high-speed operation.

[0228] Here, in the memory die MD of the first embodiment, as referred to Figure 9 As explained, in the X direction, it is related to the surrounding circuit region R. PC2 Each memory cell array region R MCA The equalizer area R is set at an adjacent position. EQ Additionally, the voltage supply line L VG1 L VG2 L VG3 Reaching each equalizer region R EQ via each equalizer region R EQ The equalizer (EQ) is electrically connected to the R region located in each memory cell array area. MCA MCA (Multi-Cell Array) storage cell array.

[0229] Here, as described above, the voltage supply line L VG1 L VG2 L VG3 The wiring resistance of the CG is sufficiently small compared to the wiring resistance of the CG. Therefore, the wiring resistance of the current path between the storage plane MP and the voltage generation circuit VG, including the equalizer EQ, is sufficiently small compared to the wiring resistance of the current path including the CG and the driver module DRVM. Therefore, the current path from the voltage generation circuit VG to the select word line WL via the equalizer EQ is sufficiently small. S By ensuring a constant supply voltage, the operating speed difference caused by variations in the location and number of the selected memory planes (MPs) can be reduced. This enables the provision of a high-speed semiconductor memory device.

[0230] [Faulty operation accompanied by leakage current]

[0231] As mentioned above, in a memory die MD', read operations are sometimes performed simultaneously or in parallel on multiple memory planes MP. Here, when multiple memory blocks BLK selected as targets for read operations contain bad blocks, it can sometimes prevent even operations on normal memory blocks BLK from being performed correctly. For example, when two adjacent word lines WL in the Z direction are short-circuited, and one of the word lines is the selected word line WL... S Sometimes, it is not possible to properly control the select word line WL. S The voltage. In this case, it will cause a voltage issue with the select word line WL. SThe voltage of the corresponding wiring CG changes, connecting to the select word line WL corresponding to other memory planes MP. S The voltage also cannot be properly controlled.

[0232] Here, as described above, the voltage supply line L VG1 L VG2 L VG3 The wiring resistance of the line L is sufficiently small compared to that of the wiring CG. Therefore, even if multiple memory blocks BLK selected for read operations, etc., contain defective blocks as described above, the voltage supply line L... VG1 L VG2 L VG3 The voltage fluctuations described above will not occur in the circuit. Therefore, the effects of leakage current as described above on the normal circuit can be appropriately suppressed.

[0233] [Other Action Methods]

[0234] Reference Figures 14-23 The described actions are merely illustrative; the specific execution methods for actions such as reading them out can be adjusted accordingly. The following is for reference only. Figures 27-29 Examples of other methods for executing the read-out action.

[0235] Figure 27 The illustrated readout action is basically the same as the reference. Figure 15 The readout action described is performed in the same way.

[0236] but, Figure 15 In the example, at time t102, the signal line S is... 51 S 52 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With voltage supply line L VG3 Conduction.

[0237] on the other hand, Figure 27 In the example, at time t202, the signal line S is made 24 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With solder pad electrode P VSS Conduction.

[0238] Additionally, at time t203, the signal line S is... 24 The voltage drops from the "H" state to the "L" state, thereby causing the select word line WL to... S With solder pad electrode P VSS Electrolysis.

[0239] Additionally, at time t203, the signal line S is... 51 S 52The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With voltage supply line L VG3 Conduction.

[0240] Figure 28 The illustrated readout action is basically the same as the reference. Figure 15 The readout action described is performed in the same way.

[0241] but, Figure 15 In the example, during the readout action, multiple readout voltages V CGR They are supplied to the select word line WL in ascending order. S .on the other hand, Figure 28 In the example, multiple readout voltages V CGR They are supplied to the select word line WL in descending order of size. S .

[0242] Figure 29 The illustrated readout action is basically the same as the reference. Figure 28 The readout action described is performed in the same way.

[0243] but, Figure 28 In the example, at time t102, the signal line S is... 51 S 52 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With voltage supply line L VG3 Conduction.

[0244] on the other hand, Figure 29 In the example, at time t212, the signal line S is... 24 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With solder pad electrode P VSS Conduction.

[0245] Additionally, at time t213, make signal line S 24 The voltage drops from the "H" state to the "L" state, thereby causing the select word line WL to... S With solder pad electrode P VSS Electrolysis.

[0246] Additionally, at time t213, make signal line S 51 S 52 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With voltage supply line L VG3 Conduction.

[0247] in addition, Figure 28In the example, at time t105, the signal line S 51 S 52 The voltage is maintained in the "H" state, switching the supply to the voltage supply line L. VG3 The voltage.

[0248] on the other hand, Figure 29 In the example, at time t215, the signal line S is... 51 S 52 The voltage drops from the "H" state to the "L" state, thereby causing the select word line WL to... S With voltage supply line L VG3 Electrolysis.

[0249] Additionally, at time t215, make signal line S 24 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With solder pad electrode P VSS Conduction.

[0250] Additionally, at time t216, make signal line S 24 The voltage drops from the "H" state to the "L" state, thereby causing the select word line WL to... S With solder pad electrode P VSS Electrolysis.

[0251] Additionally, at time t216, make signal line S 51 S 52 The voltage rises from the "L" state to the "H" state, thereby enabling the select word line WL. S With voltage supply line L VG3 Conduction.

[0252] Figure 27 and Figure 29 In the example, when selecting the word line WL S During discharge, the select word line WL is activated. S Primary electrode with solder pad P VSS Turn on. Therefore, there exists a way to enable the select word line WL. S The voltage converges to the required voltage more quickly.

[0253] Here, for example, when such an operation is performed in the memory die MD', the select word line WL is executed via wiring CG and driver module DRVM. S The discharge process can be challenging. In such operations, the discharge time can vary depending on the location and number of storage planes (MPs) selected, sometimes due to the influence of the wiring resistance in the CG. Suppressing this phenomenon can make it difficult to achieve high-speed operation.

[0254] Here, in Figure 27 and Figure 29 In the example, the word line WL is selected via an equalizer (EQ). S The discharge. According to this method, regardless of the location and number of the selected memory planes MP, the select word line WL can be made to discharge. S The voltage converges rapidly to the required voltage.

[0255] also, Figure 27 and Figure 29 In the example, via Figure 7 The illustrated current path 227 is used to select the word line WL. S The discharge. At this time, by adjusting the signal line S REF The voltage can be adjusted appropriately to control the discharge rate.

[0256] In addition, such as Figures 27-29 The illustrated actions apply not only to read operations but also to verification and erase verification operations. Furthermore, current path 227 can also be used during programming operations, verification operations, erase voltage supply operations, or erase verification operations.

[0257] Additionally, in the above explanation, the selection word line WL is mentioned during both read and write operations. S Supply readout voltage V CGR An example of charging and discharging via an equalizer (EQ) was illustrated. However, for example, in the case of non-selected word line WL... U Supply readout voltage V READ Write through voltage V PASS or ground voltage V SS At the same time, charging and discharging can also be performed via the equalizer (EQ).

[0258] [Other Implementation Methods]

[0259] The semiconductor memory device according to the first embodiment has been described above. However, these semiconductor memory devices are merely examples, and the specific configuration, operation, etc., can be adjusted appropriately.

[0260] For example, Figure 4 In the example, the memory die MD has two plane groups PG0 and PG1. Furthermore, each of the two plane groups PG0 and PG1 has eight memory planes MP. However, the number of plane groups in the memory die MD can be adjusted appropriately. Additionally, the number of memory planes MP contained within each plane group can be adjusted appropriately.

[0261] in addition, Figure 4In the example, eight types of wiring CGs (CG0A, CG1A, CG0B, CG1B, CG0C, CG1C, CG0D, and CG1D) are used as wiring CGs. Furthermore, wirings CG0A, CG1A, CG0B, CG1B, CG0C, CG1C, CG0D, and CG1D are each connected to two memory planes (MP). However, the number of wiring CG types can be adjusted appropriately. Additionally, the number of memory planes (MP) connected to the wiring CGs can be adjusted appropriately.

[0262] in addition, Figure 7 In the example, it is used to connect each memory plane MP to the voltage supply line L without going through the wiring CG and driver module DRVM. VG1 L VG2 L VG3 The connected circuit uses an equalizer (EQ). However, this circuit can also be set up separately from the equalizer (EQ).

[0263] Furthermore, regardless of whether an equalizer (EQ) is used, the number of such circuits can be the same as or less than the number of storage planes (MPs). For example, such circuits can be configured to correspond to two or more storage planes (MPs) arranged along the X or Y direction, and be shared by the two or more storage planes (MPs). Alternatively, they can be configured to correspond to four or more storage planes (MPs) arranged along both the X and Y directions, and be shared by the four or more storage planes (MPs). For example, Figure 6 In the example, the number of equalizers (EQ) is the same as the number of storage planes (MP). Therefore, for example, as... Figure 4 When 16 memory planes are set on the memory die MD, 16 equalizers (EQs) are set on the memory die MD. On the other hand, Figure 30 In the example, the number of equalizers (EQs) is the same as the number of cabling CGs. For example, as... Figure 4 When eight wiring schemes (CG0A, CG1A, CG0B, CG1B, CG0C, CG1C, CG0D, CG1D) are configured on the memory die MD, eight equalizers (EQ) are configured on the memory die MD. In this case, the equalizers (EQ) are configured corresponding to two memory planes (MP) arranged along the Y direction and are shared by the two memory planes (MP).

[0264] in addition, Figure 7 In this example, node 201 is connected to all voltage supply lines L. VG1 L VG2 L VG3 However, node 201 only needs to be connected to the voltage supply line L. VG1 L VG2 L VG3 At least one of them is required. Alternatively, the voltage supply line L can be connected at node 201. VG1L VG2 L VG3 Other voltage supply lines.

[0265] in addition, Figures 8-12 The configurations and structures shown are for illustrative purposes only; specific configurations can be adjusted accordingly. For example, Figure 11 In this example, the lower ends of the plurality of semiconductor pillars 120 are connected to the semiconductor substrate 100 via a semiconductor layer 122. However, a source line SL can also be provided between the semiconductor pillars 120 and the semiconductor substrate 100. Figure 5 This is a semiconductor layer that performs its function. Alternatively, wiring may be provided between this semiconductor layer and the semiconductor substrate 100. Furthermore, for example, the memory module MM and the peripheral circuit PC may be formed as separate chips, and a single memory die may be fabricated by bonding these two chips together.

[0266] [other]

[0267] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the invention as described in the claims and its equivalents.

[0268] [Explanation of Symbols]

[0269] MC storage unit

[0270] MCA storage cell array

[0271] PC peripheral circuits

[0272] P pad electrode.

Claims

1. A semiconductor memory device comprising: An array of multiple storage cells, including a first storage cell and a first word line connected to the first storage cell; The first wiring is electrically connected to the plurality of first word lines corresponding to the plurality of memory cell arrays; The drive circuit is electrically connected to the first wiring. Multiple second wirings are electrically connected to the first wiring via the drive circuit; The voltage generating circuit has a plurality of output terminals disposed corresponding to the plurality of second wirings; as well as Multiple first circuits are configured corresponding to the multiple memory cell arrays; The voltage generating circuit Electrically connected to the plurality of first word lines via a first current path including the plurality of second wirings, the drive circuit, and the first wirings, and Electrically connected to the plurality of first word lines via a second current path comprising the plurality of second wirings and the plurality of first circuits but excluding the drive circuit.

2. The semiconductor memory device according to claim 1, wherein The first storage cell array, which is one of the plurality of storage cell arrays, includes: Multiple storage units, including the first storage unit; and Multiple character lines, including the first character line; and The plurality of word lines are electrically connected to the plurality of second wirings via one of the plurality of first circuits.

3. The semiconductor memory device according to claim 2, wherein... One of the plurality of first circuits includes: The first node is electrically connected to the plurality of word lines and the plurality of second wirings; A plurality of first transistors are disposed on a plurality of current paths between the first node and the plurality of word lines; and Multiple second transistors are disposed on multiple current paths between the first node and the multiple second wirings.

4. The semiconductor memory device according to claim 3, further comprising bonding pad electrodes supplied with a first power supply voltage. At least one of the plurality of first circuits includes: A third transistor is disposed on a third current path between the first node and the pad electrode; and The fourth and fifth transistors are disposed on the fourth current path between the first node and the pad electrode.

5. The semiconductor memory device according to claim 3, wherein The voltage generating circuit includes: The first voltage generating component outputs the first voltage; The second voltage generating component outputs a second voltage that is smaller than the first voltage; and The third voltage generating component outputs a third voltage that is smaller than the second voltage.

6. The semiconductor memory device according to claim 5, wherein During the readout operation, a voltage is supplied to the gate electrode of the second transistor, which is electrically connected to the third voltage generating component, to turn on the second transistor.

7. The semiconductor memory device according to claim 5, wherein During programming, a voltage is supplied to the gate electrode of the second transistor, which is electrically connected to the first voltage generating component, to turn on the second transistor.

8. The semiconductor memory device according to claim 5, wherein During the verification operation, a voltage is supplied to the gate electrode of the second transistor that is electrically connected to the third voltage generating component, thereby turning the second transistor on.

9. The semiconductor memory device according to claim 5, wherein During the voltage supply erasure operation, a voltage is supplied to the gate electrode of the second transistor, which is electrically connected to the first voltage generating component, to turn on the second transistor.

10. The semiconductor memory device according to claim 5, wherein During the erase verification operation, a voltage is supplied to the gate electrode of the second transistor that is electrically connected to the third voltage generating component, in order to turn on the second transistor.

11. The semiconductor memory device according to any one of claims 1 to 10, wherein The plurality of first circuits are respectively configured to correspond to one of the memory cell arrays.

12. The semiconductor memory device according to any one of claims 1 to 10, wherein The plurality of first circuits are respectively configured to correspond to two or more of the memory cell arrays.

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