Semiconductor element with horizontally configured capacitor and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method for manufacturing the same. The semiconductor element has a first palm portion disposed on a substrate, a second palm portion disposed on the substrate and located opposite the first palm portion, a first finger portion disposed substantially parallel to a main surface of the substrate, and located between the first palm portion and the second palm portion and connected to the first palm portion, a second finger portion disposed substantially parallel to the first finger portion, and located between the first palm portion and the second palm portion and connected to the second palm portion, a capacitor isolation layer disposed between the first finger portion and the second finger portion, a first gap sub disposed between the first palm portion and the second finger portion, and a second gap sub disposed between the second palm portion and the first finger portion.

Description

[0001] Cross-references

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 352,681, filed June 21, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having horizontally configured capacitors and a method for fabricating the same. Background Technology

[0004] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, the challenge of improving quality, yield, performance, and reliability, while reducing complexity, continues.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device, comprising: a first palm portion disposed on a substrate; a second palm portion disposed on the substrate and located opposite to the first palm portion; a first finger portion disposed substantially parallel to a main surface of the substrate and located between the first palm portion and the second palm portion, and connected to the first palm portion; a second finger portion disposed substantially parallel to the first finger portion and located between the first palm portion and the second palm portion, and connected to the second palm portion; a capacitor isolation layer disposed between the first finger portion and the second finger portion; a first spacer disposed between the first palm portion and the second finger portion; and a second spacer disposed between the second palm portion and the first finger portion.

[0007] In some embodiments, the semiconductor element includes a conductive layer disposed generally parallel to the second finger portion and located between the first palm portion and the second palm portion, and connected to the first palm portion.

[0008] In some embodiments, the semiconductor element further includes a third spacer disposed between the lower conductive layer and the second palm portion.

[0009] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the first palm portion is disposed on and contacts the impurity region.

[0010] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the second palm portion is disposed on and contacts the impurity region.

[0011] In some embodiments, the semiconductor element further includes a termination layer disposed generally parallel to the capacitor isolation layer and between the second finger portion and the lower conductive layer.

[0012] In some embodiments, the semiconductor element further includes a conductive layer disposed substantially parallel to the second finger portion and located between the first palm portion and the second palm portion, and connected to the second palm portion.

[0013] In some embodiments, the semiconductor element further includes a third spacer disposed between the lower conductive layer and the first palm portion.

[0014] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the first palm portion is disposed on and contacts the impurity region.

[0015] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the second palm portion is disposed on and contacts the impurity region.

[0016] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the first palm portion is electrically connected to the impurity region via a conductive layer.

[0017] In some embodiments, the semiconductor device further includes an impurity region disposed in the substrate; wherein the second palm portion is electrically connected to the impurity region via a conductive layer.

[0018] In some embodiments, the semiconductor device further includes a buried isolation layer disposed in the substrate; wherein the impurity region is disposed on the buried isolation layer.

[0019] In some embodiments, the thickness of the first finger portion is different from the thickness of the second finger portion.

[0020] In some embodiments, the width of the first finger portion is different from the width of the second finger portion.

[0021] In some embodiments, the width of the first gap is different from the width of the second gap.

[0022] In some embodiments, the thickness of the lower conductive layer is different from the thickness of the second finger portion.

[0023] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; sequentially forming a first conductive layer, an isolation layer, and a second conductive layer, configured as a stack on the substrate; patterning the stack to form a first recess and expose an impurity region in the substrate; forming a first spacer to cover a sidewall of the first conductive layer; forming a first palm portion in the first recess and connected to the second conductive layer; patterning the stack to form a third recess, transforming the second conductive layer into a first finger portion and the first conductive layer into a second finger portion, wherein the third recess is formed opposite to the first palm portion; forming a second spacer to cover a sidewall of the first finger portion, wherein the second spacer is formed opposite to the first palm portion; and forming a second palm portion in the third recess and connected to the second finger portion.

[0024] In some embodiments, the preparation method further includes: forming a conductive layer disposed substantially parallel to a main surface of the substrate and connected to the first palm portion.

[0025] In some embodiments, the lower conductive layer comprises the same material as the second finger portion.

[0026] The semiconductor device design disclosed herein can increase the contact area of ​​the capacitor structure. Therefore, the performance of the semiconductor device can be improved. Furthermore, the manufacturing process can be easily integrated with fin-type transistors.

[0027] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0028] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0030] Figures 2 to 14This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0031] Figures 15 to 18 This is a cross-sectional schematic diagram illustrating various semiconductor elements according to an embodiment of the present disclosure.

[0032] Figures 19 to 22 This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0033] Figures 23 to 27 This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0034] Figure 28 This is a cross-sectional schematic diagram illustrating a semiconductor element according to an embodiment of the present disclosure.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1A: Semiconductor components

[0037] 1B: Semiconductor components

[0038] 1C: Semiconductor components

[0039] 1D: Semiconductor components

[0040] 1E: Semiconductor components

[0041] 1F: Semiconductor components

[0042] 1G: Semiconductor components

[0043] 1H: Semiconductor components

[0044] 10: Preparation method

[0045] 101: Base

[0046] 103: Impurity Zone

[0047] 105: Lower conductive layer

[0048] 107: Termination Layer

[0049] 109: Interlayer dielectric layer

[0050] 111: Embedding the isolation layer

[0051] 211: First palm part

[0052] 213: First finger part

[0053] 215: First finger part

[0054] 221: Second palm part

[0055] 223: Second finger part

[0056] 225: Second finger part

[0057] 231: Capacitor isolation layer

[0058] 233: Capacitor isolation layer

[0059] 235: Capacitor isolation layer

[0060] 241: First gap

[0061] 241D: Dent

[0062] 243: Second gap

[0063] 243D: Dent

[0064] 245: Third gap

[0065] 401: First conductive layer

[0066] 403: Second conductive layer

[0067] 405: Isolation layer

[0068] 407: First masking layer

[0069] 409: First Dielectric Material

[0070] 411: Second masking layer

[0071] 413: Second dielectric material

[0072] 415: Sacrificial Layer

[0073] 417: Sacrificial Layer

[0074] R1: First depression

[0075] R2: Second depression

[0076] R3: Third depression

[0077] R4: Fourth Depression

[0078] S11: Steps

[0079] S13: Steps

[0080] S15: Steps

[0081] S17: Steps

[0082] S19: Steps

[0083] S21: Steps

[0084] S23: Steps

[0085] S25: Steps

[0086] T1: Thickness

[0087] T2: Thickness

[0088] T3: Thickness

[0089] T4: Thickness

[0090] T5: Thickness

[0091] W1: Width

[0092] W2: Width

[0093] W3: Width

[0094] W4: Width

[0095] W5: Width

[0096] W6: Width

[0097] W7: Width

[0098] Z: Direction Detailed Implementation

[0099] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0100] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0101] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0102] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0103] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term “substantially” may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0104] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0105] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0106] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 14 This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device 1A according to an embodiment of the present disclosure.

[0107] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0108] It should be understood that the functions or steps mentioned in this disclosure may occur in a different order than that shown in the accompanying drawings. For example, two drawings shown consecutively may actually be performed substantially simultaneously, or sometimes in reverse order, depending on the functions or steps included.

[0109] Please refer to Figures 1 to 3 In step S11, a substrate 101 may be provided, an impurity region 103 may be formed in the substrate 101, and a conductive layer 105 may be formed on the substrate 101.

[0110] Please refer to Figure 2 The substrate 101 may be a bulk semiconductor substrate, a multilayer or gradient substrate, or the like. The substrate 101 may include a semiconductor material, such as an elemental semiconductor, a compound or alloy semiconductor, or a combination thereof. Elemental semiconductors include Si and Ge, and compound or alloy semiconductors include SiC, SiGe, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, or GaInAsP. The substrate 101 may be doped or undoped.

[0111] Please refer to Figure 2 Impurity region 103 may be formed in substrate 101. The upper surface of impurity region 103 may be substantially coplanar with the upper surface of substrate 101. A photoresist layer may be formed on substrate 101. The photoresist layer may be patterned to expose the area where impurity region 103 is formed. The fabrication technique of the photoresist layer may include using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist layer is patterned, an n-type impurity or p-type impurity implantation process may be performed, and the photoresist layer may act as a mask to substantially prevent such impurities from being implanted into the covered area. After the implantation process, the photoresist layer may be removed, for example by an acceptable ashing process.

[0112] N-type impurity implantation processes can add impurities to contribute multiple free electrons to an intrinsically semiconductor. Examples of n-type dopants for such impurities in a silicon-containing substrate include, but are not limited to, antimony, arsenic, or phosphorus. P-type impurity implantation processes can add impurities to an intrinsically semiconductor to create defects with multiple valence electrons. Examples of p-type dopants for such impurities in a silicon-containing substrate include, but are not limited to, boron, aluminum, gallium, or indium. The doping concentration of impurity region 103 can be between approximately 1E17 atoms / cm³. 3 Up to approximately 1E18 atoms / cm 3 between.

[0113] It should be understood that the term "about" modifies an ingredient, a quantity of a component, or a reactant of this disclosure, indicating a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of the components or the implementation of such methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0114] Please refer to Figure 2 The lower conductive layer 105 may be blanket-deposited on the substrate 101 and electrically connected to the impurity region 103 by contacting it. It should be understood that, at this stage, in a cross-sectional view, the lower conductive layer 105 may cover the entire substrate 101. In some embodiments, for example, the lower conductive layer 105 may comprise polysilicon, polycrystalline germanium, polycrystalline silicon-germanium, or the like. The lower conductive layer 105 may be doped or undoped. For example, the lower conductive layer 105 may be doped with an n-type dopant or a p-type dopant.

[0115] In some embodiments, for example, the lower conductive layer 105 may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, for example, the fabrication technique of the lower conductive layer 105 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or other suitable deposition techniques.

[0116] Please refer to Figure 1 and Figure 4 In step S13, a termination layer 107 may be formed on the lower conductive layer 105, and a plurality of first conductive layers 401, a plurality of isolation layers 405 and a plurality of second conductive layers 403 may be formed sequentially and alternately on the termination layer 107 to be configured as a stack.

[0117] Please refer to Figure 4The termination layer 107 may be blanket-deposited on the lower conductive layer 105. In some embodiments, for example, the termination layer 107 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide oxide, or the like. In some embodiments, for example, the termination layer 107 may comprise a low dielectric constant material. The low dielectric constant material may have a dielectric constant less than 3.6. In some embodiments, for example, the termination layer 107 may comprise oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high dielectric constant materials, or combinations thereof. In some embodiments, the termination layer 107 may comprise multiple layers. For example, a layer of silicon oxide and a layer of high dielectric constant material.

[0118] High dielectric constant materials may have a dielectric constant greater than approximately 7.0 and may be a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. Examples of high dielectric constant materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. High dielectric constant materials may also include multiple dopants, for example, lanthanum and aluminum.

[0119] In some embodiments, the fabrication technique for the termination layer 107 may include atomic layer deposition, chemical vapor deposition, molecular-beam deposition, plasma-enhanced chemical vapor deposition, chemical solution deposition, similar techniques, or combinations thereof. In some embodiments, the thickness of the termination layer 107 may vary depending on the deposition process and the composition and amount of materials used.

[0120] Please refer to Figure 4Multiple first conductive layers 401, multiple insulating layers 405, and multiple second conductive layers 403 may be deposited alternately. For brevity, clarity, and ease of description, only one first conductive layer 401, one second conductive layer 403, and one insulating layer 405 will be described. For example, the first conductive layer 401 may be blanket-formed on the termination layer 107. The insulating layer 405 may be blanket-formed on the first conductive layer 401. The second conductive layer 403 may be blanket-formed on the insulating layer 405. Other insulating layers 405 may be blanket-formed on the second conductive layer 403. Other first conductive layers 401 may be blanket-formed on other insulating layers 405. Other insulating layers 405 and other second conductive layers 403 may be sequentially formed on other first conductive layers 401. Other first conductive layers 401, second conductive layers 403, and insulating layers 405 may be stacked in a similar manner.

[0121] It should be understood that, Figure 4 The quantities of the first conductive layer 401, the second conductive layer 403, and the insulating layer 405 are for illustrative purposes only. The quantities of the first conductive layer 401, the second conductive layer 403, and the insulating layer 405 may be more or less than those specified in the diagram. Figure 4 The quantity described in the text.

[0122] In some embodiments, for example, the first conductive layer 401 and the second conductive layer 403 may comprise a group IV material or a group III-V compound material. Group IV materials include, for example, Si, Ge, SiGe, SiGeSn, or the like, while group III-V compound materials include, for example, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP, or the like. In some embodiments, the first conductive layer 401 and the second conductive layer 403 comprise silicon. In some embodiments, the first conductive layer 401 and the second conductive layer 403 comprise carbon-doped silicon (Si:C). This Si:C layer may be grown in the same chamber used for other epitaxial steps or in a dedicated Si:C epitaxial chamber. The Si:C may contain carbon in the range of 0.2% to 0.3%.

[0123] In some embodiments, the first conductive layer 401 and the second conductive layer 403 may comprise different materials. This difference in materials allows for different strains in the first conductive layer 401 and the second conductive layer 403. For example, the first conductive layer 401 may be a layer of Si. 0.50 Ge 0.50The second conductive layer 403 is a layer of Si. The first conductive layer 401 may have a natural lattice constant greater than that of the second conductive layer 403. Therefore, the first conductive layer 401 may be under compressive strain, while the second conductive layer 403 may be under tensile strain. In some embodiments, the first conductive layer 401 and the lower conductive layer 104 may contain the same material, but this is not a limitation. In some embodiments, the second conductive layer 403 and the lower conductive layer 105 may contain the same material, but this is not a limitation.

[0124] In some embodiments, the first conductive layer 401 and the second conductive layer 403 may comprise epitaxial semiconductor materials grown from gaseous or liquid precursors. The fabrication techniques for the first conductive layer 401 and the second conductive layer 403 may include rapid thermochemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, limited reaction processing chemical vapor deposition, or similar techniques. In some embodiments, the first conductive layer 401 and the second conductive layer 403 may comprise crystalline materials.

[0125] In some embodiments, epitaxial silicon, SiGe, and / or carbon-doped silicon (Si:C) may be doped during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic), or p-type dopants (e.g., boron or gallium). The doping concentration of the first conductive layer 401 and the second conductive layer 403 may be between approximately 1E19 cm⁻¹. -3 To approximately 2E21 cm -3 Between, or approximately 1E20 cm -3 To approximately 1E21 cm -3 between.

[0126] In some embodiments, the gas source for the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial Si can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof.

[0127] An epitaxial germanium layer may be deposited from a germanium gas source, wherein the silicon gas source is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, or combinations thereof.

[0128] The fabrication technique for an epitaxial silicon-germanium alloy layer may involve the use of a combination of such gas sources. Multiple carrier gases, such as hydrogen, nitrogen, helium, and argon, can be used.

[0129] In some embodiments, for example, the first conductive layer 401 may be condensed using a thermal oxidation process, resulting in the consumption of Si in the SiGe layer (e.g., the first conductive layer 401) (through the oxidation process), while Ge is driven downwards into the underlying layer. For example, the thermal oxidation process may include exposing the initial SiGe layer to oxygen at a temperature for a period of time, the temperature being between about 900 and about 1200, such as 1100, and the time period being between about 5 minutes and about 15 minutes.

[0130] In some embodiments, the thickness T1 of the first conductive layer 401 may be less than the thickness T2 of the second conductive layer 403. In some embodiments, the first conductive layer 401 and the second conductive layer 403 may have a thickness less than a critical thickness. In some embodiments, the second conductive layer 403 may have a thickness between approximately 6 nm and approximately 20 nm. The first conductive layer 401 may have a thickness between approximately 4 nm and approximately 10 nm. In some embodiments, the thickness T1 of the first conductive layer 401 may be greater than or equal to the thickness T2 of the second conductive layer 403. In some embodiments, the thickness T1 of the first conductive layer 401 may be greater than or equal to the thickness T3 of the lower conductive layer 105. In some embodiments, the thickness T1 of the first conductive layer 401 may be less than the thickness T3 of the lower conductive layer 105.

[0131] Please refer to Figure 4 For example, the isolation layer 405 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, for example, the isolation layer 405 may comprise a low dielectric constant material. In some embodiments, for example, the isolation layer 405 may comprise oxides, nitrides, oxynitride silicates (e.g., metal silicates), aluminates, titanates, nitrides, high dielectric constant materials, or combinations thereof. In some embodiments, the isolation layer 405 may comprise multiple layers. For example, a layer of silicon oxide and a layer of high dielectric constant material. In some embodiments, the isolation layer 405 may comprise the same material as the termination layer 107, but is not limited thereto.

[0132] High dielectric constant materials may have a dielectric constant greater than approximately 7.0 and may be a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. Examples of high dielectric constant materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. High dielectric constant materials may also include multiple dopants, for example, lanthanum and aluminum.

[0133] In some embodiments, the fabrication technique of the isolation layer 405 may include atomic layer deposition, chemical vapor deposition, molecular beam deposition, plasma-enhanced chemical vapor deposition, chemical solution deposition, similar techniques, or combinations thereof. In some embodiments, the thickness T4 of the isolation layer 405 may be greater than or equal to the thickness T5 of the termination layer 107. In some embodiments, the thickness T4 of the isolation layer 405 may be less than the thickness T5 of the termination layer 107. In some embodiments, the thickness of the isolation layer 405 may vary depending on the deposition process and the composition and amount of materials used.

[0134] The lower conductive layer 105, the termination layer 107, a plurality of first conductive layers 401, a plurality of isolation layers 405 and a plurality of second conductive layers 403 are configured together to form a stack.

[0135] Please refer to Figure 1 and Figure 5 and Figure 6 In step S15, the stack can be patterned to form a first recess R1.

[0136] Please refer to Figure 5 A first masking layer 407 may be formed on the top layer of the stack (e.g., the second conductive layer 403 in this embodiment). In a top view (not shown), the first masking layer 407 may be linear. For example, the first masking layer 407 may be a hard masking layer containing a material that has etch selectivity for the first conductive layer 401, the second conductive layer 403, the insulating layer 405, the terminating layer 107, and the lower conductive layer 105. In some embodiments, for example, the first masking layer 407 may contain amorphous carbon, silicon borocarbonitride, silicon oxycarbonitride, or silicon oxide.

[0137] Please refer to Figure 6 , can be for Figure 5 The described intermediate semiconductor element undergoes an etching process to form a first recess R1. For example, the etching process may be reactive ion etching, a neutral beam etching, similar methods, or a combination thereof. The etching process may be anisotropic. After the etching process, the sidewalls of the plurality of first conductive layers 401 and the plurality of second conductive layers 403 may be exposed via the first recess R1. In some embodiments, the etching process may be a timed isotropic wet etching process. In some embodiments, the etching process may be a selective dry etching process. In some embodiments, the etching process may be a combination of dry and wet etching.

[0138] In some embodiments, during the etching process, the etching rate of the first conductive layer 401 may be faster than the etching rate of the second conductive layer 403. After the etching process, the width of the plurality of first conductive layers 401 may be shorter than the width of the plurality of second conductive layers 403 and the plurality of insulating layers 405. The plurality of recesses adjacent to the plurality of first conductive layers 401 may be regarded as a plurality of pits 241D. During the etching process, the plurality of pits 241D may be the result of the plurality of first conductive layers 401 being laterally etched.

[0139] Please refer to Figure 1 and Figure 7 and Figure 8 In step S17, a plurality of first spacers 241 may be formed to cover each sidewall of a plurality of first conductive layers 401.

[0140] Please refer to Figure 7 For example Figure 7 The described intermediate semiconductor element can be conformally formed with a first dielectric material 409. This first dielectric material 409 can completely fill the plurality of pits 241D. In some embodiments, the first dielectric material 409 may be the same as the material of the terminating layer 107 or the material of the insulating layer 405, but is not limited thereto. In some embodiments, for example, the first dielectric material 409 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, for example, the first dielectric material 409 may comprise a low dielectric constant material. In some embodiments, for example, the first dielectric material 409 may comprise oxides, nitrides, oxynitride silicates (e.g., metal silicates), aluminates, titanates, nitrides, high dielectric constant materials, or any combination thereof. For example, the fabrication techniques for this first dielectric material 409 may include atomic layer deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition.

[0141] Please refer to Figure 8 An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the first dielectric material 409. After the etching process, the first dielectric material 409 outside the plurality of recesses 241D can be removed. The first dielectric material 409 retained in the plurality of recesses 241D can be considered as a plurality of first spacers 241. The first recess R1 can be transformed into a second recess R2. Each sidewall of the plurality of second conductive layers 403 can be exposed via the second recess R2. Conversely, each sidewall of the plurality of first conductive layers 401 can be covered by the plurality of first spacers 241 and is not exposed via the second recess R2. After the etching process, the first masking layer 407 can be removed.

[0142] In some embodiments, prior to the etching process, the first dielectric material 409 deposited on the outer side of the plurality of pits 241D can be transformed into a transition dielectric material (not shown). In one embodiment, the transition dielectric material may have an etch selectivity different from that of the first dielectric material 409. By modifying the etch selectivity of the transition dielectric material relative to the first dielectric material 409, the etching process can be more easily controlled to remove the first dielectric material 409 from the outer side of the plurality of pits 241D. In this case, the etching process can be an isotropic etching process. This transformation can occur through plasma treatment, implantation, oxidation, or a combination thereof. The transition process is sufficient to change the etch selectivity of the first dielectric material 409 on the outer side of the plurality of pits 241D without affecting the mobility of the plurality of first conductive layers 401 and the plurality of second conductive layers 403 or reducing the performance of the plurality of first conductive layers 401 and the plurality of second conductive layers 403.

[0143] In some embodiments, the multiple first conductive layers 401 may not be etched laterally during the etching process. In other words, the sidewalls of the stack may be substantially vertical. Alternatively, a selective oxidation process may be performed to selectively form a multiple first spacer 241 on each sidewall of the multiple first conductive layers 401. The selective oxidation process may be a selective wet oxidation or a selective dry oxidation. If a selective wet oxidation process is desired, a high-pressure steam oxidation process may be performed. A high-pressure steam oxidation process may include oxidation performed in a combined H2O / N base environment at atmospheric pressure within a relatively low temperature range, for example, between approximately 500°C and approximately 700°C. If a selective dry etching process is desired, oxidation may be performed in an O2 or O2 / N2 base environment at atmospheric pressure within a temperature range, for example, between approximately 600°C and approximately 800°C, while the atmospheric pressure is close to 10,1325 Pa. The selective oxidation process can be time-based to achieve a plurality of first spacers 241 with a desired width. The width W1 of the plurality of first spacers 241 can be between approximately 5 nm and approximately 7 nm. An additional etching process can be performed to remove excess oxide material from each sidewall of the plurality of first conductive layers 401.

[0144] Please refer to Figure 1 and Figure 9 In step S19, a first palm portion 211 may be formed in the second recess R2.

[0145] Please refer to Figure 9A first palm portion 211 may be formed to fill the second recess R2 and electrically connected to a plurality of second conductive layers 403 and a lower conductive layer 105. In some embodiments, the first palm portion 211 may be formed on and electrically connected to the impurity region 103. In some embodiments, the first palm portion 211 may contain the same material as the plurality of second conductive layers 403 and the plurality of first conductive layers 401. In some embodiments, the first palm portion 211 may contain a material different from the plurality of second conductive layers 403 or the plurality of first conductive layers 401.

[0146] In some embodiments, for example, the first palm portion 211 may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, for example, the fabrication technique of the first palm portion 211 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or other suitable deposition techniques.

[0147] In some embodiments, for example, the first palm portion 211 may comprise a group IV material or a group III-V compound material. Group IV materials include, for example, Si, Ge, SiGe, SiGeSn, or similar materials, while group III-V compound materials include, for example, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP, or similar materials. The fabrication techniques for the first palm portion 211 may include rapid thermochemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, limited reaction processing chemical vapor deposition, or similar techniques. The first palm portion 211 may be doped with n-type or p-type dopants.

[0148] Please refer to Figure 9 It can perform a planarization process, such as chemical mechanical polishing, to remove excess material and provide a generally flat surface for subsequent processing steps.

[0149] Please refer to Figure 1 , Figure 10 as well as Figure 11 In step S21, the stack is patterned to form a third recess R3. The plurality of first conductive layers 401 can be transformed into a plurality of second fingers 223, 225, the plurality of second conductive layers 403 can be transformed into a plurality of first fingers 213, 215, and the plurality of isolation layers 405 can be transformed into a plurality of capacitor isolation layers 231, 233, 235.

[0150] Please refer to Figure 10A second masking layer 411 may be formed on the top layer of the stack and may cover the first palm portion 211. In a top view (not shown), the second masking layer 411 may be linear. For example, the second masking layer 411 may be a hard mask comprising a material having etch selectivity relative to the first conductive layer 401, the second conductive layer 403, the insulating layer 405, the terminating layer 107, and the lower conductive layer 105. In some embodiments, for example, the second masking layer 411 may comprise amorphous carbon, boron silicon carbonitride, oxysilicon carbonitride, or silicon carbide.

[0151] Please refer to Figure 11 , can be for Figure 10 The described intermediate semiconductor element undergoes an etching process to form a third recess R3. For example, the etching process may be a reactive ion etching, a neutral beam etching, a similar method, or a combination thereof. The etching process may be anisotropic. The third recess R3 may be located opposite the first palm portion 211 and sandwiched therebetween with the stack. After the etching process, the sidewalls of the plurality of first conductive layers 401 and the plurality of second conductive layers 403 may be exposed via the third recess R3. In some embodiments, the etching process may be a timedisotropic wet etching process. In some embodiments, the etching process may be a selective dry etching process. In some embodiments, the etching process may be a combination of dry and wet etching.

[0152] In some embodiments, during the etching process, the etching rate of the second conductive layer 403 may be faster than the etching rate of the first conductive layer 401. After the etching process, a plurality of recesses may be formed adjacent to the plurality of second conductive layers 403 and can be considered as a plurality of pits 243D. During the etching process, these plurality of pits 243D may be the result of the plurality of second conductive layers 403 being laterally etched.

[0153] After the etching process, the plurality of first conductive layers 401 can be transformed into a plurality of second fingers 223, 225. The plurality of second conductive layers 403 can be transformed into a plurality of first fingers 213, 215. The plurality of insulating layers 405 can be transformed into a plurality of capacitor insulating layers 231, 233, 235.

[0154] In some embodiments, the width W2 of the plurality of capacitor isolation layers 231, 233, 235 may be greater than the width W3 of the plurality of first finger portions 213, 215 or the width W4 of the plurality of second finger portions 223, 235. In some embodiments, the width W3 of the plurality of first finger portions 213, 215 may be greater than or equal to the width W4 of the plurality of second finger portions 223, 225. In some embodiments, the width W3 of the plurality of first finger portions 213, 215 may be less than the width W4 of the plurality of second finger portions 223, 225. In some embodiments, the width W3 of the plurality of first finger portions 213, 215 may be equal to the width W5 of the lower conductive layer 105, but is not limited thereto. In some embodiments, the width W2 of the plurality of capacitor isolation layers 231, 233, 235 may be equal to the width W6 of the termination layer 107, but is not limited thereto.

[0155] Please refer to Figure 1 , Figure 12 and Figure 13 In step S23, a plurality of second spacers 243 may be formed to cover each sidewall of a plurality of first finger portions 213, 215, and a third spacer 245 may be formed to cover the sidewall of the lower conductive layer 105.

[0156] Please refer to Figure 12 , can be for Figure 11 The described intermediate semiconductor element conformally forms a second dielectric material 413. This second dielectric material 413 can completely fill the plurality of pits 243D. In some embodiments, the second dielectric material 413 may be the same as, but not limited to, the material of the termination layer 107, the first dielectric material 409, or the material of the isolation layer 405. In some embodiments, for example, the second dielectric material 413 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, for example, the second dielectric material 413 may comprise a low dielectric constant material. In some embodiments, for example, the second dielectric material 413 may comprise oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high dielectric constant materials, or combinations thereof. For example, the fabrication techniques of this second dielectric material 413 may include atomic layer deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition.

[0157] Please refer to Figure 13An etching process, such as an anisotropic dry etching process, can be performed to remove some portions of the second dielectric material 413. After the etching process, the second dielectric material 413 outside the plurality of recesses 243D can be removed. The second dielectric material 413 retained in the plurality of recesses 243D can be considered as a plurality of second spacers 243 and third spacers 245. The third recess R3 can be transformed into a fourth recess R4. The plurality of second spacers 243 and third spacers 245 are located opposite to the first palm portion 211. The sidewalls of the plurality of second finger portions 223, 225 can be exposed via the fourth recess R4. Conversely, the sidewalls of the plurality of first finger portions 213, 215 can be covered by the sidewalls of the plurality of second spacers 243, and the sidewalls of the lower conductive layer 105 can be covered by the third spacers 245. After the etching process, the second masking layer 411 can be removed.

[0158] In some embodiments, prior to the etching process, the second dielectric material 413 deposited on the outer side of the plurality of recesses 243D can be transformed into a transition dielectric material (not shown). In one embodiment, the transition dielectric material may have a different etch selectivity than the second dielectric material 413. By modifying the etch selectivity of the transition dielectric material relative to the second dielectric material 413, the etching process can be more easily controlled to remove the second dielectric material 413 from the outer side of the plurality of recesses 243D. In this case, the etching process can be an isotropic etching process. This transformation can occur through plasma treatment, implantation, oxidation, or a combination thereof. The transition process is sufficient to change the etch selectivity of the second dielectric material 413 on the outer side of the plurality of recesses 243D without affecting the mobility of the plurality of first fingers 213, 215 and the plurality of second fingers 223, 225 or reducing the performance of the plurality of first fingers 213, 215 and the plurality of second fingers 223, 225.

[0159] In some embodiments, the second dielectric material 413 layer may not be etched laterally during the etching process. In other words, the sidewalls of the stack may be substantially vertical. Alternatively, a selective oxidation process may be performed to selectively form a plurality of second spacers 243 on each sidewall of the plurality of first fingers 213, 215 and to form third spacers 245 on each sidewall of the plurality of second fingers 223, 225. The selective oxidation process may be a selective wet oxidation or a selective dry oxidation. If a selective wet oxidation process is desired, a high-pressure steam oxidation process may be performed. The high-pressure steam oxidation process may include performing oxidation in a combined H2O / N base environment at one atmosphere of pressure within a relatively low temperature range, for example, between approximately 500°C and approximately 700°C. If a selective dry etching process is desired, oxidation can be performed in an O2 or O2 / N2-based environment at atmospheric pressure within a temperature range, for example, between approximately 600°C and approximately 800°C, and at an atmospheric pressure close to 10,1325 Pa. This selective oxidation process can be time-based to achieve multiple second spacers 243 and third spacers 245 with a desired width. Additional etching processes can be performed to remove excess oxide material from the sidewalls of the multiple first fingers 213, 215.

[0160] In some embodiments, the width W7 of the plurality of second spacers 243 may be greater than or equal to the width W1 of the plurality of first spacers 241. In some embodiments, the width W7 of the plurality of second spacers 243 may be less than the width W1 of the plurality of first spacers 241. In some embodiments, the width W7 of the plurality of second spacers 243 may be between approximately 5 nm and approximately 7 nm.

[0161] Please refer to Figure 1 and Figure 14 In step S25, a second palm portion 221 may be formed in the fourth recess R4.

[0162] Please refer to Figure 4A second palm portion 221 can be formed to fill the fourth recess R4 and electrically connected to a plurality of second finger portions 223, 225. The second palm portion 221 can be electrically isolated from the plurality of first finger portions 213, 215 and the lower conductive layer 105 through a plurality of second spacers 243 and a third spacer 245. In some embodiments, the second palm portion 221 may contain the same material as the plurality of second finger portions 223, 225 or the plurality of first finger portions 213, 215. In some embodiments, the second palm portion 221 may contain a material different from the plurality of second finger portions 223, 225 or the plurality of first finger portions 213, 215. In some embodiments, the second palm portion 221 may contain the same material as the first palm portion 211, but is not limited thereto. In some embodiments, the second palm portion 221 and the first palm portion 211 may have the same electrical type, such as n-type or p-type.

[0163] In some embodiments, for example, the second palm portion 221 may comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, for example, the fabrication technique of the second palm portion 221 may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, or other suitable deposition techniques.

[0164] In some embodiments, for example, the second palm portion 221 may comprise a group IV material or a group III-V compound material. Group IV materials include, for example, Si, Ge, SiGe, SiGeSn, or the like, while group III-V compound materials include, for example, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP, or the like. The fabrication techniques for the second palm portion 221 may include rapid thermochemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, limited reaction processing chemical vapor deposition, or similar techniques. In some embodiments, the second palm portion 221 may be doped with n-type or p-type dopants.

[0165] Please refer to Figure 14 A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a generally flat surface for subsequent processing steps.

[0166] Please refer to Figure 14A first palm portion 211 and a plurality of first finger portions 213, 215 are configured together to form a lower electrode. A second palm portion 221 and a plurality of second finger portions 223, 225 are configured together to form an upper electrode. A plurality of capacitor isolation layers 231, 233, 235, a plurality of first spacers 241, a plurality of second spacers 243, and a third spacer 245 electrically isolate the lower electrode and the upper electrode. The upper electrode, the lower electrode, and the plurality of capacitor isolation layers 231, 233, 235 are configured together to form a capacitor structure. In some embodiments, the lower electrode may further include a lower conductive layer 105. The lower conductive layer 105 may be electrically isolated from the second finger portions 223 via a termination layer 107.

[0167] Figures 15 to 18 This is a cross-sectional schematic diagram illustrating various semiconductor elements 1B, 1C, 1D, and 1E according to an embodiment of the present disclosure.

[0168] Please refer to Figure 15 Semiconductor element 1B may have similar characteristics to Figure 14 The described structure. In Figure 15 The same or similar Figure 14 The components in the document are labeled with similar component numbers, and their repetitive descriptions have been omitted. In semiconductor component 1B, impurity region 103 may be disposed below and in contact with second palm portion 221.

[0169] Please refer to Figure 16 Semiconductor element 1C may have similar characteristics to Figure 14 The described structure. In Figure 16 The same or similar Figure 14 The components in the document are labeled with similar component numbers, and their repetitive descriptions have been omitted. In semiconductor device 1C, a third spacer 245 may be disposed between the lower conductive layer 105 and the first palm portion 211 to electrically isolate it from the lower conductive layer 105 and the first palm portion 211. The second palm portion 221 may contact the lower conductive layer 105 and be electrically connected to the lower conductive layer 105.

[0170] Please refer to Figure 17 Semiconductor element 1D can have similar characteristics to Figure 16 The described structure. In Figure 17 The same or similar Figure 16 The components in the semiconductor device 1D are labeled with similar component numbers and their repetitive descriptions have been omitted. In the semiconductor device 1D, the impurity region 103 may be disposed below and in contact with the second palm portion 221.

[0171] Please refer to Figure 18 Semiconductor element 1E may have similar characteristics to Figure 14 The described structure. In Figure 18 The same or similar Figure 14The components in the diagram are labeled with similar component numbers, and their repetitive descriptions have been omitted. Semiconductor component 1E may include a buried isolation layer 111. The buried isolation layer 111 may be horizontally disposed in the substrate 101. An impurity region 103 may be disposed above the buried isolation layer 111. The buried isolation layer 111 reduces leakage current.

[0172] Figures 19 to 22 This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device 1F according to an embodiment of the present disclosure.

[0173] Please refer to Figure 19 An intermediate semiconductor device can be similar to, for example Figures 2 to 3 The process described is what it produces. Conversely... Figure 6 After the etching process, the stack has a generally vertical sidewall. In this embodiment, the first conductive layer 401 is a layer of Si. 0.50 Ge 0.50 The second electrical layer 403 is a layer of Si.

[0174] Please refer to Figure 20 A low-temperature oxidation process, less than 700°C, can be performed to oxidize the exposed sidewalls of the plurality of first conductive layers 401 and second conductive layers 403. In this embodiment, a wet oxidation at 630°C is used. Containing Si 0.50 Ge 0.50 The plurality of first conductive layers 401 can be oxidized at least ten times faster than the plurality of second conductive layers 403 containing Si in such a case. Therefore, the plurality of sacrificial layers 415 formed during the low-temperature oxidation process can be relatively thicker than those sacrificial layers 415 formed during the low-temperature oxidation process.

[0175] Please refer to Figure 21 An oxidation etching process can be performed to remove multiple sacrificial layers 417. The oxidation process can be a plasma-assisted dry etching process, which includes exposing a substrate to hydrogen, NF3, and NH3 plasma byproducts simultaneously, or wet etching using a solution containing hydrofluoric acid. The exposed multiple second conductive layers 403 can be used as seeds to epitaxially grow the first palm portion 211. It should be understood that some portions of the sacrificial layers 415 can also be removed. However, since the sacrificial layers 415 are thicker than the sacrificial layers 417, after removing the sacrificial layers 417, the sacrificial layers 415 can still cover multiple first conductive layers 401. The remaining sacrificial layers 415 can be considered as multiple first spacers 241.

[0176] Please refer to Figure 22 Other components (such as the first palm portion 211 and the second palm portion 221) can be similar to... Figures 9 to 14 Prepared by the described procedure.

[0177] Figures 23 to 27 This is a cross-sectional schematic diagram illustrating a process for fabricating a semiconductor device 1G according to an embodiment of the present disclosure.

[0178] Please refer to Figure 23 An interlayer dielectric layer 109 may be deposited on the substrate 101 as a blanket. A lower conductive layer 105 may be formed in the lower conductive layer 105, for example, by an damascene process or other suitable process. A termination layer 107 may be selectively deposited on the interlayer dielectric layer 109. A plurality of first conductive layers 401, a plurality of insulating layers 405, and a plurality of second conductive layers 403 may be formed sequentially and alternately on the termination layer 107.

[0179] Please refer to Figure 24 The first depression R1 and multiple pits 241D can be similar to, for example, Figure 5 and Figure 6 The process described is used to prepare the material. It should be understood that the interlayer dielectric layer 109 may be inactive after the etching process.

[0180] Please refer to Figure 25 The first gap 241 and the first palm portion 211 can be similar to, Figures 7 to 9 The process described herein is used to prepare the first palm portion 211, which may be formed on the interlayer dielectric layer 109 and may contact the lower conductive layer 105. That is, the first palm portion 211 may be electrically coupled to the impurity region 103 via the lower conductive layer 105.

[0181] Please refer to Figure 26 The fourth depression R4 and multiple pits 243D can be similar to, for example... Figure 10 and Figure 11 The process described is used to prepare the material. It should be understood that the interlayer dielectric layer 109 may be inactive after the etching process.

[0182] Please refer to Figure 27 The second gap 243 and the second palm portion 221 can be similar to, Figures 12 to 14 Prepared by the described procedure.

[0183] Figure 28 This is a cross-sectional schematic diagram illustrating a semiconductor element 1H according to an embodiment of the present disclosure.

[0184] Please refer to Figure 28 Semiconductor element 1H may have similar characteristics to Figure 27 The described structure. In Figure 28 The same or similar Figure 27 The components in the diagram are labeled with similar component numbers, and their repetitive descriptions have been omitted. In semiconductor device 1H, impurity region 103 may be disposed below second palm portion 221. Second palm portion 221 and impurity region 103 may be electrically coupled via a lower conductive layer 105 inserted therebetween.

[0185] One embodiment of this disclosure provides a semiconductor device including a first palm portion disposed on a substrate; a second palm portion disposed on the substrate and located opposite to the first palm portion; a first finger portion disposed generally parallel to a main surface of the substrate and located between the first palm portion and the second palm portion, and connected to the first palm portion; a second finger portion disposed generally parallel to the first finger portion and located between the first palm portion and the second palm portion, and connected to the second palm portion; a capacitor isolation layer disposed between the first finger portion and the second finger portion; a first spacer disposed between the first palm portion and the second finger portion; and a second spacer disposed between the second palm portion and the first finger portion.

[0186] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; sequentially forming a first conductive layer, an isolation layer, and a second conductive layer on the substrate to be configured as a stack; patterning the stack to form a first recess and expose an impurity region in the substrate; forming a first spacer to cover a sidewall of the first conductive layer; forming a first palm portion in the first recess and connecting it to the second conductive layer; patterning the stack to form a third recess, transforming the second conductive layer into a first finger portion and transforming the first conductive layer into a second finger portion, wherein the third recess is opposite to the first palm portion; forming a second spacer to cover a sidewall of the first finger portion, wherein the second spacer is opposite to the first palm portion; and forming a second palm portion in the third recess and connecting it to the second finger portion.

[0187] Due to the design of the semiconductor device disclosed herein, the contact area of ​​the capacitor structure can be increased. Therefore, the performance of the semiconductor device 1A can be improved. Furthermore, the manufacturing process can be easily integrated with fin-type transistors.

[0188] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0189] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: providing a substrate; sequentially forming a first conductive layer, an isolation layer, and a second conductive layer to configure a stack on the substrate; patterning the stack to form a first recess and expose a dopant region in the substrate; forming a first spacer to cover a sidewall of the first conductive layer; forming a first palm portion in the first recess and connected to the second conductive layer; patterning the stack to form a third recess, transform the second conductive layer into a first finger portion, and transform the first conductive layer into a second finger portion, wherein the third recess is formed at an opposite of the first palm portion; forming a second spacer to cover a sidewall of the first finger portion, wherein the second spacer is formed at an opposite of the first palm portion; and forming a second palm portion in the third recess and connected to the second finger portion.

2. The method for producing a semiconductor element according to claim 1, further comprising: forming a lower conductive layer substantially parallel to a main surface of the substrate and connected to the first palm portion.

3. The method for fabricating a semiconductor device of claim 2, wherein the lower conductive layer and the second finger portion comprise a same material.

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