25Gbps transimpedance amplifier with current compensation to improve overload performance

Abstract

This invention discloses a 25Gbps transimpedance amplifier with current compensation to improve overload performance. The current compensation circuit (CMP) is part of the 25Gbps transimpedance amplifier. The main link of the transimpedance amplifier consists of a core amplifier (Tia_core), a single-ended to differential amplifier (S2D), an output buffer, an automatic gain control (AGC) circuit, the current compensation circuit (CMP), and a mirror transimpedance amplifier (Dummy_tia) module. The input current signal is converted into a single-ended voltage signal by the core amplifier (Tia_core), and then the single-ended to differential amplifier (S2D) converts the single-ended signal voltage into a differential voltage. The output buffer transmits this differential signal to the next stage chip, ensuring impedance matching during transmission. The automatic gain control (AGC) circuit automatically adjusts the gain of the core amplifier (Tia_core) circuit according to the input current amplitude. The current compensation circuit (CMP) included in this invention can effectively prevent the transimpedance amplifier link from over-saturating and causing signal distortion when the input current signal is a large signal at the mA level, thus significantly improving the overload performance of the transimpedance amplifier.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a 25Gbps transimpedance amplifier that uses current compensation to improve overload performance. Background Technology

[0002] As users demand higher network download speeds, 5G communication places greater demands on the transport network, such as high capacity, long distance, high bandwidth, low latency, and massive connectivity. The 5G transport network architecture (fronthaul, midhaul, and backhaul) shows that a large number of optical modules are needed between the RRU and DU to carry 5G fronthaul services. The large-scale deployment of macro base stations and small base stations will drive significant demand for optical modules. The core electrical chips in these optical modules include transimpedance amplifier (TIA) chips that convert the high-frequency current output from photodiodes into differential voltages, and transceiver chips that further process the TIA output signals. The typical bit rate for signal processing is 25Gbps. The TIA chip, located at the very front of the signal link, is particularly sensitive to noise and the dynamic range of the input current. When the input current is at the μA level (small signal), the performance of the TIA mainly depends on the equivalent noise and link bandwidth. However, when the input current reaches the mA level (large signal), a large-signal conditioning circuit is needed to prevent excessive saturation of the TIA link and subsequent signal distortion. The overload performance of the TIA mainly depends on the large-signal compensation circuit. Summary of the Invention

[0003] The purpose of this invention is to propose a 25Gbps transimpedance amplifier that uses current compensation to improve overload performance. The current compensation circuit (CMP) contained in this transimpedance amplifier can effectively avoid signal distortion caused by excessive saturation of the transimpedance amplifier link when the input current signal is a large signal at the mA level, thus significantly improving the overload performance of the transimpedance amplifier.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a 25Gbps transimpedance amplifier with current compensation to improve overload performance, comprising a core amplifier Tia_core, a single-ended to differential amplifier S2D, an output buffer, an automatic gain control (AGC) circuit, a current compensation circuit CMP, and a mirror transimpedance amplifier Dummy_tia; the core amplifier Tia_core is used to convert the input current signal into a single-ended voltage signal; the single-ended to differential amplifier S2D is used to convert the single-ended signal voltage into a differential voltage; the automatic gain control (AGC) circuit is used to adjust the gain of the core amplifier Tia_core circuit according to the current amplitude from the single-ended to differential amplifier S2D; and the current compensation circuit CMP is used to compensate the current of the core amplifier Tia_core circuit when a large current signal is input.

[0005] The Voutp1 output of the core amplifier Tia_core is connected to the positive input of the single-ended to differential amplifier S2D. The Voutn1 output of the mirror transimpedance amplifier Dummy_tia is connected to the negative input of the single-ended to differential amplifier S2D and the positive input of the current compensation circuit CMP. The negative input of the current compensation circuit CMP is connected to the preset reference voltage Vref. The VG output of the current compensation circuit CMP is connected to the VG input of the core amplifier Tia_core and the VG input of the mirror transimpedance amplifier Dummy_tia. The negative output of the single-ended to differential amplifier S2D is connected to the negative input of the output buffer and the negative input of the automatic gain control circuit AGC. The positive output of the single-ended to differential amplifier S2D is connected to the output buffer. The positive input terminal of the amplifier is connected to the positive input terminal of the automatic gain control (AGC) circuit. The Vb_sig output terminal of the AGC circuit is connected to the Vb_sig input terminal of the core amplifier Tia_core and the Vb_sig input terminal of the mirror transimpedance amplifier Dummy_tia, respectively. The Vb_vga output terminal of the AGC circuit is connected to the Vb_vga input terminal of the core amplifier Tia_core and the Vb_vga input terminal of the mirror transimpedance amplifier Dummy_tia, respectively. The positive output terminal of the output buffer is connected to the power supply VCC1 through resistor Ra and serves as the positive output terminal of the transimpedance amplifier, outputting Voutp. The negative output terminal of the output buffer is connected to the power supply VCC1 through resistor Rb and serves as the negative output terminal of the transimpedance amplifier, outputting Voutn.

[0006] The current compensation circuit CMP includes an operational amplifier OP, a resistor R9, and a current source Iref. The negative input terminal of the operational amplifier OP is connected to one end of the resistor R9 and one end of the current source Iref. The other end of the resistor R9 is connected to the power supply VCC, and the other end of the current source Iref is grounded. The positive input terminal of the operational amplifier OP serves as the positive input terminal of the current compensation circuit CMP.

[0007] Furthermore, the aforementioned core amplifier Tia_core circuit includes resistors R1, R2, R3, R4, Rf1, transistors Q1, Q2, Q3, Q4, Q5, and MOSFET M1. The input terminals of the core amplifier Tia_core circuit are connected to the base of transistor Q1 and one end of resistor Rf1. The emitter of transistor Q1, one end of resistor R1, and the source (S) terminal of MOSFET M1 are all grounded. The gate (G) terminal of MOSFET M1 serves as the VG input terminal of the core amplifier Tia_core. The other ends of resistors R1 and Rf1, and the drain (D) terminal of MOSFET M1 are all connected to the emitter of transistor Q3. The base of transistor Q3 is connected to the crystal... The collector of transistor Q2 is connected to one end of resistor R3. The base of transistor Q2 is connected to the external voltage Vb1. The emitter of transistor Q2 is connected to the collector of transistor Q1 and one end of resistor R4. The other end of resistor R4, the other end of resistor R3, one end of resistor R2, and the collector of transistor Q4 are all connected to the power supply VCC. The base of transistor Q4 serves as the Vb_vga input terminal of the core amplifier Tia_core. The emitter of transistor Q4 is connected to the collector of transistor Q3 and the emitter of transistor Q5. The base of transistor Q5 serves as the Vb_sig input terminal of the core amplifier Tia_core. The collector of transistor Q5 is connected to the other end of resistor R2 and also serves as the Voutp1 output terminal of the core amplifier Tia_core.

[0008] Furthermore, the aforementioned mirrored transimpedance amplifier Dummy_tia circuit includes resistors R5, R6, R7, R8, Rf2, transistors Q6, Q7, Q8, Q9, Q10, and MOSFET M2. The base of transistor Q10 is connected to one end of resistor Rf2. The emitter of transistor Q10, one end of resistor R6, and the source (S) of MOSFET M2 are all grounded. The gate (G) of MOSFET M2 serves as the VG input terminal of the mirrored transimpedance amplifier Dummy_tia. The other ends of resistors R6 and Rf2, and the drain (D) of MOSFET M2 are all connected to the emitter of transistor Q9. The base of transistor Q9 is connected to the collector of transistor Q7 and resistor Rf2. At terminal 8, the base of transistor Q7 is connected to the external voltage Vb1. The emitter of transistor Q7 is connected to the collector of transistor Q10 and one end of resistor R5. The other end of resistor R5, the other end of resistor R8, one end of resistor R7, and the collector of transistor Q6 are all connected to the power supply VCC. The base of transistor Q6 serves as the Vb_vga input of the mirror transimpedance amplifier Dummy_tia. The emitter of transistor Q6 is connected to the collector of transistor Q9 and the emitter of transistor Q8. The base of transistor Q8 serves as the Vb_sig input of the core amplifier Tia_core. The collector of transistor Q8 is connected to the other end of resistor R7 and also serves as the Voutn1 output of the mirror transimpedance amplifier Dummy_tia.

[0009] Furthermore, the aforementioned automatic gain control (AGC) circuit includes resistors R10, R11, R12, and R13, capacitor C1, NMOS transistors M3, M6, and M7, PMOS transistors M4 and M5, and current source I1. The gate (G) of NMOS transistor M6 serves as the positive input terminal of the AGC circuit and is connected to the power supply Vcm through resistor R10. The gate (G) of NMOS transistor M7 serves as the negative input terminal of the AGC circuit and is connected to the power supply Vcm through resistor R11. The sources (S) of NMOS transistors M6 and M7, one end of current source I1, and one end of capacitor C1 are all connected to the source (S) of NMOS transistor M3. The other end of current source I1 is grounded together with the other end of capacitor C1; the gate of NMOS transistor M3 is connected to power supply Vcm, and the drain of NMOS transistor M3 and the drain of PMOS transistor M5 are connected to one end of resistor R13. This connection point serves as the Vb_vga output terminal of the automatic gain control circuit AGC; the drains of NMOS transistors M6, M7, and M4 are connected to one end of resistor R12. This connection point serves as the Vb_sig output terminal of the automatic gain control circuit AGC; the gates of PMOS transistors M4 and M5, the other end of resistor R12, and the other end of resistor R13 are connected together; the source of PMOS transistors M4 and M5 are connected to power supply VCC.

[0010] The 25Gbps transimpedance amplifier described in this invention, which employs current compensation to improve overload performance, offers the following advantages compared to existing technologies:

[0011] The current compensation circuit (CMP) included in this invention can effectively prevent signal distortion caused by excessive saturation of the transimpedance amplifier link when the input current signal is a large signal at the mA level, thereby significantly improving the overload performance of the transimpedance amplifier. Attached Figure Description

[0012] Figure 1 This is the overall block diagram of a 25Gbps transimpedance amplifier;

[0013] Figure 2 It is the core amplifier Tia_core circuit;

[0014] Figure 3 It is a mirrored transimpedance amplifier Dummy_tia circuit;

[0015] Figure 4 It is a current compensation circuit CMP;

[0016] Figure 5 It is an automatic gain control (AGC) circuit.

[0017] Figure 6 This is the large-signal output eye diagram of Tia_core when there is no current compensation circuit CMP;

[0018] Figure 7 This is the simulated eye diagram of the Tia_core circuit output after CMP with current compensation circuit. Detailed Implementation

[0019] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0020] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0021] refer to Figures 1 to 5 This invention provides a 25Gbps transimpedance amplifier with current compensation to improve overload performance, including a core amplifier Tia_core, a single-ended to differential amplifier S2D, an output buffer, an automatic gain control circuit AGC, a current compensation circuit CMP, and a mirror transimpedance amplifier Dummy_tia.

[0022] In this embodiment, the current signal is input from the transimpedance amplifier, converted into a single-ended voltage signal by the core amplifier Tia_core, and input to the single-ended to differential amplifier S2D circuit. The mirror transimpedance amplifier Dummy_tia provides a DC level to one input of the single-ended to differential amplifier S2D circuit. The single-ended to differential amplifier S2D converts the single-ended signal voltage into a differential voltage. The output buffer transmits this differential signal to the next stage chip, ensuring impedance matching during transmission. The automatic gain control (AGC) circuit automatically adjusts the gain of the core amplifier Tia_core circuit based on the input current amplitude. The current compensation circuit CMP compensates for the current in the core amplifier Tia_core circuit when a large current signal is input.

[0023] In this embodiment, as Figure 2As shown, the core amplifier Tia_core circuit consists of transistors Q1, Q2, Q3, Q4, Q5, resistors Rf, R1, R2, R3, R4, and MOSFET M1. The input current is supplied from the base of transistor Q1. The base bias voltage of transistor Q2 is provided by an external reference. The base voltages Vb_sig and Vb_vga of transistors Q4 and Q5 are provided by the automatic gain control (AGC) circuit. The gate voltage VG of MOSFET M1 is provided by the current compensation circuit CMP of this invention. When the input current is large, the increase in VG voltage will cause the current of MOSFET M1 to increase, thereby increasing the compensation current for Q3 and allowing Q3 to operate in its normal working state. The mirrored transimpedance amplifier Dummy_tia circuit is shown below. Figure 3 As shown, its structure is similar to the core amplifier Tia_core circuit.

[0024] In this embodiment, as Figure 4 As shown, the positive voltage Voutn1 of the operational amplifier in the current compensation circuit CMP comes from... Figure 3 In the mirror transimpedance amplifier (Dummy_tia) circuit, the negative voltage Vref is set by the difference between the supply voltage and the product of Iref and R1. When Vref > Voutn1, the output voltage VG of the operational amplifier OP is less than the threshold voltage of MOSFET M1 in the core amplifier (Tia_core) circuit, and the current compensation circuit CMP is not enabled. When Vref < Voutn1, the output voltage VG of the operational amplifier OP increases, the gate voltage of MOSFET M2 in the mirror transimpedance amplifier (Dummy_tia) circuit increases, leading to an increase in the current of MOSFET M2. This causes the output Voutn1 of the mirror transimpedance amplifier (Dummy_tia) circuit to decrease. Ultimately, Vref = Voutn1, and the increase in the gate voltage of MOSFET M1 in the core amplifier (Tia_core) circuit causes MOSFET M1 to generate mA-level current compensation in transistor Q3.

[0025] In this embodiment, as Figure 5 As shown, the input signals Voutp2 and Voutn2 of the automatic gain control (AGC) circuit come from... Figure 1Voutp2 is connected to the gate (G) of NMOS transistor M6, and Voutn2 is connected to the gate (G) of NMOS transistor M7. Voutp2 and Voutn2 are connected to the gate (G) of NMOS transistor M3 via resistors R10 and R11, resulting in Vcm. The sources (S) of NMOS transistors M6, M7, and M3 are connected to a current source I1 and a capacitor C1, with the other ends of I1 and C1 grounded. The drains (D) of M6 and M7 are connected to the drain (D) of PMOS transistor M4, resulting in Vb_sig. The drain (D) of M3 is connected to the drain (D) of PMOS transistor M5, resulting in Vb_vga. The drains (D) of M4 and M5 are connected to their gates (G) via resistors R12 and R13. When the swings of the input signals voutp2 and voutn2 increase, the voltage of Vb_sig decreases, and the voltage of Vb_vga increases.

[0026] The schematic diagram illustrating the improvement of large signals by this invention is shown below. Figure 6 and Figure 7 As shown. Figure 6 The large-signal output eye diagram of Tia_core without the current compensation circuit CMP of this invention shows that when the input current amplitude reaches 2.5mApp, for a 25Gbps transimpedance amplifier, if current compensation is not performed, the output signal bandwidth will be limited because the cutoff frequency of transistor Q3 in the core amplifier Tia_core circuit drops significantly, and the output signal eye diagram will be distorted. Figure 7 This is a simulated eye diagram of the Tia_core circuit output when the current compensation circuit CMP of the present invention is applied and the input is 2.5mApp. Due to the effect of current compensation, the cutoff frequency of transistor Q3 does not change significantly. Figure 7 As shown, the distortion of the output signal has been optimized, the eye diagram amplitude is 160mV, the jitter is 946fs, and the crossover point and eye diagram quality are good.

[0027] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A 25Gbps transimpedance amplifier employing current compensation to improve overload performance, characterized in that, This includes the core amplifier Tia_core, the single-ended to differential amplifier S2D, the output buffer, the automatic gain control circuit AGC, the current compensation circuit CMP, and the mirror transimpedance amplifier Dummy_tia. The core amplifier Tia_core is used to convert the input current signal into a single-ended voltage signal; The single-ended to differential amplifier S2D is used to convert a single-ended signal voltage into a differential voltage. The automatic gain control (AGC) circuit is used to adjust the gain of the core amplifier Tia_core circuit based on the current amplitude from the single-ended to differential amplifier S2D. The current compensation circuit CMP is used to compensate the current of the core amplifier Tia_core circuit when a large current signal is input. The Voutp1 output of the core amplifier Tia_core is connected to the positive input of the single-ended to differential amplifier S2D. The Voutn1 output of the mirror transimpedance amplifier Dummy_tia is connected to the negative input of the single-ended to differential amplifier S2D and the positive input of the current compensation circuit CMP. The negative input of the current compensation circuit CMP is connected to the preset reference voltage Vref. The VG output of the current compensation circuit CMP is connected to the VG input of the core amplifier Tia_core and the VG input of the mirror transimpedance amplifier Dummy_tia. The negative output of the single-ended to differential amplifier S2D is connected to the negative input of the output buffer and the negative input of the automatic gain control circuit AGC. The positive output of the single-ended to differential amplifier S2D is connected to the output buffer. The positive input terminal of the amplifier is connected to the positive input terminal of the automatic gain control (AGC) circuit. The Vb_sig output terminal of the AGC circuit is connected to the Vb_sig input terminal of the core amplifier Tia_core and the Vb_sig input terminal of the mirror transimpedance amplifier Dummy_tia, respectively. The Vb_vga output terminal of the AGC circuit is connected to the Vb_vga input terminal of the core amplifier Tia_core and the Vb_vga input terminal of the mirror transimpedance amplifier Dummy_tia, respectively. The positive output terminal of the output buffer is connected to the power supply VCC1 through resistor Ra and serves as the positive output terminal of the transimpedance amplifier, outputting Voutp. The negative output terminal of the output buffer is connected to the power supply VCC1 through resistor Rb and serves as the negative output terminal of the transimpedance amplifier, outputting Voutn. The current compensation circuit CMP includes an operational amplifier OP, a resistor R9, and a current source Iref. The negative input terminal of the operational amplifier OP is connected to one end of the resistor R9 and one end of the current source Iref. The other end of the resistor R9 is connected to the power supply VCC, and the other end of the current source Iref is grounded. The positive input terminal of the operational amplifier OP serves as the positive input terminal of the current compensation circuit CMP.

2. A 25Gbps transimpedance amplifier with current compensation to improve overload performance according to claim 1, characterized in that, The core amplifier Tia_core circuit includes resistors R1, R2, R3, R4, Rf1, transistors Q1, Q2, Q3, Q4, Q5, and MOSFET M1. The input terminals of the core amplifier Tia_core circuit are connected to the base of transistor Q1 and one end of resistor Rf1. The emitter of transistor Q1, one end of resistor R1, and the source (S) terminal of MOSFET M1 are all grounded. The gate (G) terminal of MOSFET M1 serves as the VG input terminal of the core amplifier Tia_core. The other ends of resistors R1 and Rf1, and the drain (D) terminal of MOSFET M1 are all connected to the emitter of transistor Q3. The base of transistor Q3 is connected to transistors Q2 and Q5. The collector of transistor Q2 is connected to one end of resistor R3, and the base of transistor Q2 is connected to the external voltage Vb1. The emitter of transistor Q2 is connected to the collector of transistor Q1 and one end of resistor R4. The other end of resistor R4, the other end of resistor R3, one end of resistor R2, and the collector of transistor Q4 are all connected to the power supply VCC. The base of transistor Q4 serves as the Vb_vga input terminal of the core amplifier Tia_core. The emitter of transistor Q4 is connected to the collector of transistor Q3 and the emitter of transistor Q5. The base of transistor Q5 serves as the Vb_sig input terminal of the core amplifier Tia_core, and the collector of transistor Q5 is connected to the other end of resistor R2 and also serves as the Voutp1 output terminal of the core amplifier Tia_core.

3. A 25Gbps transimpedance amplifier with current compensation to improve overload performance according to claim 1, characterized in that, The mirrored transimpedance amplifier Dummy_tia circuit includes resistors R5, R6, R7, R8, Rf2, transistors Q6, Q7, Q8, Q9, Q10, and MOSFET M2. The base of transistor Q10 is connected to one end of resistor Rf2. The emitter of transistor Q10, one end of resistor R6, and the source (S) of MOSFET M2 are all grounded. The gate (G) of MOSFET M2 serves as the VG input terminal of the mirrored transimpedance amplifier Dummy_tia. The other ends of resistor R6, the other end of resistor Rf2, and the drain (D) of MOSFET M2 are all connected to the emitter of transistor Q9. The base of transistor Q9 is connected to the collector of transistor Q7 and one end of resistor R8. The base of transistor Q7 is connected to the external voltage Vb1. The emitter of transistor Q7 is connected to the collector of transistor Q10 and resistor Rf2. One end of resistor R5, the other end of resistor R8, one end of resistor R7, and the collector of transistor Q6 are all connected to the power supply VCC; the base of transistor Q6 serves as the Vb_vga input of the mirror transimpedance amplifier Dummy_tia; the emitter of transistor Q6 is connected to the collector of transistor Q9 and the emitter of transistor Q8 respectively; the base of transistor Q8 serves as the Vb_sig input of the core amplifier Tia_core, and the collector of transistor Q8 is connected to the other end of resistor R7 and also serves as the Voutn1 output of the mirror transimpedance amplifier Dummy_tia.

4. A 25Gbps transimpedance amplifier with current compensation to improve overload performance according to claim 1, characterized in that, The automatic gain control (AGC) circuit includes resistors R10, R11, R12, and R13, capacitor C1, NMOS transistors M3, M6, M7, M4, and M5, and a current source I1. The gate (G) of NMOS transistor M6 serves as the positive input terminal of the AGC circuit and is connected to the power supply Vcm via resistor R10. The gate (G) of NMOS transistor M7 serves as the negative input terminal of the AGC circuit and is also connected to the power supply Vcm via resistor R11. The sources (S) of NMOS transistors M6 and M7, one end of current source I1, and one end of capacitor C1 are all connected to the source (S) of NMOS transistor M3. The other end of I1 is grounded together with the other end of capacitor C1; the gate of NMOS transistor M3 is connected to the power supply Vcm; the drain of NMOS transistor M3 and the drain of PMOS transistor M5 are connected to one end of resistor R13, and this connection point serves as the Vb_vga output terminal of the automatic gain control circuit AGC; the drains of NMOS transistors M6, M7, and M4 are connected to one end of resistor R12, and this connection point serves as the Vb_sig output terminal of the automatic gain control circuit AGC; the gates of PMOS transistors M4 and M5, the other end of resistor R12, and the other end of resistor R13 are connected together; the source of PMOS transistors M4 and M5 are connected to the power supply VCC.

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