A bandwidth enhancement and dynamic pole tracking circuit for high-speed burst-mode transimpedance amplifiers

Abstract

This invention discloses a bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier, comprising a core loop module and a bandwidth enhancement module. The input terminal of the core loop module constitutes the input terminal of the transimpedance amplifier bandwidth circuit, and the output terminal of the core loop module constitutes the output terminal of the transimpedance amplifier bandwidth circuit. The core loop module and the bandwidth enhancement module are connected. The input terminal of the core loop module receives the current to be processed and, in conjunction with the bandwidth enhancement module, converts the current to obtain a corresponding voltage, which is output from the output terminal of the core loop module. This reduces the link bandwidth of the transimpedance amplifier bandwidth circuit for the current to be processed. This invention, through bandwidth enhancement and dynamic pole tracking circuitry, can ensure higher bandwidth across the entire dynamic range of the input signal, thereby achieving excellent bandwidth and sensitivity indicators, significantly improving chip security and signal transmission quality.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier. Background Technology

[0002] With the rapid development of the global broadband access market, 100 Mbps broadband is gradually becoming the standard in China. Existing PON (Passive Optical Network) technology standards face new upgrade demands in terms of bandwidth requirements, service support capabilities, and performance improvements for access node equipment and supporting equipment. PON uses TDM broadcasting for downlink and Time Division Multiple Access (TDM) for uplink. This operating mode dictates that the downlink transceiver circuits (including the transmitter at the OLT and the receiver at the ONU) operate in continuous mode, while the uplink transceiver circuits (including the transmitter at the ONU and the receiver at the OLT) operate in burst mode. Compared to continuous mode, the burst transceiver chip at the OLT, especially the transimpedance amplifier (TIA), has a higher technical threshold. The protection time between burst signal data packets is shorter, and the preamble sequence used for level and clock recovery is also shorter, making the performance requirements for the PON burst transceiver chip more stringent.

[0003] To achieve a high-speed, wide dynamic range burst-mode transimpedance amplifier, it is usually necessary to dynamically adjust the closed-loop parameters of the core amplifier according to the signal strength. This automatic gain control circuit poses a great challenge to the bandwidth and stability of the core amplifier. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier. This circuit achieves higher bandwidth across the entire dynamic range of the input signal, thereby obtaining excellent bandwidth and sensitivity performance, and significantly improving the chip's security and signal transmission quality.

[0005] The purpose of this invention is to provide a bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier, comprising a core loop module and a bandwidth enhancement module. The input terminal of the core loop module constitutes the input terminal of the transimpedance amplifier bandwidth circuit, and the output terminal of the core loop module constitutes the output terminal of the transimpedance amplifier bandwidth circuit. The core loop module and the bandwidth enhancement module are connected. The input terminal of the core loop module receives the current to be processed and, in conjunction with the bandwidth enhancement module, converts the current to be processed to obtain a corresponding voltage, which is output from the output terminal of the core loop module, thereby reducing the link bandwidth of the transimpedance amplifier bandwidth circuit for the current to be processed.

[0006] The core loop module includes a current mirror I1, a current mirror I2, an NMOS transistor M1, an NMOS transistor M2, a gate capacitor C1, resistors R1 and R2, and variable resistors R3, R4, and R5. The bandwidth enhancement module includes a current mirror I3, NMOS transistors 4, M5, M6, M7, and M8, a PMOS transistor M9 and M10, and resistors R6, R7, and R8. The gate of NMOS transistor M1 is connected to one end of resistor R2 and one end of variable resistor R3; this connection point is the input terminal of the core loop module, forming the bandwidth circuit of the transimpedance amplifier. The input terminal is used to receive the current to be processed. The source terminals of NMOS transistors M1, M7, M5, and M6, one end of resistor R1, and the negative terminal of current mirror I3 are connected and grounded. The drain terminal of NMOS transistor M1, the negative terminal of current mirror I2, one end of gate capacitor C1, and the source terminal of NMOS transistor M2 are connected. The drain terminal of NMOS transistor M2 is connected to one end of resistor R4, one end of variable resistor R5, and the gate terminal of NMOS transistor M4. The source terminal of NMOS transistor M4 is connected to the other end of resistor R2, the other end of variable resistor R3, and the gate terminal of NMOS transistor M6. The gate of transistor M7 is connected to the drain of NMOS transistor M5. This connection point is the output terminal of the core loop module, forming the output terminal of the transimpedance amplifier bandwidth circuit, and the output voltage. The drain of NMOS transistor M7 is connected to the source of NMOS transistor M8. The gate of NMOS transistor M5 is connected to the gate of NMOS transistor M6, the drain of NMOS transistor M6, and the drain of PMOS transistor M9. The other end of resistor R4 is connected to the other end of variable resistor R5, the positive terminal of current mirror I2, and the positive terminal of current mirror I1. The negative terminal of current mirror I1, the drain of NMOS transistor M3, the gate of NMOS transistor M3, and the NMOS transistor M9 are also connected. The gate of transistor M2 is connected to the gate of NMOS transistor M8. The source of NMOS transistor M3 is connected to the other end of resistor R1. The other end of gate capacitor C1, the drain of NMOS transistor M8, and one end of resistor R6 are connected. The drain of NMOS transistor M4, the source of PMOS transistor M9, and one end of resistor R7 are connected. The other end of resistor R6 is connected to the other end of resistor R7 and one end of resistor R8. The other end of resistor R8 is connected to the source of PMOS transistor M10. The gate of PMOS transistor M9, the gate of PMOS transistor M10, the drain of MOS transistor M10, and the positive terminal of current mirror I3 are connected.

[0007] It also includes a bandwidth enhancement module and a dynamic pole compensation module; NMOS transistor M5, NMOS transistor M7, PMOS transistor M9, and resistor R7 constitute the bandwidth enhancement module.

[0008] NMOS transistors M7 and M8, resistor R6, and capacitor C1 constitute a dynamic pole compensation module. Attached Figure Description

[0009] Figure 1 This is a circuit diagram illustrating the application of this patent to bandwidth enhancement and dynamic pole tracking in burst transimpedance amplifiers.

[0010] Figure 2 A schematic diagram of the AC characteristics of the bandwidth enhancement technology of this patent when the average input current is 10uA;

[0011] Figure 3 This is a schematic diagram of the AC characteristics of the bandwidth enhancement technology of this patent when the average input current is 1mA. Detailed Implementation

[0012] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier. This circuit, through its bandwidth enhancement and dynamic pole tracking, ensures higher bandwidth across the entire dynamic range of the input signal, thereby achieving excellent bandwidth and sensitivity performance, significantly improving chip security and signal transmission quality. To better understand the above-mentioned objects, features, and advantages of this disclosure, the solutions of this disclosure will be further described below. It should be noted that, unless otherwise specified, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] Figure 1 This is a circuit diagram illustrating the application of this patent in bandwidth enhancement and dynamic pole tracking of burst transimpedance amplifiers, as shown below. Figure 1As shown, it includes a core loop module and a bandwidth enhancement module. The input terminal of the core loop module forms the input terminal of the transimpedance amplifier bandwidth circuit, and the output terminal of the core loop module forms the output terminal of the transimpedance amplifier bandwidth circuit. The core loop module and the bandwidth enhancement module are connected. The input terminal of the core loop module receives the current to be processed, and in conjunction with the bandwidth enhancement module, converts the current to be processed to obtain the corresponding voltage, which is output by the output terminal of the core loop module, thereby reducing the link bandwidth of the transimpedance amplifier bandwidth circuit for the current to be processed.

[0015] The core loop module includes a current mirror I1, a current mirror I2, an NMOS transistor M1, an NMOS transistor M2, a gate capacitor C1, resistors R1 and R2, and variable resistors R3, R4, and R5. The bandwidth enhancement module includes a current mirror I3, NMOS transistors 4, M5, M6, M7, and M8, a PMOS transistor M9 and M10, and resistors R6, R7, and R8. The gate of NMOS transistor M1 is connected to one end of resistor R2 and one end of variable resistor R3; this connection point is the input terminal of the core loop module, forming the input terminal of the transimpedance amplifier bandwidth circuit, used to receive the current to be processed. The source terminals of OS transistors M1, M7, M5, and M6, one end of resistor R1, and the negative terminal of current mirror I3 are connected and grounded. The drain terminal of NMOS transistor M1, the negative terminal of current mirror I2, one end of gate capacitor C1, and the source terminal of NMOS transistor M2 are connected. The drain terminal of NMOS transistor M2 is connected to one end of resistor R4, one end of variable resistor R5, and the gate terminal of NMOS transistor M4. The source terminal of NMOS transistor M4 is connected to the other end of resistor R2, the other end of variable resistor R3, the gate terminal of NMOS transistor M7, and the drain terminal of NMOS transistor M5. This connection point is the core loop module. The output terminal of the block forms the output terminal of the transimpedance amplifier bandwidth circuit, outputting the voltage. The drain terminal of NMOS transistor M7 is connected to the source terminal of NMOS transistor M8. The gate terminal of NMOS transistor M5 is connected to the gate terminal of NMOS transistor M6, the drain terminal of NMOS transistor M6, and the drain terminal of PMOS transistor M9. The other end of resistor R4 is connected to the other end of variable resistor R5, the positive terminal of current mirror I2, and the positive terminal of current mirror I1. The negative terminal of current mirror I1, the drain terminal of NMOS transistor M3, the gate terminal of NMOS transistor M3, the gate terminal of NMOS transistor M2, and the gate terminal of NMOS transistor M8 are connected. The source terminal of NMOS transistor M3 is connected to the other end of resistor R1. The terminals are connected as follows: the other end of the gate capacitor C1, the drain terminal of NMOS transistor M8, and one end of resistor R6 are connected; the drain terminal of NMOS transistor M4, the source terminal of PMOS transistor M9, and one end of resistor R7 are connected; the other end of resistor R6 is connected to the other end of resistor R7 and one end of resistor R8; the other end of resistor R8 is connected to the source of PMOS transistor M10; the gate terminal of PMOS transistor M9, the gate terminal of PMOS transistor M10, and the drain terminal of PMOS transistor M10 are connected to the positive terminal of current mirror I3; This also includes a bandwidth enhancement function module and a dynamic pole compensation function module; NMOS transistor M5, NMOS transistor M7, PMOS transistor M9, and resistor R7 constitute the bandwidth enhancement function module.NMOS transistors M7 and M8, resistor R6, and capacitor C1 constitute a dynamic pole compensation module. The link bandwidth of this circuit is limited at the input IN by resistors R2, R3, R4, and R5, the transconductance gm1 of NMOS transistor M1, and the gate capacitance C1, as well as the gate-to-ground equivalent capacitance of NMOS transistor M4. At the output, it is limited by the transconductances gm4 and gm1 of NMOS transistors M4 and M1, and resistors R4 and R5. For this feedback architecture transimpedance amplifier, to achieve optimal bandwidth performance, the amplifier pole frequency in the feedback loop is set to twice the input pole frequency, thus achieving a 50% bandwidth improvement under acceptable link overshoot. However, once the size of NMOS transistor M4 is determined, the Miller effect between its gate and drain causes an increase in the gate equivalent capacitance of M4, resulting in a decrease in the closed-loop amplifier pole frequency. Furthermore, regarding dynamic characteristics, since the variable resistors R3 and R5 need to decrease as the input signal amplitude increases, the poles of the closed-loop system (the gate of NMOS transistor M4) increase with the signal amplitude, while the input poles remain unchanged when R3 and R5 change synchronously. This will cause the closed-loop amplifier pole frequency to no longer be twice the input pole frequency when the input swing increases, resulting in a reduction in link bandwidth.

[0016] To address the aforementioned issues, this invention developed a circuit for output stage bandwidth enhancement and dynamic pole tracking, as shown in the block diagram below. Figure 1 As shown, the core loop of the transimpedance amplifier consists of NMOS transistors M1, M2, M3, M4, and M5, resistors R2, R3, R4, and R5, and current mirrors I1 and I2. The bandwidth enhancement function consists of NMOS transistors M6, M9, and M10, resistors R7 and R8, and current mirror I3. The loop pole-tracking function consists of NMOS transistors M7 and M8, resistor R6, and capacitor C1.

[0017] The bandwidth enhancement function is described as follows: Under the action of the feedback loop formed by NMOS transistors M5 and M7, PMOS transistor M9, and resistor R7, a negative impedance is introduced into the equivalent impedance at the output terminal OUT of the core amplifier, reducing the equivalent impedance at the output terminal and increasing the pole frequency. Simultaneously, the source of PMOS transistor M9 is connected to the drain of NMOS transistor M4. The low source impedance characteristic of PMOS transistor M9 reduces the Miller effect of the gate-drain capacitance of NMOS transistor M4, lowering the gate-to-equivalent capacitance of NMOS transistor M4 and increasing the pole frequency of the feedback amplifier.

[0018] The dynamic pole compensation function is described as follows: Under the action of the feedback loop formed by NMOS transistors M7 and M8, resistor R6, and capacitor C1, the increase in the input signal will reduce resistors R3 and R5, and at the same time reduce the voltage value of the output terminal OUT, resulting in a decrease in the bias current of NMOS transistors M7 and M8. This leads to an increase in the gain of the amplifier formed by NMOS transistors M7 and M8 and resistor R6, which in turn increases the Miller effect of capacitor C1. After capacitor C1 is multiplied, it is equivalent to the gate of NMOS transistor M4 through NMOS transistor M2. The dynamic compensation resistor R5 reduces the influence on the pole frequency of the closed-loop amplifier. Furthermore, since capacitor C1 is connected to the source of NMOS transistor M2 instead of the gate of NMOS transistor M4, the feedforward zero of capacitor C1 can be eliminated, improving the loop stability.

[0019] The performance improvement applied to high-speed burst transimpedance amplifier circuits is as follows: Figure 2 and Figure 3 As shown, Figure 3 The link bandwidth performance is shown when the average input current is 10uA. The bandwidth enhancement technology of this invention increases the bandwidth from 1.82GHz (M2 curve) to 2.26GHz (M1 curve) with the same core device parameters. Figure 2 The link bandwidth performance is shown when the average input current is 1mA. Under the condition that the core device parameters are the same, the dynamic pole tracking technology of this invention increases the bandwidth from 1.99GHz (M5 curve) to 2.42GHz (M3 curve). It can be seen that the bandwidth enhancement function and dynamic pole compensation function of this invention are effective.

Claims

1. A bandwidth enhancement and dynamic pole tracking circuit for a high-speed burst-mode transimpedance amplifier, characterized in that, It includes a core loop module and a bandwidth enhancement module. The input terminal of the core loop module forms the input terminal of the transimpedance amplifier bandwidth circuit, and the output terminal of the core loop module forms the output terminal of the transimpedance amplifier bandwidth circuit. The core loop module and the bandwidth enhancement module are connected. The input terminal of the core loop module receives the current to be processed, and in conjunction with the bandwidth enhancement module, it converts the current to be processed to obtain the corresponding voltage, which is output by the output terminal of the core loop module, thereby reducing the link bandwidth of the transimpedance amplifier bandwidth circuit for the current to be processed. The core loop module includes current mirror I1, current mirror I2, NMOS transistor M1, NMOS crystal M2, gate capacitor C1, resistor R1, resistor R2, variable resistor R3, resistor R4, and variable resistor R5; The bandwidth enhancement module includes a current mirror I3, NMOS transistors 4, M5, M6, M7, and M8, PMOS transistors M9 and M10, and resistors R6, R7, and R8. The gate of NMOS transistor M1 is connected to one end of resistor R2 and one end of variable resistor R3. This connection point is the input terminal of the core loop module, which forms the input terminal of the transimpedance amplifier bandwidth circuit and is used to receive the current to be processed. The sources of NMOS transistors M1, M7, M5, and M6, one end of resistor R1, and the negative terminal of current mirror I3 are connected together and grounded. The drain of NMOS transistor M1, the negative terminal of current mirror I2, one end of gate capacitor C1, and the source of NMOS transistor M2 are connected together. The drain of NMOS transistor M2 is connected to one end of resistor R4, one end of variable resistor R5, and the gate of NMOS transistor M4. The source terminal of transistor M4 is connected to the other end of resistor R2, the other end of variable resistor R3, the gate terminal of NMOS transistor M7, and the drain terminal of NMOS transistor M5. This connection point is the output terminal of the core loop module, forming the output terminal of the transimpedance amplifier bandwidth circuit, which outputs the voltage. The drain terminal of NMOS transistor M7 is connected to the source terminal of NMOS transistor M8. The gate terminal of NMOS transistor M5 is connected to the gate terminal of NMOS transistor M6, the drain terminal of NMOS transistor M6, and the drain terminal of PMOS transistor M9. The other end of resistor R4 is connected to the other end of variable resistor R5, the positive terminal of current mirror I2, and the positive terminal of current mirror I1. The negative terminal of current mirror I1, the drain terminal of NMOS transistor M3, the gate terminal of NMOS transistor M3, the gate terminal of NMOS transistor M2, and the gate terminal of NMOS transistor M8 are connected. The source terminal of NMOS transistor M3 is connected to the other end of resistor R1. The other end of the gate capacitor C1, the drain terminal of NMOS transistor M8, and one end of resistor R6 are connected together. The drain terminal of NMOS transistor M4, the source terminal of PMOS transistor M9, and one end of resistor R7 are connected together. The other end of resistor R6 is connected to the other end of resistor R7 and one end of resistor R8. The other end of resistor R8 is connected to the source of PMOS transistor M10. The gate terminal of PMOS transistor M9, the gate terminal of PMOS transistor M10, and the drain terminal of PMOS transistor M10 are connected to the positive terminal of current mirror I3. The system also includes a bandwidth enhancement module and a dynamic pole compensation module. NMOS transistors M5, M7, M9, and R7 constitute the bandwidth enhancement module. NMOS transistors M7 and M8, R6, and capacitor C1 constitute the dynamic pole compensation module.

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