A frequency band reconfigurable high-isolation low-insertion-loss switch chip and a control method thereof

Abstract

The application provides a frequency band reconfigurable high-isolation low-insertion-loss switch chip and a control method, which comprises a substrate material, GaNFET, a port transmission line, a matching transmission line, an open short stub, a ground via and the like, FET1-FET16 are field effect tubes and are used for realizing switch port switching; the drain, the source and the gate surface metal layer of the GaNFET die are used for connecting the die gate, the source and the drain to the surface metal circuit through ohmic contact to lead out corresponding electrodes; the ground via is used for realizing GaNFET source grounding; the port transmission line is used for realizing external connection of the internal circuit of the chip; the matching transmission lines are used for realizing impedance matching of each port to obtain good chip performance; the open short stub is used for realizing in-band transmission zero point of the multifunctional switch chip to realize amplitude suppression of the corresponding frequency band; the control signal is a GaNFET gate control signal and is used for realizing control of the on-off state of the corresponding FET. The application has the advantages of low insertion loss, miniaturization, high power bearing and low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of automobile handling, in particular to a high-isolation low-insertion-loss switch chip with reconfigurable frequency bands. BACKGROUND

[0002] High-power switches are generally used in ultra-wideband TR components to realize the function of transceiver conversion, and need to have the technical features of miniaturization, low insertion loss, high isolation, etc. In view of the current multi-functional TR component transceiver hot switching operation, it is required that the transmit noise cannot affect the receive sensitivity, and at the same time the wideband TR component needs to have the ability of in-band low harmonic emission, so a high-power switch is needed, which has the ability of high isolation and reconfigurable frequency band.

[0003] In order to realize the miniaturization of the TR component, the high-power switch therein is generally implemented by a GaN FET switch in chip form, and its topology structure is generally implemented by a series-parallel or parallel structure. The GaN FET switch with a series-parallel structure has the advantage of ultra-wideband, but the isolation is relatively low. In order to improve the isolation of the GaN switch, a multi-stage switch structure is generally used, which will increase the insertion loss of the switch. The GaN FET switch with a parallel structure has the advantage of low insertion loss, but the operating bandwidth can only achieve 3 octaves, and in order to improve the withstand power of the switch, a plurality of GaN FETs are generally connected in series to improve the breakdown voltage, which will lengthen the channel length when the FET is turned on and deteriorate the isolation of the switch, and will also increase the insertion loss.

[0004] At the same time, the conventional GaN FET high-power switch generally has a fixed operating bandwidth and cannot realize frequency band reconfiguration, and does not have the function of dynamically suppressing a specific frequency band. The conventional TR component scheme for realizing in-band low harmonic emission generally uses a switch + band-stop filter scheme (see attached Figure 3 ), which has the disadvantages of large size and large insertion loss. Therefore, the existing GaN FET switch chip does not meet the application requirements of the new generation of TR components. SUMMARY

[0005] The present application aims to at least solve one of the technical problems in the prior art that the existing GaN FET switch chip cannot meet the application requirements of the new generation of TR components, cannot realize frequency band reconfiguration, does not have the function of dynamically suppressing a specific frequency band, has relatively low isolation, and has large switch insertion loss.

[0006] To this end, the first aspect of the present application provides a high-isolation low-insertion-loss switch chip with reconfigurable frequency bands.

[0007] The second aspect of the present application provides a control method for a high-isolation low-insertion-loss switch chip with reconfigurable frequency bands.

[0008] The application provides a high-isolation low-insertion-loss switch chip with frequency band reconfiguration, comprising: a substrate material, GaN FETs, port transmission lines, matching transmission lines and open stubs; the GaN FETs comprise FET1-FET16, and the FET1-FET16 are integrally arranged on the substrate material;

[0009] The chip surface is integrally provided with port transmission lines 1-3, matching transmission lines 1-1, matching transmission lines 1-2, matching transmission lines 2-1, matching transmission lines 2-2, matching transmission line 3, open stubs 1-1-1-4, open stubs 2-1-2-4 and ground vias;

[0010] One end of the port transmission line 3 is a switch common radio frequency port RFc, and the other end is connected to one end of the matching transmission line 3; the other end of the matching transmission line 3 is connected to one end of the matching transmission line 1-2 and one end of the matching transmission line 2-2, respectively;

[0011] The other end of the matching transmission line 1-2 is connected to one end of the matching transmission line 1-1; FET6 and FET7 are connected in parallel between the matching transmission line 1-1 and the matching transmission line 1-2; FET6 is connected to FET5, FET5 is connected to the ground via, and open stub 1-2 is connected in parallel between FET6 and FET5; FET7 is connected to FET8, FET8 is connected to the ground via, and open stub 1-4 is connected in parallel between FET7 and FET8;

[0012] The other end of the matching transmission line 1-1 is connected to one end of the port transmission line 1; the other end of the port transmission line 1 is a radio frequency port RF1; FET2 and FET3 are connected in parallel between the matching transmission line 1-1 and the port transmission line 1; FET2 is connected to FET1, FET1 is connected to the ground via, and open stub 1-1 is connected in parallel between FET2 and FET1; FET3 is connected to FET4, FET4 is connected to the ground via, and open stub 1-2 is connected in parallel between FET3 and FET4;

[0013] The other end of the matching transmission line 2-2 is connected to one end of the matching transmission line 2-1; FET10 and FET11 are connected in parallel between the matching transmission line 2-2 and the matching transmission line 2-1; FET10 is connected to FET9, FET9 is connected to the ground via, and open stub 2-3 is connected in parallel between FET10 and FET9; FET11 is connected to FET12, FET12 is connected to the ground via, and open stub 2-4 is connected in parallel between FET11 and FET12;

[0014] The other end of the matching transmission line 2-1 is connected with one end of a port transmission line 2, and the other end of the port transmission line 2 is a radio frequency port RF2; FET 14 and FET 15 are connected in parallel between the matching transmission line 2-1 and the port transmission line 2, FET 14 is connected with FET 13, FET 13 is connected with a ground via hole, and an open stub 2-1 is connected in parallel between FET 14 and FET 13; FET 15 is connected with FET 16, FET 16 is connected with a ground via hole, and an open stub 2-2 is connected in parallel between FET 15 and FET 16;

[0015] FET1, FET4, FET5, FET8 are connected with control signal Vg1-1; FET2, FET3, FET6, FET7 are connected with control signal Vg1-2; FET9, FET12, FET13, FET16 are connected with control signal Vg2-2; FET10, FET11, FET14, FET15 are connected with control signal Vg2-1.

[0016] According to the frequency band reconfigurable high-isolation low-insertion-loss switch chip of the technical scheme, the following additional technical features can be further provided:

[0017] Further, the drain D of FET6 is connected with the matching transmission line 1-1 and the matching transmission line 1-2 respectively, the source of FET6 is connected with the drain of FET5, and the source of FET5 is connected with a ground via hole; the drain D of FET7 is connected with the matching transmission line 1-1 and the matching transmission line 1-2 respectively, the source of FET7 is connected with the drain of FET8, and the source of FET8 is connected with a ground via hole.

[0018] The drain D of FET2 is connected with the matching transmission line 1-1 and the port transmission line 1 respectively, the source of FET2 is connected with the drain of FET1, and the source of FET1 is connected with a ground via hole; the drain D of FET3 is connected with the matching transmission line 1-1 and the port transmission line 1 respectively, the source of FET3 is connected with the drain of FET4, and the source of FET4 is connected with a ground via hole.

[0019] The drain D of FET10 is connected with the matching transmission line 2-2 and the matching transmission line 2-1 respectively, the source of FET10 is connected with the drain of FET9, and the source of FET9 is connected with a ground via hole; the drain D of FET11 is connected with the matching transmission line 2-2 and the matching transmission line 2-1 respectively, the source of FET11 is connected with the drain of FET12, and the source of FET12 is connected with a ground via hole.

[0020] The drain D of the FET 14 is connected with the matching transmission line 2-1 and the port transmission line respectively, the source of the FET 14 is connected with the drain of the FET 13, and the source of the FET 13 is connected with the ground via hole; the drain D of the FET 15 is connected with the matching transmission line 2-1 and the port transmission line respectively, the source of the FET 15 is connected with the drain of the FET 16, and the source of the FET 16 is connected with the ground via hole.

[0021] Further, the gates of the FET 1, the FET 4, the FET 5 and the FET 8 are connected with the control signal Vg1-1; the gates of the FET 2, the FET 3, the FET 6 and the FET 7 are connected with the control signal Vg1-2; the gates of the FET 9, the FET 12, the FET 13 and the FET 16 are connected with the control signal Vg2-2; and the gates of the FET 10, the FET 11, the FET 14 and the FET 15 are connected with the control signal Vg2-1.

[0022] Further, the FET 6 and the FET 7 are arranged on both sides of the transmission line; and / or, the FET 10 and the FET 11 are arranged on both sides of the transmission line; and / or, the FET 2 and the FET 3 are arranged on both sides of the transmission line; and / or, the FET 14 and the FET 15 are arranged on both sides of the transmission line.

[0023] Further, the FET 5 and the FET 6 are arranged on the same side of the transmission line, and the FET 7 and the FET 8 are arranged on the other side of the transmission line; and / or, the FET 9 and the FET 10 are arranged on the same side of the transmission line, and the FET 11 and the FET 12 are arranged on the other side of the transmission line; and / or, the FET 1 and the FET 2 are arranged on the same side of the transmission line, and the FET 3 and the FET 4 are arranged on the other side of the transmission line; and / or, the FET 13 and the FET 14 are arranged on the same side of the transmission line, and the FET 15 and the FET 16 are arranged on the other side of the transmission line.

[0024] Further, the FET 1 to the FET 16 are field effect tubes, which are used to realize switching port switching.

[0025] Further, the surfaces of the drain, the source and the gate of the GaN FET die are provided with metal layers, which are used to lead out electrodes of the gate, the source and the drain of the GaN FET die through ohmic contact and connect with the chip surface metal circuit.

[0026] Further, the matching transmission line 1-1, the matching transmission line 1-2, the matching transmission line 2-1, the matching transmission line 2-2 and the matching transmission line 3 are used to realize impedance matching.

[0027] The port transmission line 1 to the port transmission line 3 are used to realize external connection of the internal circuit of the chip.

[0028] The open stub 1-1~open stub 1-4, open stub 2-1~open stub 2-4 are used to realize that the chip generates an in-band transmission zero point, and realize the amplitude suppression of the corresponding frequency band, and the length is one quarter of the wavelength of the corresponding trap frequency band.

[0029] Further, the control signals Vg1-1, Vg1-2, Vg2-1, Vg2-2 are used to realize the control of the on-off state of the FET.

[0030] The application further provides a control method of a frequency band reconfigurable high-isolation low-insertion-loss switch chip, which is applied to the frequency band reconfigurable high-isolation low-insertion-loss switch chip as described in the above technical solution, and when the chip works in a switch switching state, the control method comprises the following steps:

[0031] 1) When the switch is switched to RFc→RF1, the control signals Vg1-1 and Vg1-2 make FET1~FET8 in the off state, the control signals Vg2-1 and Vg2-2 make FET9~FET16 in the on state, so that the switch port RFc to RF1 is turned on;

[0032] 2) When the switch is switched to RFc→RF2, the control signals Vg1-1 and Vg1-2 make FET1~FET8 in the on state, the control signals Vg2-1 and Vg2-2 make FET9~FET16 in the off state, so that the switch port RFc to RF2 is turned on;

[0033] When the chip works in the switch switching state and needs to suppress the corresponding frequency band, the control method comprises the following steps:

[0034] 1) When the switch is switched to RFc→RF1 and needs to suppress the corresponding frequency band, the control signal Vg1-1 makes FET1, FET4, FET5, FET8 in the off state, the control signal Vg1-2 makes FET2, FET3, FET6, FET7 in the on state, realizes that the open stub 1-1~open stub 1-4 are introduced into the circuit, according to the length and width of the open stub, the corresponding frequency band suppression function can be realized, the control signals Vg2-1 and Vg2-2 make FET9~FET16 in the on state, so that the switch port RFc to RF1 is turned on;

[0035] 2) When the switch is switched to RFc→RF2 and the corresponding frequency band suppression is needed, the control signal Vg2-1 makes FET9, FET12, FET13 and FET16 in the off state, the control signal Vg2-2 makes FET10, FET11, FET14 and FET15 in the on state, the open stub 2-1~open stub 2-4 is introduced into the circuit, the corresponding frequency band suppression function can be realized according to the length and width of the open stub, the control signals Vg1-1 and Vg1-2 make FET1~FET8 in the on state, so that the switch port RFc to RF2 can be turned on.

[0036] In summary, due to the adoption of the above technical features, the beneficial effects of the present application are:

[0037] The circuit of the present application has been verified in a 2~6GHz ultra-wideband SPDT, and can realize switch switching through the control signal, and can realize 4~6GHz frequency band 30dBc amplitude suppression when the frequency band is suppressed, the insertion loss is not more than 1.5dB, and the power bearing is more than 100W.

[0038] The high-power switch circuit topology is a single-pole double-throw switch, and the wave trap circuit is integrated, and the main function is to realize switch switching and wave trap of the corresponding frequency band, such as realizing in-band second harmonic suppression of the transmit signal in the ultra-wideband transceiver assembly.

[0039] A frequency band reconfigurable high-isolation low-insertion-loss multifunctional switch chip is realized, which is designed in an integrated design mode of GaN-based FET, open stub and matching transmission line, can realize switch switching function and corresponding frequency band amplitude suppression function, compared with the traditional switch+filter structure, can realize frequency band reconfiguration, has dynamic suppression function for specific frequency band, relatively high isolation, and small switch insertion loss; has the advantages of low insertion loss, miniaturization, high bearing power and low cost.

[0040] Additional aspects and advantages of the present application will become apparent in the light of the following description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0041] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0042] Figure 1 is a circuit principle schematic diagram of a frequency band reconfigurable high-isolation low-insertion-loss switch chip of one embodiment of the present application;

[0043] Figure 2 is a structure layout schematic diagram of a frequency band reconfigurable high-isolation low-insertion-loss switch chip of one embodiment of the present application;

[0044] Figure 3 is a schematic diagram of a traditional frequency band reconfigurable switch circuit principle. DETAILED DESCRIPTION

[0045] In order to enable a more clear understanding of the above-mentioned objects, features and advantages of the present application, the present application will be further described in details below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0046] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, however, the present application can also be implemented in other different manners from those described herein, and therefore, the protection scope of the present application is not limited by the specific embodiments disclosed below.

[0047] The frequency band reconfigurable high-isolation low-insertion-loss switch chip and the control method of the frequency band reconfigurable high-isolation low-insertion-loss switch chip according to some embodiments of the present application will be described below with reference to the accompanying drawings. Figures 1 to 2

[0048] Some embodiments of the present application provide a frequency band reconfigurable high-isolation low-insertion-loss switch chip.

[0049] As shown in Figures 1 to 2 , the first embodiment of the present application proposes a frequency band reconfigurable high-isolation low-insertion-loss switch chip, the circuit of which mainly consists of a substrate material, GaN FET, port transmission line, matching transmission line, open short stub.

[0050] GaN FET is adopted to realize high-power switching; the substrate material can be Si or SiC; GaN-based FET1-FET16 tube cells are integrated on the substrate material through epitaxial growth, diffusion, doping, photolithography and other processes, and the tube cell structure and parameters can be determined according to specific requirements; the drain, source and gate surface metal layers of the GaN FET die are integrated on the surface of the chip to realize corresponding ohmic contact, and a ground via is also integrated.

[0051] As shown in Figure 1 , the chip surface is integrated with port transmission lines 1-3, matching transmission lines 1-1, matching transmission lines 1-2, matching transmission lines 2-1, matching transmission lines 2-2, matching transmission line 3, open short stubs 1-1-1-4, open short stubs 2-1-2-4;

[0052] One end of the port transmission line 3 is a switch common radio frequency port RFc, and the other end is connected to one end of the matching transmission line 3, and the other end of the matching transmission line 3 is connected to the matching transmission line 1-2 and the matching transmission line 2-2, respectively; ​

[0053] The other end of the matching transmission line 1-2 is connected to one end of the matching transmission line 1-1, and FET 6 and FET 7 are connected in parallel between the matching transmission lines 1-1 and 1-2, FET 6 and FET 7 are arranged on both sides of the transmission line, the drain D of FET 6 is connected to the transmission line, the source of FET 6 is connected to the drain of FET 5, the source of FET 5 is connected to the ground via hole, and open stub 1-2 is connected in parallel between FET 6 and FET 5; similarly, the drain D of FET 7 is connected to the transmission line, the source of FET 7 is connected to the drain of FET 8, the source of FET 8 is connected to the ground via hole, and open stub 1-4 is connected in parallel between FET 7 and FET 8;

[0054] The other end of the matching transmission line 1-1 is connected to one end of the port transmission line 1, and the other end of the port transmission line 1 is the radio frequency port RF1, FET 2 and FET 3 are connected in parallel between the matching transmission line 1-1 and the port transmission line 1, FET 2 and FET 3 are arranged on both sides of the transmission line, the drain D of FET 2 is connected to the transmission line, the source of FET 2 is connected to the drain of FET 1, the source of FET 1 is connected to the ground via hole, and open stub 1-1 is connected in parallel between FET 2 and FET 1; similarly, the drain D of FET 3 is connected to the transmission line, the source of FET 3 is connected to the drain of FET 4, the source of FET 4 is connected to the ground via hole, and open stub 1-2 is connected in parallel between FET 3 and FET 4;

[0055] The other end of the matching transmission line 2-2 is connected to one end of the matching transmission line 2-1, and FET 10 and FET 11 are connected in parallel between the matching transmission lines 2-2 and 2-1, FET 10 and FET 11 are arranged on both sides of the transmission line, the drain D of FET 10 is connected to the transmission line, the source of FET 10 is connected to the drain of FET 9, the source of FET 9 is connected to the ground via hole, and open stub 2-3 is connected in parallel between FET 10 and FET 9; similarly, the drain D of FET 11 is connected to the transmission line, the source of FET 11 is connected to the drain of FET 12, the source of FET 12 is connected to the ground via hole, and open stub 2-4 is connected in parallel between FET 11 and FET 12;

[0056] The other end of the matching transmission line 2-1 is connected with one end of a port transmission line 2, and the other end of the port transmission line 2 is a radio frequency port RF2; FETs 14 and 15 are connected in parallel between the matching transmission line 2-1 and the port transmission line 2, and the FETs 14 and 15 are arranged on both sides of the transmission line; the drain D of the FET 14 is connected with the transmission line, the source of the FET 14 is connected with the drain of the FET 13, the source of the FET 13 is connected with a ground via, and an open stub 2-1 is connected in parallel between the FET 14 and the FET 13; similarly, the drain D of the FET 15 is connected with the transmission line, the source of the FET 15 is connected with the drain of the FET 16, the source of the FET 16 is connected with a ground via, and an open stub 2-2 is connected in parallel between the FET 15 and the FET 16.

[0057] The GaN FETs 1, 4, 5 and 8 form a group, and the gates thereof are controlled by a control signal Vg1-1; the GaN FETs 2, 3, 6 and 7 form a group, and the gates thereof are controlled by a control signal Vg1-2; the GaN FETs 9, 12, 13 and 16 form a group, and the gates thereof are controlled by a control signal Vg2-2; and the GaN FETs 10, 11, 14 and 15 form a group, and the gates thereof are controlled by a control signal Vg2-1.

[0058] The second embodiment of the present application provides a frequency band reconfigurable high-isolation low-insertion-loss switch chip, and on the basis of the first embodiment, as shown in the figure, Figures 1 to 2 The FETs 1-16 are field effect tubes, which are mainly used as switch control elements, and the structure and device parameters thereof can be designed according to actual application requirements; the drain, source and gate surface metal layers of the GaN FET die are mainly used for connecting the corresponding electrodes of the die gate, source and drain to the surface metal circuit of the chip through ohmic contact, and the material and pattern structure of the metal layer are designed according to specific requirements.

[0059] The ground via is a metallized ground via, which is used for realizing GaN FET source grounding, and the aperture size and depth-diameter ratio are determined according to process capability;

[0060] The third embodiment of the present application provides a frequency band reconfigurable high-isolation low-insertion-loss switch chip, and on the basis of any of the above embodiments, as shown in the figure, Figures 1 to 2 The port transmission lines 1-3 are transmission lines with a characteristic impedance of 50 ohms, which are used for realizing the external connection of the internal circuit of the chip, and the length thereof is determined according to the layout of the output port of the chip;

[0061] The matching transmission line 1-1, the matching transmission line 1-2, the matching transmission line 2-1, the matching transmission line 2-2 and the matching transmission line 3 are all for realizing impedance matching, and are used for obtaining good chip performance, the line width and length thereof are related to the working frequency band of the chip and the radio frequency parameter of the GaN-based FET, and can be obtained through software simulation optimization;

[0062] The open-circuit stub 1-1 to the open-circuit stub 1-4, the open-circuit stub 2-1 to the open-circuit stub 2-4 are mainly used for realizing that the multi-functional switch chip generates a transmission zero point in a band, and realizes amplitude suppression of a corresponding frequency band, and are generally high-impedance lines, and the characteristic impedance is generally between 100 ohms and 200 ohms, and the length is one quarter of the wavelength of the corresponding wave-trapping frequency band;

[0063] The fourth embodiment of the present application provides a frequency band reconfigurable high-isolation low-insertion-loss switch chip, and is based on any one of the above embodiments, as shown in the figure, Figures 1 to 2 The control signal Vg1-1, Vg1-2, Vg2-1 and Vg2-2 are GaN-based FET gate control signals, and are used for realizing control of the on-off state of the corresponding FET, the voltage type should be determined according to the type of the GaN-based FET, and is generally 0V / -20V to -40V, the current driving capability of the control signal is generally mA level, and the instantaneous current is generally 10mA level.

[0064] Some embodiments of the present application provide a control method of a frequency band reconfigurable high-isolation low-insertion-loss switch chip.

[0065] The fifth embodiment of the present application provides a control method of a frequency band reconfigurable high-isolation low-insertion-loss switch chip, and is based on any one of the above embodiments, as shown in the figure, Figures 1 to 2 When the chip works in a switch switching state, the control signal Vg1-1 and Vg1-2 make the FET1 to FET8 in the off state, the control signal Vg2-1 and Vg2-2 make the FET9 to FET16 in the on state, so that the switch port RFc to RF1 is turned on.

[0066] 1) When the switch is switched to RFc→RF1, the control signal Vg1-1 and Vg1-2 make the FET1 to FET8 in the off state, the control signal Vg2-1 and Vg2-2 make the FET9 to FET16 in the on state, so that the switch port RFc to RF1 is turned on.

[0067] 2) When the switch is switched to RFc→RF2, the control signal Vg1-1 and Vg1-2 make the FET1 to FET8 in the on state, the control signal Vg2-1 and Vg2-2 make the FET9 to FET16 in the off state, so that the switch port RFc to RF2 is turned on.

[0068] When the chip works in a switch switching state and needs to suppress the corresponding frequency band, the control signal Vg1-1 and Vg1-2 make the FET1 to FET8 in the off state, the control signal Vg2-1 and Vg2-2 make the FET9 to FET16 in the on state, so that the switch port RFc to RF1 is turned on.

[0069] 1) When the switch is switched to RFc→RF1 and the corresponding frequency band suppression is needed, the control signal Vg1-1 makes FET1, FET4, FET5, FET8 in the off state, the control signal Vg1-2 makes FET2, FET3, FET6, FET7 in the on state, which realizes the introduction of open stub 1-1~open stub 1-4 into the circuit, according to the length and width of the open stub, the corresponding frequency band suppression function can be realized, the control signal Vg2-1 and Vg2-2 makes FET9~FET16 in the on state, so that the switch port RFc to RF1 can be turned on;

[0070] 2) When the switch is switched to RFc→RF2 and the corresponding frequency band suppression is needed, the control signal Vg2-1 makes FET9, FET12, FET13, FET16 in the off state, the control signal Vg2-2 makes FET10, FET11, FET14, FET15 in the on state, which realizes the introduction of open stub 2-1~open stub 2-4 into the circuit, according to the length and width of the open stub, the corresponding frequency band suppression function can be realized, the control signal Vg1-1 and Vg1-2 makes FET1~FET8 in the on state, so that the switch port RFc to RF2 can be turned on.

[0071] In this specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0072] Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A frequency band reconfigurable, high-isolation, low-insertion-loss switching chip, characterized in that, include: The components include a substrate material, a GaN FET, a port transmission line, a matching transmission line, and an open-circuit stub; the GaN FET includes FET1 to FET16, and FET1 to FET16 cells are integrated on the substrate material. The chip surface is integrated with port transmission lines 1~3, matching transmission lines 1-1, matching transmission lines 1-2, matching transmission lines 2-1, matching transmission lines 2-2, matching transmission lines 3, open circuit stubs 1-1~1-4, open circuit stubs 2-1~2-4 and a grounding via. One end of port transmission line 3 is the switch common radio frequency port RFc, and the other end is connected to one end of matching transmission line 3. The other end of matching transmission line 3 is connected to one end of matching transmission line 1-2 and one end of matching transmission line 2-2 respectively. The other end of the matching transmission line 1-2 is connected to one end of the matching transmission line 1-1. FET6 and FET7 are connected in parallel between the matching transmission line 1-1 and the matching transmission line 1-2. FET6 is connected to FET5, and FET5 is connected to the grounding via. Open circuit stub 1-2 is connected in parallel between FET6 and FET5. FET7 is connected to FET8, and FET8 is connected to the grounding via. Open circuit stub 1-4 is connected in parallel between FET7 and FET8. The other end of the matching transmission line 1-1 is connected to one end of the port transmission line 1. The other end of the port transmission line 1 is the radio frequency port RF1. FET2 and FET3 are connected in parallel between the matching transmission line 1-1 and the port transmission line 1. FET2 is connected to FET1, and FET1 is connected to the ground via. An open-circuit stub 1-1 is connected in parallel between FET2 and FET1. FET3 is connected to FET4, and FET4 is connected to the ground via. An open-circuit stub 1-3 is connected in parallel between FET3 and FET4. The other end of the matching transmission line 2-2 is connected to one end of the matching transmission line 2-1. FET10 and FET11 are connected in parallel between the matching transmission line 2-2 and the matching transmission line 2-1. FET10 is connected to FET9, and FET9 is connected to the grounding via. An open-circuit stub 2-3 is connected in parallel between FET10 and FET9. FET11 is connected to FET12, and FET12 is connected to the grounding via. An open-circuit stub 2-4 is connected in parallel between FET11 and FET12. The other end of the matching transmission line 2-1 is connected to one end of the port transmission line 2. The other end of the port transmission line 2 is the radio frequency port RF2. FET14 and FET15 are connected in parallel between the matching transmission line 2-1 and the port transmission line 2. FET14 is connected to FET13, and FET13 is connected to the ground via. An open-circuit stub 2-1 is connected in parallel between FET14 and FET13. FET15 is connected to FET16, and FET16 is connected to the ground via. An open-circuit stub 2-2 is connected in parallel between FET15 and FET16. FET1, FET4, FET5, and FET8 are connected to control signal Vg1-1; FET2, FET3, FET6, and FET7 are connected to control signal Vg1-2; FET9, FET12, FET13, and FET16 are connected to control signal Vg2-1; FET10, FET11, FET14, and FET15 are connected to control signal Vg2-2. The drain D of FET6 is connected to matching transmission line 1-1 and matching transmission line 1-2 respectively. The source of FET6 is connected to the drain of FET5. The source of FET5 is connected to the ground via. The drain D of FET7 is connected to matching transmission line 1-1 and matching transmission line 1-2 respectively. The source of FET7 is connected to the drain of FET8. The source of FET8 is connected to the ground via. The drain D of FET2 is connected to the matching transmission line 1-1 and the port transmission line 1, respectively. The source of FET2 is connected to the drain of FET1, and the source of FET1 is connected to the ground via. The drain D of FET3 is connected to the matching transmission line 1-1 and the port transmission line 1, respectively. The source of FET3 is connected to the drain of FET4, and the source of FET4 is connected to the ground via. The drain D of FET10 is connected to matching transmission line 2-2 and matching transmission line 2-1 respectively. The source of FET10 is connected to the drain of FET9. The source of FET9 is connected to the ground via. The drain D of FET11 is connected to matching transmission line 2-2 and matching transmission line 2-1 respectively. The source of FET11 is connected to the drain of FET12. The source of FET12 is connected to the ground via. The drain D of FET14 is connected to the matching transmission line 2-1 and the port transmission line 2, respectively. The source of FET14 is connected to the drain of FET13, and the source of FET13 is connected to the ground via. The drain D of FET15 is connected to the matching transmission line 2-1 and the port transmission line 2, respectively. The source of FET15 is connected to the drain of FET16, and the source of FET16 is connected to the ground via. Gate access control signal Vg1-1 for FET1, FET4, FET5, and FET8; gate access control signal Vg1-2 for FET2, FET3, FET6, and FET7; gate access control signal Vg2-1 for FET9, FET12, FET13, and FET16; gate access control signal Vg2-2 for FET10, FET11, FET14, and FET15.

2. The frequency band reconfigurable high isolation low insertion loss switch chip according to claim 1, characterized in that, FET6 and FET7 are arranged on both sides of the transmission line; and / or, FET10 and FET11 are arranged on both sides of the transmission line; and / or, FET2 and FET3 are arranged on both sides of the transmission line; and / or, FET14 and FET15 are arranged on both sides of the transmission line.

3. The frequency band reconfigurable high isolation low insertion loss switch chip according to claim 2, characterized in that, FET5 and FET6 are arranged on the same side of the transmission line, and FET7 and FET8 are arranged on the other side of the transmission line; and / or, FET9 and FET10 are arranged on the same side of the transmission line, and FET11 and FET12 are arranged on the other side of the transmission line; and / or, FET1 and FET2 are arranged on the same side of the transmission line, and FET3 and FET4 are arranged on the other side of the transmission line; and / or, FET13 and FET14 are arranged on the same side of the transmission line, and FET15 and FET16 are arranged on the other side of the transmission line.

4. A frequency band reconfigurable high-isolation low-insertion-loss switching chip according to any one of claims 1 to 3, characterized in that, FET1 to FET16 are field-effect transistors used to switch the switching ports.

5. A frequency band reconfigurable high-isolation low-insertion-loss switching chip according to any one of claims 1 to 3, characterized in that, The drain, source, and gate of a GaN FET die are provided with metal layers, which are used to lead out electrodes of the gate, source, and drain of the GaN FET die through ohmic contacts and connect them to the metal circuitry on the chip surface.

6. A frequency band reconfigurable high-isolation low-insertion-loss switch chip according to any one of claims 1 to 3, characterized in that, The matching transmission lines 1-1, 1-2, 2-1, 2-2, and 3 are used to achieve impedance matching. The port transmission lines 1-3 are used to connect the internal circuitry of the chip to the external environment; The open-circuit stubs 1-1 to 1-4 and 2-1 to 2-4 are used to generate in-band transmission zeros in the chip and achieve amplitude suppression in the corresponding frequency band. Their length is one-quarter of the wavelength of the corresponding notch band.

7. A frequency band reconfigurable high-isolation low-insertion-loss switching chip according to any one of claims 1 to 3, characterized in that, The control signals Vg1-1, Vg1-2, Vg2-1, and Vg2-2 are used to control the on / off state of the FET.

8. A control method for a frequency band reconfigurable high-isolation low-insertion-loss switch chip, applied to a frequency band reconfigurable high-isolation low-insertion-loss switch chip as described in any one of claims 1 to 7, characterized in that, When the chip is operating in a switching state, it includes: (1) When the switch is switched to RFc→RF1, the control signals Vg1-1 and Vg1-2 make FET1~FET8 in the off state, and the control signals Vg2-1 and Vg2-2 make FET9~FET16 in the on state, so that the switch port RFc to RF1 can be turned on. (2) When the switch is switched to RFc→RF2, the control signals Vg1-1 and Vg1-2 make FET1~FET8 in the on state, and the control signals Vg2-1 and Vg2-2 make FET9~FET16 in the off state, so that the switch port RFc to RF2 can be turned on. When the chip is operating in a switching state and needs to suppress the corresponding frequency band, including: (1) When the switch is switched to RFc→RF1 and corresponding frequency band suppression is required, the control signal Vg1-1 makes FET1, FET4, FET5, and FET8 in the off state, and the control signal Vg1-2 makes FET2, FET3, FET6, and FET7 in the on state, thus realizing the introduction of open circuit stubs 1-1 to 1-4 into the circuit. According to the length and width of the open circuit stubs, the corresponding frequency band suppression function can be realized. The control signals Vg2-1 and Vg2-2 make FET9 to FET16 in the on state, thus realizing the conduction from the switch port RFc to RF1. (2) When the switch is switched to RFc→RF2 and corresponding frequency band suppression is required, the control signal Vg2-1 makes FET9, FET12, FET13, and FET16 in the off state, and the control signal Vg2-2 makes FET10, FET11, FET14, and FET15 in the on state, thus realizing the introduction of open circuit stubs 2-1 to 2-4 into the circuit. According to the length and width of the open circuit stubs, the corresponding frequency band suppression function can be realized. The control signals Vg1-1 and Vg1-2 make FET1 to FET8 in the on state, thus realizing the conduction of the switch port RFc to RF2.

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