Circuit board and method for manufacturing the same

Abstract

A circuit board and a method for manufacturing the same include providing a copper-clad laminate, the copper-clad laminate including a first metal layer and a second metal layer as a base layer, the base layer including a circuit area, a resistor area, and a connection area; forming a resistor layer on the surface of the first metal layer corresponding to the resistor area, the resistor layer extending to the connection area; forming a first dielectric layer on the surface of the first metal layer, the resistor layer embedded in the first dielectric layer; forming a first opening in the base layer; removing the first metal layer corresponding to the first opening to form a second opening, and patterning the first and second metal layers to form a first circuit layer and a second circuit layer, the first circuit layer and the second circuit layer being electrically connected so that the resistor layer is electrically connected to the first and second circuit layers; disposing a second dielectric layer in the second opening; and disposing a first covering layer in the first opening, thereby obtaining a circuit board. The circuit board manufacturing method provided by the present invention simplifies the manufacturing process and improves the circuit board yield by embedding the resistor layer in a specific area.

Description

Technical Field

[0001] The present invention relates to a printed circuit board technology, and in particular to a circuit board and a manufacturing method thereof. Background Art

[0002] With the development requirements of intelligent, multifunctional, high-reliability, thin and small electronic products, embedded resistor technology is becoming more and more popular in the industry.

[0003] The traditional manufacturing method of embedded resistors mainly uses specific embedded resistor materials (such as Ohmega embedded resistor materials) to produce embedded resistors through circuit etching, resistor layer etching and alkaline etching. The manufacturing process is complicated; specific embedded resistor materials are required, which are expensive and increase the cost of the circuit board; the resistor layer is located below the circuit layer, and the bonding strength between the resistor layer (usually NiP) and the circuit layer (usually copper) and the substrate (usually polyimide) is poor, which poses a risk of poor foldability; the manufacturing processes of the resistor layer and the circuit layer interfere with each other, and the line width, line spacing and thickness uniformity of the resistor layer and the circuit layer are poor, thereby reducing the yield of the circuit board. Summary of the Invention

[0004] In view of this, in order to overcome at least one of the above-mentioned drawbacks, it is necessary to provide a method for manufacturing a circuit board with resistors embedded in a specific area.

[0005] In addition, the present invention also provides a circuit board manufactured using the above manufacturing method.

[0006] The present invention provides a method for manufacturing a circuit board, the method comprising the steps of:

[0007] A copper-clad laminate is provided, comprising a base layer and a first metal layer and a second metal layer provided on two opposite surfaces of the base layer. The base layer comprises a circuit area, a resistor area and a connection area provided between the circuit area and the resistor area.

[0008] A resistance layer is formed on a surface of the first metal layer corresponding to the resistance area, and the resistance layer extends to the connection area.

[0009] A first dielectric layer is formed on a surface of the first metal layer corresponding to the resistance area. The first dielectric layer extends to the connection area, and the resistance layer is embedded in the first dielectric layer.

[0010] The base layer corresponding to the resistance region is removed to form a first opening, wherein the first opening penetrates the second metal layer, and the first metal layer is exposed in the first opening.

[0011] The first metal layer exposed by the first opening is removed to form a second opening, the resistance layer is exposed in the second opening, and the first metal layer and the second metal layer are patterned to form a first circuit layer and a second circuit layer, respectively. The first circuit layer includes a first connection pad located in the connection area, and the second circuit layer includes a second connection pad located in the connection area. The first connection pad is electrically connected to the second connection pad so that the resistance layer is electrically connected to the first circuit layer and the second circuit layer.

[0012] A second dielectric layer is disposed in the second opening, and the second dielectric layer covers the resistance layer.

[0013] Furthermore, a first covering layer is disposed in the first opening and on the surface of the second dielectric layer, thereby obtaining the circuit board.

[0014] In the embodiment of the present application, before forming the resistance layer, the manufacturing method further includes:

[0015] A via hole is opened in the copper clad laminate corresponding to the connection area, and the via hole passes through the first metal layer and the base layer, so as to electrically connect the first metal layer and the second metal layer.

[0016] After forming the first dielectric layer, the manufacturing method further includes:

[0017] The first dielectric layer is extended to cover the via hole.

[0018] In the embodiment of the present application, after forming the first covering layer, the manufacturing method further includes:

[0019] A surface treatment layer is formed on the surface of the second connection pad.

[0020] In the embodiment of the present application, the method for manufacturing the resistance layer includes:

[0021] A first dry film is covered on the first metal layer.

[0022] The first dry film is exposed, developed and etched to form a patterned dry film.

[0023] The patterned area of ​​the patterned dry film is filled with a resistor material and cured to form a resistor layer.

[0024] and removing the patterned dry film.

[0025] In an embodiment of the present application, the thickness of the second dielectric layer is equal to the thickness of the first connection pad.

[0026] In the embodiment of the present application, the material of the resistance layer includes at least one of nickel-phosphorus alloy, carbon nanotubes, graphene and nanosilver.

[0027] The present invention also provides a circuit board, comprising: a base layer, a first circuit layer, a second circuit layer, a first dielectric layer, a second dielectric layer, and a resistor layer. The base layer comprises a circuit area, a resistor area, and a connection area between the circuit area and the resistor area, the base layer having a first opening corresponding to the resistor area, and a first covering layer disposed within the first opening; the first circuit layer is disposed on a first surface of the base layer, the first circuit layer comprising a first connection pad disposed corresponding to the connection area, and the first circuit layer having a second opening communicating with the first opening corresponding to the resistor area; the second circuit layer is disposed on a second surface of the base layer away from the first surface, the second circuit layer comprising a second connection pad disposed corresponding to the connection area, the first connection pad being electrically connected to the second connection pad; the second dielectric layer is disposed within the second opening and located on a surface of the first covering layer; the resistor layer is disposed on a surface of the second dielectric layer, the resistor area extending to the surface of the first connection pad so as to electrically connect the resistor layer to the first circuit layer and the second circuit layer; the first dielectric layer is disposed on a surface of the second dielectric layer and extending to the connection area, and the resistor layer is embedded in the first dielectric layer.

[0028] In an embodiment of the present application, the circuit board also includes a via hole provided in the connection area, the via hole passes through the first connection pad and the base layer so that the resistance layer is electrically connected to the first circuit layer and the second circuit layer, and the first dielectric layer also covers the via hole.

[0029] In an embodiment of the present application, the thickness of the second dielectric layer is equal to the thickness of the first connection pad.

[0030] In the embodiment of the present application, the material of the resistance layer includes at least one of nickel-phosphorus alloy, carbon nanotubes, graphene and nanosilver.

[0031] Compared with the prior art, the circuit board manufacturing method provided by the present invention simplifies the manufacturing process by forming a resistor layer in a specific area. The manufacturing process of the first circuit layer and the second circuit layer is carried out independently from the manufacturing process of the resistor layer and does not interfere with each other. There is no need to set a resistor layer under the circuit layer, and no high-temperature copper sulfate etching process is required. The circuit sidewalls are smooth, the signal transmission performance is excellent, and the line width, line spacing and thickness can be precisely controlled. It is particularly suitable for manufacturing fine circuits and can manufacture fine circuits with a line width of less than 25μm. The resistor layer is only formed in the resistor area, which reduces the amount of resistor material used and reduces costs. Except for the first connection pad in the connection area, which partially contacts the resistor layer, there is no resistor layer in the circuit area. Therefore, there is no need to consider the bonding strength of the resistor material with the circuit layer and the base layer. Moreover, the resistor layer is embedded in the first dielectric layer and the second dielectric layer, and the bonding strength is good, which helps to ensure that the overall flexibility of the circuit board is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a copper clad laminate provided in an embodiment of the present invention.

[0033] Figure 2 For Figure 1 Schematic diagram of forming via holes on a copper clad board.

[0034] Figure 3 For Figure 2 Schematic diagram showing a first metal layer and a second metal layer covering a first dry film.

[0035] Figure 4 and Figure 5 For graphics Figure 3 The schematic diagram of the first dry film forming the patterned dry film is shown.

[0036] Figure 6 For Figure 5 The pattern shown is filled with a resistive material to form a resistive layer.

[0037] Figure 7 To remove Figure 6 Schematic diagram after patterning dry film.

[0038] Figure 8 For Figure 7 Schematic diagram of forming a first dielectric layer on the surface of the resistance layer.

[0039] Figure 9 To remove Figure 8 Schematic diagram of the corresponding base layer and second metal layer in the resistance area.

[0040] Figure 10 For Figure 9 Schematic diagram showing that the surfaces of the first metal layer and the second metal layer are covered with a second dry film.

[0041] Figure 11 and Figure 12 For graphics Figure 10 The schematic diagram shown is of the first metal layer and the second metal layer forming the first circuit layer and the second circuit layer respectively.

[0042] Figure 13 For Figure 12 Schematic diagram of disposing the second dielectric layer and the first covering layer in the first opening and the second opening.

[0043] Figure 14 A schematic structural diagram of a circuit board provided in one embodiment of the present invention.

[0044] Figure 15 A bottom view of a circuit board provided in accordance with one embodiment of the present invention.

[0045] Figure 16 This is a SEM photograph of a cross section of a circuit board provided in one embodiment of the present invention.

[0046] Figure 17 This is a SEM photograph of the surface of a circuit board provided in one embodiment of the present invention.

[0047] Description of main component symbols

[0048] Circuit board 100

[0049] Copper Clad Laminate 10

[0050] Grassroots 11

[0051] First surface 111

[0052] Second surface 112

[0053] First metal layer 12

[0054] Second metal layer 13

[0055] Via 14

[0056] First circuit layer 15

[0057] First connection pad 151

[0058] Second circuit layer 16

[0059] Second connection pad 161

[0060] First opening 17

[0061] Second opening 18

[0062] Resistive layer 20

[0063] First dry film 30

[0064] Graphic dry film 31

[0065] Second dry film 30a

[0066] First dielectric layer 40

[0067] Second dielectric layer 50

[0068] The third dielectric layer 60

[0069] First covering layer 70

[0070] Second covering layer 80

[0071] Surface treatment layer 90

[0072] Line Area A

[0073] Resistance Zone B

[0074] Connector region C

[0075] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0076] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0078] An embodiment of the present invention provides a method for manufacturing a circuit board 100, the method specifically comprising the following steps:

[0079] Step S1, see Figure 1 A copper-clad laminate 10 is provided. The copper-clad laminate 10 includes a base layer 11, a first metal layer 12, and a second metal layer 13. The base layer 11 includes a first surface 111 and a second surface 112 opposite to each other. The first metal layer 12 is disposed on the first surface 111, and the second metal layer 13 is disposed on the second surface 112. The base layer 11 includes a circuit region A, a resistor region B, and a connection region C disposed between the circuit region A and the resistor region B.

[0080] In this embodiment, the copper clad laminate 10 is a double-sided copper clad laminate. It is understandable that the copper clad laminate 10 may also be a single-sided copper clad laminate.

[0081] In this embodiment, the material of the base layer 11 can be selected from one of epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the base layer 11 is PI.

[0082] In this embodiment, the first metal layer 12 and the second metal layer 13 may be made of copper.

[0083] Step S2, see Figure 2 A via hole 14 is opened in the copper clad laminate 10 corresponding to the connection area C. The via hole 14 passes through the first metal layer 12 and the base layer 11 to electrically connect the first metal layer 12 to the second metal layer 13.

[0084] In this embodiment, the via holes 14 are formed by laser punching. It is understood that the via holes 14 can also be formed by mechanical punching.

[0085] Step S3, see Figures 3 to 7 A resistance layer 20 is formed on the surface of the first metal layer 12 corresponding to the resistance area B, and the resistance layer 20 extends to the connection area C.

[0086] In this embodiment, the manufacturing method of the resistance layer 20 specifically includes the following steps:

[0087] Step S31, see Figure 3 , a first dry film 30 is covered on the surface of the first metal layer 12 .

[0088] In this embodiment, in order to protect the second metal layer 13 from being affected during the manufacturing process of the resistor layer 20 , the surface of the second metal layer 13 is also covered with a first dry film 30 .

[0089] Step S32, see Figures 3 to 5 , the first dry film 30 corresponding to the resistance area B is exposed and developed to etch the first dry film 30 to form a patterned dry film 31 .

[0090] In this embodiment, the first dry film 30 on the surface of the second metal layer 13 is not patterned and is only used as a protective film.

[0091] Step S33, see Figure 6, a resistor material is filled in the patterned area of ​​the patterned dry film 31 and cured to form the resistor layer 20 .

[0092] In this embodiment, there are no specific requirements for the resistor material; any conventional embedded resistor material that meets practical needs can be used, which is cost-effective. Specifically, the resistor material can be selected from, but not limited to, at least one of nickel-phosphorus alloy, carbon nanotubes, graphene, and nanosilver. Furthermore, the thickness and area of ​​the resistor layer 20 can be varied based on the actual design requirements of the circuit board. Thus, resistors with different electrical properties can be designed to meet diverse needs.

[0093] Step S34, see Figure 7 , remove the patterned dry film 31.

[0094] In this embodiment, the resistor layer 20 is manufactured by the above method, and the line width and thickness of the resistor layer 20 can be precisely controlled. Moreover, the resistor layer 20 with a thin line can be manufactured according to the actual resistance value requirement, thereby improving the resistance value.

[0095] It is understandable that the resistance layer 20 may also be manufactured by a subtractive method.

[0096] Step S3, see Figure 8 A first dielectric layer 40 is formed on the surface of the first metal layer 12 corresponding to the resistance area B. The resistance layer 20 is embedded in the first dielectric layer 40 . The first dielectric layer 40 extends to the connection area C and covers the via 14 .

[0097] In this embodiment, the material of the first dielectric layer 40 can be selected from any thermosetting or photocurable material that has filling and protective functions, other than a resistor material, such as coverlay film (CVL), ink, pure glue, ABF resin, and prepreg (PP). Specifically, the material of the first dielectric layer 40 is ink.

[0098] Step S4, see Figure 9 , the base layer 11 corresponding to the resistance area B is removed to form a first opening 17 . The first opening 17 penetrates the second metal layer 13 , and the first metal layer 12 is exposed at the first opening 17 .

[0099] In this embodiment, the base layer 11 and the second metal layer 13 corresponding to the resistance area B are removed by laser ablation.

[0100] Step S5, see Figures 10 to 12The first metal layer 12 exposed by the first opening 17 is removed to form a second opening 18. The resistor layer 20 is exposed in the second opening 18. The first metal layer 12 and the second metal layer 13 are then patterned to form a first circuit layer 15 and a second circuit layer 16. The first circuit layer 15 includes a first connection pad 151 corresponding to the connection area C, and the second circuit layer 16 includes a second connection pad 161 corresponding to the connection area C. The vias 14 are provided corresponding to the first connection pad 151 and the second connection pad 161. The resistor layer 20 is electrically connected to the first circuit layer 15 and the second circuit layer 16 via the first connection pad 151, the via 14, and the second connection pad 161.

[0101] In the present application, the fabrication of the first circuit layer 15 and the second circuit layer 16 is performed separately from the fabrication of the resistor layer 20 without interfering with each other. Furthermore, there is no circuit layer within the resistor region B. Therefore, the line width, line spacing, and thickness of the first circuit layer 15, the second circuit layer 16, and the resistor layer 20 can be precisely controlled.

[0102] In this embodiment, the first circuit layer 15 and the second circuit layer 16 are manufactured by covering with a second dry film 30a, exposing, developing, and etching.

[0103] In this embodiment, the first metal layer 12 corresponding to the resistor region B is removed simultaneously with the fabrication of the first and second circuit layers 15, 16 to form the second opening 18. Because the laser ablation thickness is limited when removing portions of the base layer 11 and the second metal layer 13, the first metal layer 12 in the resistor region B must be further removed during the circuit fabrication step. This removal of the first metal layer 12 is performed simultaneously with the fabrication of the first and second circuit layers 15, 16, eliminating the need for separate fabrication steps and simplifying the manufacturing process.

[0104] Step S6, see Figure 13 A second dielectric layer 50 is disposed in the second opening 18, and the second dielectric layer 50 covers the resistor layer 20. A third dielectric layer 60 is disposed on two opposite surfaces of the base layer 11, and the first circuit layer 15 and the second circuit layer 16 are both embedded in the third dielectric layer 60 on the same side.

[0105] The second dielectric layer 50 can completely cover the resistor layer 20 and has a strong bonding force with the first dielectric layer 40 , so that the resistor layer 20 is embedded in the first dielectric layer 40 and the second dielectric layer 50 , thereby protecting the resistor layer 20 .

[0106] In this embodiment, the material of the second dielectric layer 50 can be selected from any thermosetting or photocurable material that has filling and protective functions, other than a resistor material, such as cover film (CVL), ink, pure glue, ABF resin, and prepreg (PP). Specifically, the material of the second dielectric layer 50 is a cover film.

[0107] In this embodiment, the thickness of the second dielectric layer 50 is approximately equal to the thickness of the removed first metal layer 12, that is, the thickness of the second dielectric layer 50 is approximately equal to the thickness of the first connection pad 151. The bottom of the resistor layer 20 contacts the first connection pad 151 and the second dielectric layer 50, and the contact area forms a T-shaped structure. The contact area between the resistor layer 20 and the first connection pad 151 is limited, and the other surfaces are covered by the first dielectric layer 40. The resistor layer 20 is embedded in the first dielectric layer 40 and the second dielectric layer 50, and the resistor layer 20 has good bonding strength with the first dielectric layer 40 and the second dielectric layer 50. The resistor layer 20 has no contact with the base layer 11, and there is no circuit layer in the resistor area B. Therefore, the problem of poor bonding strength between the resistor layer 20 and the base layer 11 or the circuit layer does not arise. Therefore, the design of the resistor layer 20 in this application will not affect the flexibility of the entire circuit board.

[0108] In this embodiment, the material of the third dielectric layer 60 can be selected from any thermosetting material or light-curing material with filling and protection functions that is different from the resistor material, such as cover film (CVL), ink, pure glue, ABF resin and prepreg (PP).

[0109] Step S7, please refer again Figure 13 A first covering layer 70 is disposed in the first opening 17 . The first covering layer 70 is located on the surface of the second dielectric layer 50 , and a second covering layer 80 is disposed on the surface of each of the third dielectric layers 60 .

[0110] The first covering layer 70 supports the resistance area B and can improve the strength of the entire circuit board.

[0111] In this embodiment, the first covering layer 70 can be made of the same material as the base layer 11. The material of the first covering layer 70 can be selected from one of the resins such as epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the first covering layer 70 is PI.

[0112] In this embodiment, the material of the second covering layer 80 can be selected from one of epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the second covering layer 80 is PI.

[0113] Step S8, see Figure 14 and Figure 15 , a surface treatment layer 90 is formed on the surface of the second connection pad 161 to obtain the circuit board 100.

[0114] In this embodiment, the surface treatment layer 90 can be formed by electroplating, chemical plating or mechanical plating.

[0115] In this embodiment, the material of the surface treatment layer 90 can be one or more of gold, nickel, silver and tin. Specifically, the material of the surface treatment layer 90 is gold.

[0116] The manufacturing method provided by the present invention forms the resistor layer 20 in a specific area. There is no special requirement for the roughness of the copper layer of the first metal layer 12 and the second metal layer 13. The circuit is produced using the traditional circuit production process of lamination, exposure, development and etching. The circuit layer can be formed without high-temperature copper sulfate etching, which simplifies the process. The production process of the first circuit layer 15 and the second circuit layer 16 is independent of the production process of the resistor layer 20 and does not interfere with each other. There is no need to set a resistor layer under the circuit layer, and no high-temperature copper sulfate etching process is required. As shown in Figure 16 and Figure 17As shown, the cross-sectional SEM (scanning electron microscope) photograph of the first circuit layer 15 of circuit board 100 and the surface SEM photograph of the first circuit layer 15 of circuit board 100 demonstrate smooth circuit sidewalls and uniform circuit thickness and width, resulting in excellent signal transmission performance. The circuit layer and resistor layer fabrication processes do not interfere with each other, eliminating the need for circuit compensation. This allows for precise control of line width, line spacing, thickness, and specific patterns, making it particularly suitable for producing fine circuits, with widths of less than 25μm. Furthermore, the resistor layer 20 is fabricated only in resistor area B, reducing the amount of resistor material used and lowering costs. The drilling direction of the via 14 has no specific requirements and is identical to conventional via processes, as long as it provides electrical connection between the first connection pad 151 and the second connection pad 161. Except for the partial contact between the first connection pad 151 and the resistor layer 20 in connection area C, the circuit area A lacks the resistor layer 20. Therefore, there is no need to consider the bonding strength of the resistor material with the circuit layer and base layer 11, effectively ensuring the overall flexibility of the circuit board 100.

[0117] See also Figure 12 and Figure 13 The present invention also provides a circuit board 100, comprising: a base layer 11, a first circuit layer 15, a second circuit layer 16, a resistor layer 20, a first dielectric layer 40, a second dielectric layer 50, and a first cover layer 70. The base layer 11 comprises a circuit region A, a resistor region B, and a connection region C disposed between the circuit region A and the resistor region B. The base layer 11 comprises a first surface 111 and a second surface 112 opposing each other. The first circuit layer 15 is disposed on the first surface 111 and comprises a first connection pad 151, which is disposed corresponding to the connection region C. The second circuit layer 16 is disposed on the second surface 112 and comprises a second connection pad 161, which is disposed corresponding to the connection region C. The first connection pad 151 is electrically connected to the second connection pad 161. The base layer 11 has a first opening 17 corresponding to the resistor region B. A first covering layer 70 is disposed within the first opening 17. The first circuit layer 15 has a second opening 18 corresponding to the resistor region B. The second opening 18 is connected to the first opening 17. The second dielectric layer 50 is disposed within the second opening 18 and is disposed on the surface of the first covering layer 70. The resistor layer 20 is disposed on the surface of the second dielectric layer 50. The resistor layer 20 extends to the connection region C and is located on the surface of the first connection pad 151, electrically connecting the resistor layer 20 to the first circuit layer 15 and the second circuit layer 16. A first dielectric layer 40 is disposed on the surface of the second dielectric layer 50. The first dielectric layer 40 extends to the connection region C and is embedded in the first dielectric layer 40.

[0118] In this embodiment, the material of the base layer 11 can be selected from one of epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the base layer 11 is PI.

[0119] In this embodiment, the resistor material may be selected from but not limited to at least one of nickel-phosphorus alloy, carbon nanotubes, graphene, and nanosilver.

[0120] In this embodiment, the thickness of the second dielectric layer 50 is equal to the thickness of the first connection pad 151 .

[0121] In this embodiment, the material of the second dielectric layer 50 can be selected from any thermosetting or photocurable material that has filling and protective functions, other than a resistor material, such as cover film (CVL), ink, pure glue, ABF resin, and prepreg (PP). Specifically, the material of the second dielectric layer 50 is a cover film.

[0122] In this embodiment, the first covering layer 70 can be made of the same material as the base layer 11. The material of the first covering layer 70 can be selected from one of the resins such as epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the first covering layer 70 is PI.

[0123] In this embodiment, the circuit board 100 further includes a via 14 corresponding to the connection area C. The via 14 penetrates the first connection pad 151 and the base layer 11 to electrically connect the first connection pad 151 to the second connection pad 161. The first dielectric layer 40 also covers the via 14.

[0124] In this embodiment, the first surface 111 and the second surface 112 corresponding to the circuit area A are both provided with a third dielectric layer 60, the first circuit layer 15 and the second circuit layer 16 are both embedded in the third dielectric layer 60, and each surface of the third dielectric layer 60 facing away from the base layer 11 is provided with a second covering layer 80.

[0125] In this embodiment, the material of the third dielectric layer 60 can be selected from any thermosetting material or light-curing material with filling and protection functions that is different from the resistor material, such as cover film (CVL), ink, pure glue, ABF resin and prepreg (PP).

[0126] In this embodiment, the material of the second covering layer 80 can be selected from one of epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Specifically, the material of the second covering layer 80 is PI.

[0127] In another embodiment, the circuit board 100 can also be a single-sided board, comprising only the first circuit layer 15. In this case, there is no need to provide the vias 14 to achieve electrical connection between the two layers of circuits, simplifying the manufacturing process. It is understood that the circuit board 100 can also be a multi-layer board. During the manufacturing process, layers can be added to the surfaces of the first circuit layer 15 and the second circuit layer 16 by adding layers. The manufacturing process of the circuit layers is not affected by the manufacturing of the resistor layer 20 and can be achieved using conventional circuit layer adding methods.

[0128] The manufacturing method of the circuit board 100 provided by the present invention simplifies the manufacturing process by forming the resistor layer 20 in specific areas. The manufacturing process of the first circuit layer 15 and the second circuit layer 16 is carried out independently of the manufacturing process of the resistor layer 20, and does not interfere with each other. No resistor layer is required under the circuit layer, and a high-temperature copper sulfate etching process is not required. The circuit sidewalls are smooth, the signal transmission performance is excellent, and the line width, line spacing, and thickness can be precisely controlled. It is particularly suitable for manufacturing fine circuits, and can produce fine circuits with a line width of less than 25μm. The resistor layer 20 is only formed in the resistor area B, which reduces the amount of resistor material used and lowers costs. Except for the first connection pad 151 in the connection area C, which partially contacts the resistor layer 20, the circuit area A does not have the resistor layer 20. Therefore, there is no need to consider the bonding strength of the resistor material with the circuit layer and the base layer 11. Moreover, the resistor layer 20 is embedded in the first dielectric layer 40 and the second dielectric layer 50, and the bonding strength is good, which helps to ensure that the flexibility of the entire circuit board is not affected.

Claims

1. A method for manufacturing a circuit board, characterized in that: Including steps: A copper-clad laminate is provided, comprising a base layer and a first metal layer and a second metal layer provided on two opposite surfaces of the base layer, wherein the base layer comprises a circuit area, a resistor area, and a connection area provided between the circuit area and the resistor area; forming a resistance layer on a surface of the first metal layer corresponding to the resistance area, wherein the resistance layer extends to the connection area; forming a first dielectric layer on a surface of the first metal layer corresponding to the resistance area, wherein the first dielectric layer extends to the connection area, and the resistance layer is embedded in the first dielectric layer; removing the base layer corresponding to the resistance region to form a first opening, wherein the first opening penetrates the second metal layer, and the first metal layer is exposed at the first opening; Removing the first metal layer exposed by the first opening to form a second opening, exposing the resistor layer in the second opening, and patterning the first metal layer and the second metal layer to form a first circuit layer and a second circuit layer, respectively, wherein the first circuit layer includes a first connection pad located in the connection area, and the second circuit layer includes a second connection pad located in the connection area, and the first connection pad is electrically connected to the second connection pad, so that the resistor layer is electrically connected to the first circuit layer and the second circuit layer; Disposing a second dielectric layer in the second opening, wherein the second dielectric layer covers the resistance layer; as well as A first covering layer is disposed in the first opening and on the surface of the second dielectric layer, thereby obtaining the circuit board.

2. The method for manufacturing a circuit board according to claim 1, wherein: Before forming the resistance layer, the manufacturing method further includes: Opening a via hole in the copper-clad laminate corresponding to the connection area, wherein the via hole passes through the first metal layer and the base layer, so as to electrically connect the first metal layer and the second metal layer; After forming the first dielectric layer, the manufacturing method further includes: The first dielectric layer is extended to cover the via hole.

3. The method for manufacturing a circuit board according to claim 1, wherein: After forming the first covering layer, the manufacturing method further includes: A surface treatment layer is formed on the surface of the second connection pad.

4. The method for manufacturing a circuit board according to claim 1, wherein: The manufacturing method of the resistance layer includes: covering the first metal layer with a first dry film; exposing, developing and etching the first dry film to form a patterned dry film; Filling a resistive material in the patterned area of ​​the patterned dry film and curing the material to form a resistive layer; and The patterned dry film is removed.

5. The method for manufacturing a circuit board according to claim 1, wherein: The thickness of the second dielectric layer is equal to the thickness of the first connection pad.

6. The method for manufacturing a circuit board according to claim 1, wherein: The material of the resistance layer includes at least one of nickel-phosphorus alloy, carbon nanotubes, graphene and nanosilver.

7. A circuit board, characterized in that: include: A base layer, comprising a circuit area, a resistor area, and a connection area provided between the circuit area and the resistor area, wherein the base layer is provided with a first opening corresponding to the resistor area, and a first covering layer is provided in the first opening; a first circuit layer disposed on the first surface of the base layer, the first circuit layer including a first connection pad disposed corresponding to the connection area, and the first circuit layer having a second opening communicating with the first opening corresponding to the resistance area; a second circuit layer, the second circuit layer being disposed on a second surface of the base layer away from the first surface, the second circuit layer comprising a second connection pad, the second connection pad being disposed corresponding to the connection area, the first connection pad being electrically connected to the second connection pad; a second dielectric layer, disposed in the second opening and located on a surface of the first covering layer; a resistor layer disposed on a surface of the second dielectric layer, wherein the resistor region extends to a surface of the first connection pad, so that the resistor layer is electrically connected to the first circuit layer and the second circuit layer; as well as The first dielectric layer is disposed on the surface of the second dielectric layer and extends to the connection area. The resistance layer is embedded in the first dielectric layer.

8. The circuit board according to claim 7, wherein: It also includes a via hole provided in the connection area, the via hole passes through the first connection pad and the base layer to electrically connect the resistance layer with the first circuit layer and the second circuit layer, and the first dielectric layer also covers the via hole.

9. The circuit board according to claim 7, wherein: The thickness of the second dielectric layer is equal to the thickness of the first connection pad.

10. The circuit board according to claim 7, wherein: The material of the resistance layer includes at least one of nickel-phosphorus alloy, carbon nanotubes, graphene and nanosilver.

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