Methods for forming capacitor holes and semiconductor structures

Abstract

This invention proposes a method for forming a capacitor aperture and a semiconductor structure. The method includes: providing a substrate in which electrodes are formed; forming a pattern definition layer on the surface of the substrate; sequentially forming three sets of trenches in the pattern definition layer, the three sets of trenches intersecting each other at 120° intervals, and forming hexagonal holes in the pattern definition layer at the intersections; using the pattern definition layer as a mask, etching the substrate along the holes to form a capacitor aperture in the substrate. Under the effect of etching load, the bottom of the capacitor aperture is circular, and the electrodes are exposed at the bottom of the capacitor aperture. Through the above design, this invention can ensure that the bottom of the capacitor aperture is circular, thus maintaining the uniform curvature of the capacitor aperture.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor memory device fabrication methods, and more particularly to a method for forming capacitor holes and a semiconductor structure. Background Technology

[0002] In the current semiconductor structure capacitor manufacturing scheme, due to the exposure limit, the current immersion lithography process usually uses two photomasks to form linear patterns in two directions. The two linear patterns in two directions form a blank parallelogram pattern. After dry etching, the pattern is transferred downward and finally forms a capacitor array that is roughly arranged in a hexagonal pattern.

[0003] However, taking a single capacitor as an example, the capacitor aperture changes from its original parallelogram shape to an ellipse and then moves downwards. Due to the etching load effect, the top of the aperture is continuously subjected to plasma, resulting in a more regular circular shape. Near the bottom of the aperture, the bombardment effect of etching gas dominates, causing the bottom of the aperture to maintain its original elliptical shape. The ellipticity of the aperture increases from top to bottom. On the one hand, the adhesion between the high-dielectric material and the bottom electrode is limited, and there is a difference in the coefficient of thermal expansion. At the two ends of the aperture with greater elliptical curvature, the stress is greater, which can easily lead to voids during the thermal process. On the other hand, the uneven curvature distribution of the aperture leads to an uneven electric field distribution within the aperture. The electric field density is higher in areas with greater curvature, resulting in poor leakage current. Summary of the Invention

[0004] A primary objective of this invention is to overcome at least one of the deficiencies of the prior art and to provide a method for forming a capacitor hole that ensures the bottom of the capacitor hole is circular and that the curvature of the capacitor hole remains uniform.

[0005] Another major objective of the present invention is to overcome at least one of the defects of the prior art described above and to provide a semiconductor structure in which a capacitor hole is formed by the above-described forming method.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] According to one aspect of the present invention, a method for forming a capacitor hole is provided, wherein the method comprises: providing a substrate in which electrodes are formed; forming a pattern definition layer on the surface of the substrate; sequentially forming three sets of trenches in the pattern definition layer, the three sets of trenches intersecting each other at 120°, and forming hexagonal holes in the pattern definition layer at the intersection positions; using the pattern definition layer as a mask and etching the substrate along the holes to form a capacitor hole in the substrate, wherein under the action of etching load effect, the bottom of the capacitor hole is circular, and the electrodes are exposed at the bottom of the capacitor hole.

[0008] According to one embodiment of the present invention, the step of forming a pattern definition layer on the substrate surface includes: forming a first passivation layer on the substrate surface; forming a first anti-reflection layer on the surface of the first passivation layer, wherein the first anti-reflection layer and the first passivation layer together form the pattern definition layer, and the three sets of trenches are formed on the first anti-reflection layer.

[0009] According to one embodiment of the present invention, after the first antireflective layer forms the three sets of trenches, the hole is formed in the first passivation layer at the intersection of the three sets of trenches.

[0010] According to one embodiment of the present invention, the step of forming a first set of trenches in the pattern definition layer includes: forming a first mask layer on the surface of the pattern definition layer; forming a first trench structure on the surface of the first mask layer by a pitch doubling process; etching the pattern definition layer with the first mask layer as a mask to transfer the first trench structure to the pattern definition layer to form a first set of trenches.

[0011] According to one embodiment of the present invention, the step of forming a first trench structure on the surface of a first mask layer by a pitch doubling process includes: forming a first photoresist layer on the surface of the first mask layer; patterning the first photoresist layer to form a first opening; forming a first sacrificial layer on the surfaces of the first mask layer and the first photoresist layer, the first sacrificial layer covering the sidewalls and bottomwalls of the first opening; etching away the first sacrificial layer located on the surface of the first mask layer and the top of the first photoresist layer, the remaining first sacrificial layer being the first trench structure.

[0012] According to one embodiment of the present invention, the step of forming a first mask layer on the surface of the pattern definition layer includes: forming a second passivation layer on the surface of the pattern definition layer; forming a second anti-reflection layer on the surface of the second passivation layer, wherein the second anti-reflection layer and the second passivation layer together form the first mask layer.

[0013] According to one embodiment of the present invention, the step of forming a second set of trenches in the pattern definition layer includes: forming a second mask layer on the surface of the pattern definition layer, the second mask layer filling the first set of trenches; forming a second trench structure on the surface of the second mask layer by a pitch doubling process; etching the pattern definition layer with the second mask layer as a mask to transfer the second trench structure to the pattern definition layer to form a second set of trenches.

[0014] According to one embodiment of the present invention, the step of forming a second trench structure on the surface of the second mask layer by a pitch doubling process includes: forming a second photoresist layer on the surface of the second mask layer; patterning the second photoresist layer to form a second opening; forming a second sacrificial layer on the surfaces of the second mask layer and the second photoresist layer, the second sacrificial layer covering the sidewalls and bottomwalls of the second opening; etching away the second sacrificial layer located on the surface of the second mask layer and the top of the second photoresist layer, the remaining second sacrificial layer being the second trench structure.

[0015] According to one embodiment of the present invention, the step of forming a second mask layer on the surface of the pattern definition layer includes: forming a third passivation layer on the surface of the pattern definition layer, the third passivation layer filling a first set of trenches; forming a third anti-reflection layer on the surface of the third passivation layer, the third anti-reflection layer and the third passivation layer together forming the second mask layer.

[0016] According to one embodiment of the present invention, the third passivation layer is formed on the pattern definition layer by a spin coating process.

[0017] According to one embodiment of the present invention, the step of forming a third set of trenches in the pattern definition layer includes: forming a third mask layer on the surface of the pattern definition layer, the third mask layer filling the first set of trenches and the second set of trenches; forming a third trench structure on the surface of the third mask layer by a pitch doubling process; etching the pattern definition layer with the third mask layer as a mask to transfer the third trench structure to the pattern definition layer to form a third set of trenches.

[0018] According to one embodiment of the present invention, the step of forming a third trench structure on the surface of a third mask layer by a pitch doubling process includes: forming a third photoresist layer on the surface of the third mask layer; patterning the third photoresist layer to form a third opening; forming a third sacrificial layer on the surfaces of the third mask layer and the third photoresist layer, the third sacrificial layer covering the sidewalls and bottom wall of the third opening; etching away the third sacrificial layer located on the surface of the third mask layer and the top of the third photoresist layer, the remaining third sacrificial layer being the third trench structure.

[0019] According to one embodiment of the present invention, the step of forming a third mask layer on the surface of the pattern definition layer includes: forming a fourth passivation layer on the surface of the pattern definition layer, the fourth passivation layer filling a first set of trenches and a second set of trenches; forming a fourth anti-reflection layer on the surface of the fourth passivation layer, the fourth anti-reflection layer and the fourth passivation layer together forming the third mask layer.

[0020] According to another aspect of the present invention, a semiconductor structure is provided having a capacitor hole, wherein the capacitor hole is formed by a capacitor hole forming method proposed in the present invention and described in the above embodiments.

[0021] As can be seen from the above technical solutions, the advantages and positive effects of the capacitor hole formation method and semiconductor structure proposed in this invention are as follows:

[0022] The capacitor aperture formation method proposed in this invention uses a three-exposure process to form a hexagonal hole. During the downward transfer of this hole to form the capacitor aperture, under the action of the etching load effect, the capacitor aperture changes from the straight hexagonal outline at the top to an arc, forming a more regular circle, thereby significantly improving the shape of the bottom of the capacitor aperture. Through the above design, this invention can ensure that the bottom of the capacitor aperture is circular, keeping the curvature of the capacitor aperture uniform. Attached Figure Description

[0023] Various objects, features, and advantages of the invention will become more apparent from the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings. The drawings are merely illustrative of the invention and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0024] Figures 1 to 3 , Figures 5 to 8 , Figures 10 to 13 , Figure 15 and Figure 17 These are schematic diagrams of the semiconductor structure under several steps of the capacitor hole formation method proposed in this invention.

[0025] Figure 4 , Figure 9 , Figure 14 , Figure 16 and Figure 18 These are planar diagrams of the semiconductor structure under several steps of the capacitor hole formation method proposed in this invention.

[0026] The annotations in the attached figures are explained as follows:

[0027] 100. Substrate; 420. Second photoresist layer;

[0028] 101. Electrode; 421. Second opening;

[0029] 200. Pattern definition layer; 430. Second sacrificial layer;

[0030] 210. First passivation layer; 431. Second trench structure;

[0031] 220. First anti-reflective layer; 510. Third mask layer;

[0032] 310. First mask layer; 511. Fourth passivation layer;

[0033] 311. Second passivation layer; 512. Fourth anti-reflection layer;

[0034] 312. Second anti-reflective layer; 520. Third photoresist layer;

[0035] 320. First photoresist layer; 521. Third opening;

[0036] 321. First opening; 530. Third sacrificial layer;

[0037] 330. First sacrificial layer; 531. Third trench structure;

[0038] 331. First trench structure; G1. Trench;

[0039] 410. Second mask layer; G2. Trench;

[0040] 411. Third passivation layer; G3. Trench;

[0041] 412. Third anti-reflective layer; H. Capacitive aperture;

[0042] h. Hole. Detailed Implementation

[0043] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the description and drawings therein are for illustrative purposes only and not intended to limit the present invention.

[0044] In the following description of different exemplary embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and in which different exemplary structures, systems, and steps that can implement various aspects of the invention are shown by way of example. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the invention. Furthermore, although the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the invention, these terms are used herein only for convenience, such as the orientation according to the examples shown in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the invention.

[0045] See Figures 1 to 3 , Figures 5 to 8 , Figures 10 to 13 , Figure 15 and Figure 17The diagrams illustrate, respectively, the structural schematics of the semiconductor structure under several steps of the capacitor hole formation method proposed in this invention. In this exemplary embodiment, the capacitor hole formation method proposed in this invention is described using the manufacturing process of a capacitor tube with a semiconductor structure formed by immersion photolithography as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of this invention to other types of capacitor structures or other processes; these changes are still within the scope of the principles of the capacitor hole formation method proposed in this invention.

[0046] like Figures 1 to 3 , Figures 5 to 8 , Figures 10 to 13 , Figure 15 and Figure 17 As shown, in this embodiment, the method for forming a capacitor hole proposed in this invention includes:

[0047] A substrate 100 is provided, wherein electrodes 101 are formed in the substrate 100;

[0048] A pattern definition layer 200 is formed on the surface of the substrate 100;

[0049] Three sets of grooves G1, G2, and G3 are formed sequentially in the pattern definition layer 200. The three sets of grooves G1, G2, and G3 intersect each other at 120°, and hexagonal holes h are formed in the pattern definition layer 200 at the intersection positions.

[0050] Using the pattern definition layer 200 as a mask, the substrate 100 is etched along the hole h to form a capacitor hole H in the substrate 100. Under the effect of etching load, the bottom of the capacitor hole H is circular, and the electrode 101 is exposed at the bottom of the capacitor hole H.

[0051] As described above, the method for forming a capacitor aperture proposed in this invention uses a three-exposure process to form a hexagonal hole h. During the downward transfer of this hole h to form the capacitor aperture H, under the action of the etching load effect, the capacitor aperture H changes from a straight hexagonal outline at the top to an arc, forming a more regular circle, thereby significantly improving the shape of the bottom of the capacitor aperture H. Through the above design, this invention can ensure that the bottom of the capacitor aperture H is circular, keeping the curvature of the capacitor aperture H uniform.

[0052] Optionally, such as Figures 1 to 3 , Figures 5 to 8 , Figures 10 to 13 , Figure 15 and Figure 17 As shown, in this embodiment, the step of "forming a pattern definition layer 200 on the surface of substrate 100" may specifically include:

[0053] A first passivation layer 210 is formed on the surface of the substrate 100;

[0054] A first anti-reflective layer 220 is formed on the surface of the first passivation layer 210. The first anti-reflective layer 220 and the first passivation layer 210 together form a pattern definition layer 200. Three sets of trenches G1, G2 and G3 are formed on the first anti-reflective layer 220.

[0055] Furthermore, such as Figure 3 , Figure 8 , Figure 13 and Figure 15 As shown, based on the above-mentioned process design for forming the pattern definition layer 200, in this embodiment, the step of "forming hole h" is to form a hole h in the first passivation layer 210 after forming three sets of trenches G1, G2, and G3 in the first anti-reflection layer 220. The hole h is the pattern of the pattern definition layer 200.

[0056] Optionally, such as Figures 1 to 3 As shown, the step of "forming the first set of trenches G1 in the pattern definition layer 200" may specifically include:

[0057] A first mask layer 310 is formed on the surface of the pattern definition layer 200;

[0058] The first trench structure 331 is formed on the surface of the first mask layer 310 by a spacing doubling process;

[0059] Using the first mask layer 310 as a mask, the pattern definition layer 200 is etched, and the first trench structure 331 is transferred to the pattern definition layer 200 to form the first set of trenches G1.

[0060] Furthermore, such as Figures 1 to 3 As shown, based on the above-described process design for forming the first set of trenches G1, in this embodiment, the step of "forming the first mask layer 310 on the surface of the pattern definition layer 200" may specifically include:

[0061] A second passivation layer 311 is formed on the surface of the pattern definition layer 200;

[0062] A second anti-reflection layer 312 is formed on the surface of the second passivation layer 311, and the second anti-reflection layer 312 and the second passivation layer 311 together form the first mask layer 310.

[0063] Furthermore, such as Figures 1 to 3 As shown, based on the above-described process design for forming the first set of trenches G1, in this embodiment, the step of "forming the first trench structure 331 on the surface of the first mask layer 310 by means of a spacing doubling process" may specifically include:

[0064] A first photoresist layer 320 is formed on the surface of the first mask layer 310;

[0065] The first photoresist layer 320 is patterned to form the first opening 321;

[0066] A first sacrificial layer 330 is formed on the surface of the first mask layer 310 and the first photoresist layer 320, and the first sacrificial layer 330 covers the sidewall and bottom wall of the first opening 321;

[0067] The first sacrificial layer 330 located on the surface of the first mask layer 310 and the top of the first photoresist layer 320 is removed by etching, and the remaining first sacrificial layer 330 is the first trench structure 331.

[0068] Specifically, such as Figure 1 The diagram illustrates a typical semiconductor structure in the step of "forming a first sacrificial layer 330 on the surfaces of the first mask layer 310 and the first photoresist layer 320". Specifically, in this step, the semiconductor structure includes a substrate 100, a patterning layer 200, a first mask layer 310, a patterned first photoresist layer 320, and a first sacrificial layer 330. An electrode 101 is formed in the substrate 100. The patterning layer 200 is formed on the surface of the substrate 100 and includes a first passivation layer 210 and a first anti-reflection layer 220. The first mask layer 310 is formed on the surface of the patterning layer 200 and includes a second passivation layer 311 and a second anti-reflection layer 312. The first photoresist layer 320 is formed on the surface of the first mask layer 310, and the first photoresist layer 320 is patterned to form a first opening 321. The first sacrificial layer 330 is formed on the surface of the first mask layer 310 and the surface of the remaining first photoresist layer 320. That is, the first sacrificial layer 330 covers the surface of the first mask layer 310 exposed to the first opening 321, and also covers the sidewalls and bottom wall of the first opening 321.

[0069] It should be noted that, as Figure 1 As shown, the substrate 100 in this embodiment specifically includes a silicon substrate and a stacked structure. Based on this, an electrode 101 is formed in the silicon substrate and exposed on its surface. The stacked structure is formed on the surface of the silicon substrate and covers the electrode 101. Furthermore, in the step of forming the capacitor hole H described later, the capacitor hole H is specifically formed by removing a portion of the stacked structure. For ease of understanding and explanation, the aforementioned silicon substrate and stacked structure are collectively referred to as "substrate 100" in this specification.

[0070] Furthermore, in this embodiment, the material of electrode 101 may include, but is not limited to, tungsten (W).

[0071] Furthermore, in this embodiment, the first passivation layer 210 may, but is not limited to, include a DLC coating (diamond-like carbon).

[0072] Furthermore, in this embodiment, the material of the first antireflective layer 220 may include, but is not limited to, silicon oxynitride (SiON).

[0073] Furthermore, in this embodiment, the second passivation layer 311 may, but is not limited to, include a DLC coating.

[0074] Furthermore, in this embodiment, the material of the first sacrificial layer 330 may include, but is not limited to, silicon dioxide (SiO2).

[0075] Furthermore, in this embodiment, the material of the second antireflective layer 312 may include, but is not limited to, silicon oxynitride.

[0076] like Figure 2 The diagram illustrates a typical semiconductor structure in the step of "forming a first trench structure 331 on the surface of the first mask layer 310". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200, a first mask layer 310, and a remaining first sacrificial layer 330. The portion of the first sacrificial layer 330 located on the surface of the first mask layer 310 and the top surface of the first photoresist layer 320 is etched away via a pitch doubling process, leaving the remaining first sacrificial layer 330 to form the first trench structure 331. Furthermore, during the etching process, the remaining first photoresist layer 320 is completely removed.

[0077] like Figure 3 As shown, this represents a schematic diagram of the semiconductor structure in the step of "transferring the first trench structure 331 to the pattern definition layer 200 to form the first set of trenches G1". Figure 4 The diagram illustrates a plan view of a semiconductor structure during the step of "transferring the first trench structure 331 to the patterning layer 200 to form the first set of trenches G1". Specifically, in this step, the semiconductor structure includes a substrate 100 and a patterning layer 200 on which the first set of trenches G1 is formed. In this step, the first trench structure 331 is transferred to the first anti-reflective layer 220 of the patterning layer 200 using a dry etching process, thereby forming the first set of trenches G1 on the surface of the first anti-reflective layer 220. Furthermore, during the etching process, the first trench structure 331 (i.e., the remaining first sacrificial layer 330) and the first mask layer 310 are completely removed.

[0078] Optionally, such as Figures 5 to 8 As shown, the step of "forming the second set of trenches G2 in the pattern definition layer 200" may specifically include:

[0079] A second mask layer 410 is formed on the surface of the pattern definition layer 200, and the second mask layer 410 fills the first set of trenches G1;

[0080] A second trench structure 431 is formed on the surface of the second mask layer 410 by a spacing doubling process;

[0081] Using the second mask layer 410 as a mask, the pattern definition layer 200 is etched, and the second trench structure 431 is transferred to the pattern definition layer 200 to form the second set of trenches G2.

[0082] Furthermore, such as Figures 5 to 8 As shown, based on the above-described process design for forming the second set of trenches G2, in this embodiment, the step of "forming the second mask layer 410 on the surface of the pattern definition layer 200" may specifically include:

[0083] A third passivation layer 411 is formed on the surface of the pattern definition layer 200;

[0084] A third anti-reflection layer 412 is formed on the surface of the third passivation layer 411, and the third anti-reflection layer 412 and the third passivation layer 411 together form the second mask layer 410.

[0085] Furthermore, such as Figures 5 to 8 As shown, based on the above-described process design for forming the second set of trenches G2, in this embodiment, the step of "forming the second trench structure 431 on the surface of the second mask layer 410 by means of a spacing doubling process" may specifically include:

[0086] A second photoresist layer 420 is formed on the surface of the second mask layer 410;

[0087] The second photoresist layer 420 is patterned to form the second opening 421;

[0088] A second sacrificial layer 430 is formed on the surface of the second mask layer 410 and the second photoresist layer 420, and the second sacrificial layer 430 covers the sidewall and bottom wall of the second opening 421;

[0089] The second sacrificial layer 430 located on the surface of the second mask layer 410 and on top of the second photoresist layer 420 is etched away, and the remaining second sacrificial layer 430 forms the second trench structure 431.

[0090] Specifically, such as Figure 5The diagram illustrates a typical semiconductor structure in the step of "forming a second photoresist layer 420 in the second mask layer 410". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1, a second mask layer 410, and a patterned second photoresist layer 420. The second mask layer 410 is formed on the surface of the pattern definition layer 200 and fills the first set of trenches G1 on the surface of the first anti-reflective layer 220. The second mask layer 410 includes a third passivation layer 411 and a third anti-reflective layer 412. The second photoresist layer 420 is formed on the surface of the second mask layer 410, and the second photoresist layer 420 forms a second opening 421 through patterning.

[0091] Furthermore, in this embodiment, the third passivation layer 411 can be formed on the pattern definition layer 200 by a spin coating process.

[0092] Furthermore, in this embodiment, the material of the third antireflective layer 412 may include, but is not limited to, silicon oxynitride.

[0093] like Figure 6 The diagram illustrates a typical semiconductor structure in the step of "forming a second sacrificial layer 430 on the surfaces of the second mask layer 410 and the second photoresist layer 420". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1, a second mask layer 410, a patterned second photoresist layer 420, and a second sacrificial layer 430. The second sacrificial layer 430 is formed on the surface of the second mask layer 410 and the remaining surface of the second photoresist layer 420; that is, the second sacrificial layer 430 covers the surface of the second mask layer 410 exposed to the second opening 421, and also covers the sidewalls and bottom wall of the second opening 421.

[0094] Furthermore, in this embodiment, the material of the second sacrificial layer 430 may include, but is not limited to, silicon dioxide.

[0095] like Figure 7 The diagram illustrates a typical semiconductor structure in the step of "forming a second trench structure 431 on the surface of the second mask layer 410". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1 formed, a second mask layer 410, and the remaining second sacrificial layer 430. Through a pitch doubling process, the portion of the second sacrificial layer 430 located on the surface of the second mask layer 410 and the top surface of the second photoresist layer 420 is etched away, and the remaining second sacrificial layer 430 forms the second trench structure 431. Furthermore, during the etching process, the remaining second photoresist layer 420 is completely removed.

[0096] like Figure 8 As shown, this represents a schematic diagram of the semiconductor structure in the step of "transferring the second trench structure 431 to the pattern definition layer 200 to form the second set of trenches G2". Figure 9 The diagram illustrates a plan view of a semiconductor structure during the step of "transferring the second trench structure 431 to the patterning layer 200 to form a second set of trenches G2". Specifically, in this step, the semiconductor structure includes a substrate 100 and a patterning layer 200 on which the first set of trenches G1 and the second set of trenches G2 are formed. In this step, the second trench structure 431 is transferred to the first anti-reflective layer 220 of the patterning layer 200 using a dry etching process, thereby forming the second set of trenches G2 on the surface of the first anti-reflective layer 220 on which the first set of trenches G1 has already been formed. Furthermore, during the etching process, the second trench structure 431 (i.e., the remaining second sacrificial layer 430) and the second mask layer 410 are completely removed. Figure 9 In the planar diagram of the semiconductor structure shown, the first set of trenches G1 and the second set of trenches G2 have an angle of 120°.

[0097] Optionally, such as Figures 10 to 13 As shown, the step of "forming the third set of trenches G3 in the pattern definition layer 200" may specifically include:

[0098] A third mask layer 510 is formed on the surface of the pattern definition layer 200, and the third mask layer 510 fills the first set of trenches G1 and the second set of trenches G2.

[0099] A third trench structure 531 is formed on the surface of the third mask layer 510 by a spacing doubling process;

[0100] Using the third mask layer 510 as a mask, the pattern definition layer 200 is etched, and the third trench structure 531 is transferred to the pattern definition layer 200 to form the third set of trenches G3.

[0101] Furthermore, such as Figures 10 to 13 As shown, based on the above-described process design for forming the third set of trenches G3, in this embodiment, the step of "forming the third mask layer 510 on the surface of the pattern definition layer 200" may specifically include:

[0102] A fourth passivation layer 511 is formed on the surface of the pattern definition layer 200;

[0103] A fourth anti-reflection layer 512 is formed on the surface of the fourth passivation layer 511, and the fourth anti-reflection layer 512 and the fourth passivation layer 511 together form a third mask layer 510.

[0104] Furthermore, such as Figures 10 to 13As shown, based on the above-described process design for forming the third set of trenches G3, in this embodiment, the step of "forming the third trench structure 531 on the surface of the third mask layer 510 by a spacing doubling process" may specifically include:

[0105] A third photoresist layer 520 is formed on the surface of the third mask layer 510;

[0106] The third photoresist layer 520 is patterned to form the third opening 521;

[0107] A third sacrificial layer 530 is formed on the surface of the third mask layer 510 and the third photoresist layer 520, and the third sacrificial layer 530 covers the sidewall and bottom wall of the third opening 521.

[0108] The third sacrificial layer 530 located on the surface of the third mask layer 510 and the top of the third photoresist layer 520 is removed by etching, and the remaining third sacrificial layer 530 is the third trench structure 531.

[0109] Specifically, such as Figure 10 The diagram illustrates a typical semiconductor structure in the step of "forming a third photoresist layer 520 on the third mask layer 510". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1 and a second set of trenches G2, a third mask layer 510, and a patterned third photoresist layer 520. The third mask layer 510 is formed on the surface of the pattern definition layer 200 and fills the first set of trenches G1 and the second set of trenches G2 on the surface of the first anti-reflective layer 220. The third mask layer 510 includes a fourth passivation layer 511 and a fourth anti-reflective layer 512. The third photoresist layer 520 is formed on the surface of the third mask layer 510, and the third photoresist layer 520 forms a third opening 521 through patterning.

[0110] Furthermore, in this embodiment, the fourth passivation layer 511 can be formed on the pattern definition layer 200 by spin coating.

[0111] Furthermore, in this embodiment, the material of the fourth antireflective layer 512 may include, but is not limited to, silicon oxynitride.

[0112] like Figure 11The diagram illustrates a typical semiconductor structure in the step of "forming a third sacrificial layer 530 on the surfaces of the third mask layer 510 and the third photoresist layer 520". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1 and a second set of trenches G2, a third mask layer 510, a patterned third photoresist layer 520, and a third sacrificial layer 530. The third sacrificial layer 530 is formed on the surface of the third mask layer 510 and the remaining surface of the third photoresist layer 520; that is, the third sacrificial layer 530 covers the surface of the third mask layer 510 exposed to the third opening 521, and also covers the sidewalls and bottom wall of the third opening 521.

[0113] Furthermore, in this embodiment, the material of the third sacrificial layer 530 may include, but is not limited to, silicon dioxide.

[0114] like Figure 12 The diagram illustrates a typical semiconductor structure in the step of "forming a third trench structure 531 on the surface of the third mask layer 510". Specifically, in this step, the semiconductor structure includes a substrate 100, a pattern definition layer 200 with a first set of trenches G1 and a second set of trenches G2, a third mask layer 510, and the remaining third sacrificial layer 530. The portion of the third sacrificial layer 530 located on the surface of the third mask layer 510 and the top surface of the third photoresist layer 520 is etched away via a pitch doubling process, and the remaining third sacrificial layer 530 forms the third trench structure 531. Furthermore, during the etching process, the remaining third photoresist layer 520 is completely removed.

[0115] like Figure 13 As shown, this represents a schematic diagram of the semiconductor structure in the step of "transferring the third trench structure 531 to the pattern definition layer 200 to form the third set of trenches G3". Figure 14 The diagram illustrates a plan view of a semiconductor structure during the step of "transferring the third trench structure 531 to the patterning layer 200 to form a third set of trenches G3". Specifically, in this step, the semiconductor structure includes a substrate 100 and a patterning layer 200 on which the first set of trenches G1, the second set of trenches G2, and the third set of trenches G3 are formed. In this step, the third trench structure 531 is transferred to the first anti-reflective layer 220 of the patterning layer 200 using a dry etching process, thereby forming the third set of trenches G3 on the surface of the first anti-reflective layer 220 on which the first set of trenches G1 and the second set of trenches G2 have already been formed. Furthermore, during the etching process, the third trench structure 531 (i.e., the remaining third sacrificial layer 530) and the third mask layer 510 are completely removed. Figure 14In the planar diagram of the semiconductor structure shown, the first group of trenches G1 and the third group of trenches G3 have an angle of 120°, and the second group of trenches G2 and the third group of trenches G3 have an angle of 120°, that is, the three groups of trenches G1, G2 and G3 have an angle of 120° with each other.

[0116] like Figure 15 As shown, it represents a schematic diagram of the semiconductor structure in the step of "forming the hole h of the pattern definition layer 200", and Figure 16 A planar view of the semiconductor structure in this step is shown representatively. Specifically, in this step, after forming three sets of trenches G1, G2, and G3 in the first antireflective layer 220, a hole h is formed in the first passivation layer 210 at the intersection of the three sets of trenches G1, G2, and G3 in the first antireflective layer 220. Since the three sets of trenches G1, G2, and G3 have an included angle of 120° with each other, the hole h formed in the pattern definition layer 200 at the intersection of the three sets of trenches G1, G2, and G3 is hexagonal.

[0117] like Figure 17 As shown, it represents a schematic diagram of the semiconductor structure in the step of "forming the capacitor hole H", and Figure 18 A planar view of the semiconductor structure in this step is shown representatively. Specifically, in this step, as the hole h of the pattern definition layer 200 moves downward, under the effect of the etching load, the capacitor hole H changes from a hexagonal straight-edge profile at the top to an arc to form a more regular circle, and the electrode 101 in the substrate 100 is exposed at the bottom of the capacitor hole H.

[0118] It should be noted that the methods for forming capacitor holes shown in the accompanying drawings and described in this specification are merely a few examples of many methods capable of employing the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or steps of the methods for forming capacitor holes shown in the accompanying drawings or described in this specification.

[0119] Based on the detailed description of several exemplary embodiments of the method for forming capacitor holes proposed in this invention, an exemplary embodiment of the semiconductor structure proposed in this invention will be described below.

[0120] In this embodiment, the semiconductor structure proposed by the present invention has a capacitor hole, and the capacitor hole of the semiconductor structure is formed by the capacitor hole forming method proposed by the present invention and described in detail in the above embodiment.

[0121] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples among many semiconductor structures capable of employing the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any detail or component of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0122] In summary, the capacitor aperture formation method proposed in this invention uses a three-exposure process to form a hexagonal hole. During the downward transfer of this hole to form the capacitor aperture, under the action of the etching load effect, the capacitor aperture changes from a straight hexagonal outline at the top to an arc, forming a more regular circle, thereby significantly improving the shape of the bottom of the capacitor aperture. Through the above design, this invention can ensure that the bottom of the capacitor aperture is circular, keeping the curvature of the capacitor aperture uniform.

[0123] The foregoing has described and / or illustrated exemplary embodiments of the method for forming capacitor holes and semiconductor structures proposed in this invention. However, the embodiments of this invention are not limited to the specific embodiments described herein; rather, components and / or steps of each embodiment may be used independently and separately from other components and / or steps described herein. Each component and / or step of one embodiment may also be used in combination with other components and / or steps of other embodiments. In describing the elements / components / etc. described and / or illustrated herein, the terms “a,” “an,” and “the above” are used to indicate the presence of one or more elements / components / etc. The terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to those listed. Furthermore, the terms “first” and “second” in the claims and specification are used only as illustrative marks and are not intended to limit the numerical scope of the subject matter.

[0124] Although the method for forming a capacitor hole and the semiconductor structure proposed in this invention have been described according to different specific embodiments, those skilled in the art will recognize that modifications can be made to the implementation of this invention within the spirit and scope of the claims.

Claims

1. A method for forming a capacitor aperture, characterized in that, Include: A substrate is provided in which electrodes are formed; A pattern definition layer is formed on the surface of the substrate; Three sets of grooves are formed sequentially in the pattern definition layer. The three sets of grooves intersect each other at 120°, and hexagonal holes are formed in the pattern definition layer at the intersection positions. Using the pattern definition layer as a mask, the substrate is etched along the holes to form capacitor holes in the substrate. Under the effect of etching load, the bottom of the capacitor hole is circular, and the electrode is exposed at the bottom of the capacitor hole.

2. The method for forming a capacitor hole according to claim 1, characterized in that, The step of forming a pattern definition layer on the substrate surface includes: A first passivation layer is formed on the surface of the substrate; A first anti-reflective layer is formed on the surface of the first passivation layer. The first anti-reflective layer and the first passivation layer together form the pattern definition layer. The three sets of trenches are formed on the first anti-reflective layer.

3. The method for forming a capacitor hole according to claim 2, characterized in that, After the first anti-reflective layer forms the three sets of trenches, the holes are formed in the first passivation layer at the intersection of the three sets of trenches.

4. The method for forming a capacitor hole according to claim 1, characterized in that, The step of forming the first set of trenches in the pattern definition layer includes: A first mask layer is formed on the surface of the pattern definition layer; A first trench structure is formed on the surface of the first mask layer by a spacing doubling process; Using the first mask layer as a mask, the pattern definition layer is etched to transfer the first trench structure to the pattern definition layer, thereby forming the first set of trenches.

5. The method for forming a capacitor hole according to claim 4, characterized in that, The step of forming the first trench structure on the surface of the first mask layer by the spacing doubling process includes: A first photoresist layer is formed on the surface of the first mask layer; The first photoresist layer is patterned to form a first opening; A first sacrificial layer is formed on the surface of the first mask layer and the first photoresist layer, and the first sacrificial layer covers the sidewall and bottom wall of the first opening; The first sacrificial layer located on the surface of the first mask layer and on top of the first photoresist layer is etched away, and the remaining first sacrificial layer is the first trench structure.

6. The method for forming a capacitor hole according to claim 4, characterized in that, The step of forming a first mask layer on the surface of the pattern definition layer includes: A second passivation layer is formed on the surface of the pattern definition layer; A second anti-reflective layer is formed on the surface of the second passivation layer, and the second anti-reflective layer and the second passivation layer together form the first mask layer.

7. The method for forming a capacitor hole according to claim 1, characterized in that, The step of forming the second set of trenches in the pattern definition layer includes: A second mask layer is formed on the surface of the pattern definition layer, and the second mask layer fills the first set of trenches; A second trench structure is formed on the surface of the second mask layer by a spacing doubling process; The pattern definition layer is etched using the second mask layer as a mask, and the second trench structure is transferred to the pattern definition layer to form a second set of trenches.

8. The method for forming a capacitor hole according to claim 7, characterized in that, The step of forming the second trench structure on the surface of the second mask layer by the spacing doubling process includes: A second photoresist layer is formed on the surface of the second mask layer; The second photoresist layer is patterned to form a second opening; A second sacrificial layer is formed on the surface of the second mask layer and the second photoresist layer, and the second sacrificial layer covers the sidewall and bottom wall of the second opening; The second sacrificial layer located on the surface of the second mask layer and on top of the second photoresist layer is etched away, and the remaining second sacrificial layer is the second trench structure.

9. The method for forming a capacitor hole according to claim 7, characterized in that, The step of forming a second mask layer on the surface of the pattern definition layer includes: A third passivation layer is formed on the surface of the pattern definition layer, and the third passivation layer fills the first set of trenches; A third anti-reflective layer is formed on the surface of the third passivation layer, and the third anti-reflective layer and the third passivation layer together form the second mask layer.

10. The method for forming a capacitor hole according to claim 9, characterized in that, The third passivation layer is formed on the pattern definition layer by a spin coating process.

11. The method for forming a capacitor hole according to claim 1, characterized in that, The step of forming the third set of trenches in the pattern definition layer includes: A third mask layer is formed on the surface of the pattern definition layer, and the third mask layer fills the first set of trenches and the second set of trenches; A third trench structure is formed on the surface of the third mask layer by a spacing doubling process; The pattern definition layer is etched using the third mask layer as a mask, and the third trench structure is transferred to the pattern definition layer to form the third set of trenches.

12. The method for forming a capacitor hole according to claim 11, characterized in that, The step of forming a third trench structure on the surface of the third mask layer by a spacing doubling process includes: A third photoresist layer is formed on the surface of the third mask layer; Pattern the third photoresist layer to form a third opening; A third sacrificial layer is formed on the surface of the third mask layer and the third photoresist layer, and the third sacrificial layer covers the sidewall and bottom wall of the third opening; The third sacrificial layer located on the surface of the third mask layer and on top of the third photoresist layer is etched away, and the remaining third sacrificial layer is the third trench structure.

13. The method for forming a capacitor hole according to claim 11, characterized in that, The step of forming a third mask layer on the surface of the pattern definition layer includes: A fourth passivation layer is formed on the surface of the pattern definition layer, and the fourth passivation layer fills the first set of trenches and the second set of trenches; A fourth anti-reflective layer is formed on the surface of the fourth passivation layer, and the fourth anti-reflective layer and the fourth passivation layer together form the third mask layer.

14. The method for forming a capacitor hole according to claim 13, characterized in that, The fourth passivation layer is formed on the pattern definition layer by a spin coating process.

15. A semiconductor structure having a capacitor hole, characterized in that, The capacitor hole is formed by the capacitor hole forming method according to any one of claims 1 to 14.

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