A bulk silicon metal gate fabrication process optimization method
By optimizing the bulk silicon metal gate fabrication process and controlling the metal gate width, the problem of inconsistent metal gates in traditional processes has been solved, thereby improving the electrical performance of semiconductor devices.
Patent Information
- Application Number
- CN202211309441.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2022-04-29
- Filing Date
- 2022-10-25
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2042-10-25
AI Technical Summary
Traditional polysilicon gate fabrication processes are complex and can easily lead to inconsistent or increased metal gate widths, affecting the electrical performance of semiconductor devices and failing to meet small size requirements.
The bulk silicon metal gate fabrication process involves forming sidewalls, an etch stop layer, and an interlayer dielectric layer outside the polysilicon gate, followed by grinding and etching to form etch trenches, depositing thin films and metal gate materials, controlling the width of the metal gate, and then using chemical mechanical polishing to form the metal gate.
Precise control of the metal gate width was achieved, avoiding inconsistencies and increases, ensuring the electrical performance of semiconductor devices, and meeting small size requirements.
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Figure CN115588613B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to an optimized method for fabricating bulk silicon metal gates. Background Technology
[0002] As the integration level of integrated circuits continues to increase, the size of semiconductor chips, as the main components of integrated circuits, is also decreasing. In the semiconductor transistor manufacturing process, the chip feature size is mainly measured by the gate width. Although reducing the gate width of semiconductor devices can meet the high integration requirements of integrated circuits, it also brings a series of negative effects. For example, the metal gate of a field-effect transistor has a voltage control function, but if the metal gate width is too short, a short circuit can easily occur between the source and drain, generating leakage current and causing the metal gate's control function to fail. Therefore, the manufacturing process of the metal gate should be continuously optimized. Optimization of the metal gate process can not only reduce leakage current by several times, but also control power consumption well. Under the same power consumption, the performance of the entire semiconductor device can be significantly improved.
[0003] However, the traditional polysilicon gate fabrication process is quite complex. After forming the channel layer and the polysilicon gate, the polysilicon gate is removed and a metal gate material is filled in. During the polysilicon gate removal process, problems such as over-etching or uneven etching of the sidewalls on both sides of the polysilicon gate and the bottom channel layer are very likely to occur. This can easily lead to an increase in the width or inconsistent width of the subsequently filled metal gate material, which cannot meet the small size requirements of the metal gate and affects the electrical performance of the entire semiconductor device. Summary of the Invention
[0004] To address the aforementioned problems in the existing technology, this invention provides an optimized method for the fabrication process of bulk silicon metal gates. The process is simple and reasonable, can meet the requirements for small-size fabrication of metal gates, and can avoid the problems of increased or inconsistent width of metal gates.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] An optimized method for fabricating a bulk silicon metal gate, characterized in that the fabrication process steps of the metal gate include: S1, providing a substrate and fabricating a polycrystalline silicon gate on the substrate;
[0007] S2. A sidewall, an etch stop layer, and an interlayer dielectric layer are sequentially formed on the outer surface of the polysilicon gate.
[0008] S3. The top of the interlayer dielectric layer, the etch stop layer, the sidewall, and the polysilicon gate are polished sequentially.
[0009] S4. The remaining polysilicon gate after etching and polishing forms an etching trench of a first fixed width.
[0010] S5. Deposit a thin film to cover the polished interlayer dielectric layer, the etching stop layer, the upper surface of the sidewall, and the inner end face of the etching trench.
[0011] S6. Etch the thin film on the upper surface of the interlayer dielectric layer, the etching stop layer, the sidewall, and the thin film at the bottom of the etching groove, wherein the width between the thin films in the etching groove is a second fixed width.
[0012] S7. Deposit metal gate material to fill the etching trench and cover the upper surface of the interlayer dielectric layer, etching stop layer, and sidewalls. The width of the metal gate material in the etching trench is the second fixed width.
[0013] S8. Grind the metal gate material on the upper surface of the interlayer dielectric layer, the etch stop layer, and the sidewall, as well as the upper part of the metal gate material in the etch groove, to form a metal gate.
[0014] Its further feature is that,
[0015] Furthermore, in step S2, the sidewall mainly comprises silicon nitride, the etching stop layer is made of silicon nitride, and the interlayer dielectric layer is made of silicon dioxide;
[0016] Furthermore, in step S3, a chemical mechanical polishing process is used to polish the sidewalls, etch stop layer, interlayer dielectric layer, and top of the polysilicon gate until the top of the polysilicon gate is exposed.
[0017] Furthermore, in step S4, the remaining polysilicon gate is removed using a photolithography etching process;
[0018] Furthermore, the first fixed width is greater than or equal to 6nm and less than or equal to 30nm;
[0019] Furthermore, in step S5, the thin film is deposited using atomic layer deposition, chemical vapor deposition, or furnace tube deposition, and the material of the thin film is one or more of silicon nitride, silicon oxide, or low-dielectric materials (LOW-K materials).
[0020] Furthermore, in step S6, the thin film is etched using a photolithography etching process, and the upper surface of the thin film obtained after etching is lower than the upper surface of the sidewall, the etching stop layer, and the interlayer dielectric layer.
[0021] Furthermore, the second fixed width is greater than or equal to 4nm and less than or equal to 28nm;
[0022] Furthermore, in step S8, the top of the metal gate is polished using a chemical mechanical polishing process.
[0023] The above-described structure of this invention achieves the following beneficial effects: In the metal gate fabrication process of this application, the metal gate is fabricated by first etching a polysilicon gate to form an etching trench, and then sequentially depositing a thin film and a metal gate material in the etching trench. After the thin film deposition, the second fixed width in the etching trench is consistent with the required width of the metal gate. Therefore, filling the etching trench with the second fixed width formed by the thin film with metal gate material is beneficial for controlling the width of the metal gate material, facilitating the fabrication of small-sized metal gates, and avoiding the problems of inconsistent or increased width of the metal gate. After etching the polysilicon gate, a thin film is deposited in the etching trench. The thin film compensates for the over-etching of sidewalls or channel layers caused by polysilicon etching, avoiding an increase in the width (i.e., the second fixed width) of the subsequently deposited metal gate material. Furthermore, the thin film compensates for the uneven or insufficient etching of sidewalls or channel layers caused by polysilicon etching, ensuring the consistency of the width of the metal gate obtained by subsequent filling and etching, effectively preventing the failure of the metal gate's control function, thereby ensuring the electrical performance of the entire semiconductor device. Attached Figure Description
[0024] Figure 1 This is a flowchart of the metal gate fabrication process optimization method of the present invention;
[0025] Figure 2 This is a schematic diagram of the main structure after the polysilicon gate is fabricated in step S1 of the present invention.
[0026] Figure 3 This is a schematic diagram of the main structure after the sidewalls, etch stop layer, interlayer dielectric layer, and polysilicon gate are polished in step S3 of the present invention.
[0027] Figure 4 This is a schematic diagram of the main view structure after the remaining polysilicon gate is etched in step S4 of the present invention.
[0028] Figure 5 This is a schematic diagram of the main structure after the thin film is deposited in step S5 of the present invention;
[0029] Figure 6 This is a schematic diagram of the main structure after thin film etching in step S6 of the present invention;
[0030] Figure 7 This is a schematic diagram of the main structure after the metal grid material is deposited in step S7 of the present invention;
[0031] Figure 8This is a schematic diagram of the main structure of the metal gate formed by grinding the interlayer dielectric layer, the etching stop layer, the metal gate material on the upper surface of the sidewall, and the upper part of the metal gate material in the etching trench in step S8 of the present invention. Detailed Implementation
[0032] Different embodiments or examples are provided below to implement different structures of the present invention. To simplify the disclosure of the present invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the present invention. Furthermore, reference numerals and / or reference letters may be repeated in different examples of the present invention; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0033] To address the problems in existing technologies, such as complex metal gate fabrication processes, and the tendency for over-etching or uneven / insufficient etching of the channel layer and sidewalls during polysilicon gate etching, leading to inconsistent or increased widths of the subsequently obtained metal gates, failing to meet the requirements for small-size metal gate fabrication, and affecting the electrical performance of the entire semiconductor device, this invention provides a specific embodiment of an optimized bulk silicon metal gate fabrication process, see [see details]. Figure 1 The specific steps of this process include: S1, providing a substrate 1, and fabricating a polysilicon gate 2 on the substrate 1. The polysilicon gate 2 is fabricated using a traditional process, namely, depositing a polysilicon gate layer on top of the substrate, and then etching the polysilicon gate layer using photolithography to form the polysilicon gate. See [link to relevant documentation]. Figure 2 .
[0034] S2. A sidewall 3, an etch stop layer 4, and an interlayer dielectric layer 5 are sequentially formed on the outer surface of the polysilicon gate 2. The sidewall 3 is primarily formed of silicon nitride, the etch stop layer 4 is made of silicon nitride, and the interlayer dielectric layer 5 is made of silicon dioxide. The specific steps for forming the sidewall 3, etch stop layer 4, and interlayer dielectric layer 5 are as follows: S21. A first silicon nitride layer is deposited on the outer surface of the polysilicon gate and above the substrate. Photolithography is used to etch the first silicon nitride above the substrate to form the sidewall 3. S22. A second silicon nitride layer is deposited on the sidewall 3 and the substrate on both sides. Photolithography is used to form the etch stop layer 4. S23. Silicon dioxide is deposited on the outer surface of the etch stop layer 4 to form the interlayer dielectric layer 5. During subsequent polysilicon gate etching, the interlayer dielectric layer protects the etch stop layer below it from being etched, and the etch stop layer protects the substrate below it from being etched.
[0035] S3. The interlayer dielectric layer 5, etch stop layer 4, sidewall 3, and the top of the polysilicon gate 2 are sequentially polished using a chemical mechanical polishing process until the top of the polysilicon gate 2 is exposed. (See attached image) Figure 3 ;
[0036] S4. The remaining polysilicon gate 2 after etching and polishing forms an etching trench 6 of the first fixed width. Figure 4 The first fixed width is set as 'a', with a width range of 6nm to 30nm. In this embodiment, 10nm is preferred. The remaining polysilicon gate 2 is removed using a photolithography etching process to form an etching trench 6. During photolithography, a mask is arranged above the interlayer dielectric layer 5, the etch stop layer 4, the sidewall 3, and the polysilicon gate 2. The mask includes an anti-reflection layer and a photoresist layer. The mask has a pattern matching the shape of the polysilicon gate. The light source in the photolithography machine etches the etching trench 6 through the circuit pattern on the mask, that is, the circuit pattern on the mask is transferred to the substrate.
[0037] S5. Deposit thin film 7, so that thin film 7 covers the upper surface of the polished interlayer dielectric layer 5, the etching stop layer 4, the sidewall 3, and the inner end face of the etching trench 6. See Figure 5 In this embodiment, atomic layer deposition is used to deposit thin film 7. The material of the thin film is one or more of silicon nitride, silicon oxide or low-k materials. In this embodiment, silicon nitride is preferred.
[0038] S6. A photolithography etching process is used to repeatedly etch the thin film 7 on the upper surface of the interlayer dielectric layer 5, the etching stop layer 4, and the sidewall 3, as well as the thin film 7 above the etching trench 6, so that the width between the thin films 7 in the etching trench is a second fixed width. (See...) Figure 6 The second fixed width is set to b, ranging from 4nm to 28nm. The second fixed width b is determined based on the pre-obtained metal gate size, and in this embodiment, 4nm is preferred. Using existing single-etching methods, obtaining small-sized gates is difficult and the process is unstable. However, using the multi-etching method of this application, the film thickness of a single etching is limited, and the error is smaller. Therefore, the multi-etching method is beneficial for controlling the etching accuracy of the film, ensuring that the film is precisely etched, thereby facilitating precise control of the accuracy of the second fixed width, so as to obtain a smaller metal gate.
[0039] S7. Deposit metal gate material 8, filling the outer surface of the thin film 7 within the etching trench 6, and covering the upper surfaces of the interlayer dielectric layer, the etching stop layer, and the sidewalls. The minimum width of the metal gate material within the etching trench is a second fixed width b defined by the thin film 7, i.e., the width of the metal gate material within the etching trench is equal to the gap width between the thin films. See [link to relevant documentation]. Figure 7 .
[0040] S8. A chemical mechanical polishing process is used to polish the metal gate material 8 on the upper surface of the interlayer dielectric layer 5, the etch stop layer 4, and the sidewall 3, as well as the upper part of the metal gate material in the etching tank 6, to form a metal gate. Specific polishing steps include: S81. Polishing the top metal gate material 8 of the sidewall 3, the etch stop layer 4, the interlayer dielectric layer 5, and the thin film 7 to rapidly thin the metal gate material 8, while simultaneously exposing the sidewall 3, the etch stop layer 4, and the interlayer dielectric layer 5; S82. Simultaneously polishing the exposed sidewall 3, the etch stop layer 4, the interlayer dielectric layer 5, and the metal gate material 8 until the tops of the sidewall 3, the etch stop layer 4, the interlayer dielectric layer 5, the thin film 7, and the metal gate material 8 are on the same horizontal plane. Figure 8 The metal gate material 8 obtained after grinding is the required metal gate.
[0041] The method described in this application controls the fabrication size of the metal gate by creating an etching trench and depositing a thin film (i.e., using atomic layer deposition to deposit the sidewall layer of the etching trench) within the etching trench. After the thin film is partially etched, the metal gate material is then filled into an etching trench of a second fixed width. This second fixed width is the final width of the metal gate and is preset according to the actual process and the electrical performance requirements of the semiconductor device, so that the width of the metal gate is controlled within the range of 4nm to 28nm. The metal gate fabrication method of this application reduces the width of the existing metal gate to 4nm, thereby meeting the small-size processing requirements of the metal gate.
[0042] This application utilizes atomic layer deposition (ALD) to deposit thin films. The thin film compensates for over-etching of sidewalls or channel layers at the bottom of the gate layer caused by polysilicon etching, thus avoiding an increase in the minimum width (i.e., the second fixed width) of the subsequently deposited metal gate material. Furthermore, the thin film compensates for uneven or insufficient etching of sidewalls or channel layers caused by polysilicon etching, ensuring a consistent metal gate width obtained through subsequent filling and etching. While meeting the small-size processing requirements of the metal gate, this application effectively prevents the failure of the metal gate's control function, ensuring the overall electrical performance of the semiconductor device.
[0043] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. A bulk silicon metal gate fabrication process optimization method, characterized in that, The manufacturing process steps of the metal gate electrode include: S1, providing a substrate, and manufacturing a polysilicon gate electrode on the substrate; S2, sequentially forming a side wall, an etching stop layer, and an interlayer dielectric layer on the outer surface of the polysilicon gate electrode; S3, sequentially grinding the top end of the interlayer dielectric layer, the etching stop layer, the side wall, and the polysilicon gate electrode; S4, etching the remaining polysilicon gate electrode to form an etching groove with a first fixed width; S5, depositing a thin film, so that the thin film covers the upper surface of the interlayer dielectric layer, the etching stop layer, and the side wall after grinding, and the inner end surface of the etching groove; S6, etching the thin film on the upper surface of the interlayer dielectric layer, the etching stop layer, and the side wall, and the thin film at the bottom end of the etching groove, and the width of the gap between the thin films in the etching groove is a second fixed width; In step S6, the thin film is etched multiple times by using a photolithography etching process, and the upper surface of the thin film obtained after etching is lower than the upper surfaces of the side wall, the etching stop layer, and the interlayer dielectric layer; S7, depositing a metal gate material, so that the metal gate material fills in the etching groove, and the metal gate material covers the upper surfaces of the interlayer dielectric layer, the etching stop layer, and the side wall, and the width of the metal gate material in the etching groove is the second fixed width; S8, grinding the metal gate material on the upper surfaces of the interlayer dielectric layer, the etching stop layer, and the side wall, and the upper part of the metal gate material in the etching groove to form a metal gate electrode, and the minimum width of the metal gate electrode is the second fixed width.
2. The method of claim 1, wherein the method is optimized for bulk silicon metal gate fabrication. In step S2, the side wall mainly includes first silicon nitride, the material of the etching stop layer is second silicon nitride, and the material of the interlayer dielectric layer is silicon dioxide.
3. The method of claim 2, wherein the method further comprises: The specific steps of sequentially forming the side wall, the etching stop layer, and the interlayer dielectric layer are: S21, depositing the first silicon nitride on the outer surface of the polysilicon gate electrode and above the substrate, etching the first silicon nitride above the substrate by using a photolithography etching process to form the side wall; S22, depositing the second silicon nitride above the side wall and the substrate on both sides of the side wall, and forming the etching stop layer by using a photolithography etching process; and S23, depositing the silicon dioxide on the outer surface of the etching stop layer to form the interlayer dielectric layer.
4. The method of claim 3, wherein the method further comprises: In step S3, the top end of the side wall, the etching stop layer, the interlayer dielectric layer, and the polysilicon gate electrode is ground by using a chemical mechanical grinding process until the top end of the polysilicon gate electrode is exposed.
5. The method of claim 4, wherein the method further comprises: In step S4, the remaining polysilicon gate electrode is removed by using a photolithography etching process.
6. The method of claim 5, wherein the method further comprises: The first fixed width is greater than or equal to 6 nm and less than or equal to 30 nm.
7. The method of claim 6, wherein the method further comprises: In step S5, the thin film deposition is achieved by using an atomic layer deposition process, a chemical vapor deposition process, or a furnace tube process, and the material of the thin film is one or more of silicon nitride, silicon oxide, or low dielectric constant material.
8. The method of claim 7, wherein the method is optimized for bulk silicon metal gate fabrication. The second fixed width is greater than or equal to 4 nm and less than or equal to 28 nm.
9. The method of claim 8, wherein the method further comprises: In step S8, the top end of the metal gate material is polished by a chemical mechanical polishing process. The polishing process includes: S81, polishing the top end of the metal gate material of the side wall, etching stop layer, interlayer dielectric layer and thin film, so as to thin the metal gate material and expose the top end of the side wall, etching stop layer and interlayer dielectric layer; S82, synchronously polishing the exposed side wall, etching stop layer, interlayer dielectric layer and metal gate material until the top end of the side wall, etching stop layer, interlayer dielectric layer, thin film and metal gate material are located at the same horizontal plane.
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