Method of manufacturing a silicon carbide semiconductor device

Abstract

A method of manufacturing a silicon carbide semiconductor device includes forming an electrode and forming a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of a material capable of deoxidizing an oxide film. By heat treating the gate wiring in or after the formation of the gate wiring, an oxide film formed on the connection wiring is deoxidized to remove oxygen from the oxide film into the gate wiring to remove the oxide film.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for manufacturing a silicon carbide (SiC) semiconductor device made of silicon carbide. BACKGROUND

[0002] For example, JP 2010-62402 A discloses a SiC semiconductor device including a metal oxide semiconductor field effect transistor (MOSFET) having, for example, a base layer and a source region at a semiconductor substrate made of SiC. The SiC semiconductor includes a drift layer and a base layer formed on the drift layer. In the SiC semiconductor device, a gate structure having a gate electrode is formed on a gate insulation film, and a connection wiring connected to the gate electrode is formed at a surface of the semiconductor substrate. The gate electrode and the connection wiring are made of polysilicon.

[0003] An interlayer insulation film is formed at the surface of the semiconductor substrate so as to cover the gate electrode and the connection wiring. A first contact hole for exposing, for example, the source region is formed at the interlayer insulation film, and a second contact hole for exposing the connection wiring is formed at the interlayer insulation film.

[0004] A source electrode connected to, for example, the source region through the first contact hole is formed on the interlayer insulation film, and a gate wiring connected to the connection wiring through the second contact hole is formed on the interlayer insulation film. A metal silicide film is arranged between the source electrode and the source region, and the like.

[0005] Such a SiC semiconductor device is manufactured in the following manner. After an interlayer insulation film is formed at a surface of a semiconductor substrate on which, for example, a base layer and a source region are formed, a first contact hole and a second contact hole are simultaneously formed. An oxide film is formed by thermal oxidation at a portion of the semiconductor substrate exposed from the first contact hole, and an oxide film is formed by thermal oxidation at the connection wiring exposed from the second contact hole. Since the semiconductor substrate is made of SiC, and the connection wiring is made of polysilicon, the oxide film on the connection wiring is formed thicker than the oxide film on the semiconductor substrate. When a metal silicide film is formed with a metal layer, the oxide film suppresses diffusion of atoms contained in the metal layer into, for example, the connection wiring.

[0006] Subsequently, the oxide film formed at the portion of the semiconductor substrate exposed from the first contact hole is removed while leaving the oxide film on the connection wiring. A metal layer made of, for example, nickel is formed to be disposed inside the first contact hole, and a metal silicide film is formed at the portion of the semiconductor substrate exposed from the first contact hole by heat treatment. Since the oxide film is formed on the connection wiring, diffusion of atoms contained in the metal layer into, for example, the connection wiring is suppressed, and variation in characteristics of the SiC semiconductor device is suppressed.

[0007] The oxide film formed on the connection wiring is removed. An upper electrode connected to, for example, the source region through the first contact hole is formed, and a gate wiring electrically connected to the connection wiring through the second contact hole is formed. SUMMARY

[0008] However, in order to manufacture the above-described SiC semiconductor device, it is necessary to remove the oxide film on the connection wiring by an additional process, and thus the manufacturing process is likely to be lengthened.

[0009] An object of the present application is to provide a method of manufacturing a SiC semiconductor device capable of reducing an additional process.

[0010] According to one aspect of the present disclosure, a method of manufacturing a SiC semiconductor device is provided. The method includes preparation of a semiconductor substrate, formation of an interlayer insulating film, formation of a first contact hole, formation of a second contact hole, formation of an oxide film, formation of a metal silicide film, removal of an unreacted metal layer, formation of an electrode, and formation of a gate wiring. The preparation of the semiconductor substrate includes formation of a gate insulating film, formation of a gate electrode, and formation of a connection wiring. The semiconductor substrate is made of silicon carbide and includes a substrate, a drift layer, a base layer, and an impurity region. The substrate has a first conductivity or a second conductivity. The drift layer has the first conductivity and is formed on the substrate. The base layer has the second conductivity and is formed on the drift layer. The impurity region has the first conductivity and is formed at a surface layer portion of the base layer. The gate insulating film is formed at a portion of the base layer between the drift layer and the impurity region. The gate electrode is formed on the gate insulating film. The connection wiring is formed on a surface of a side of the semiconductor substrate closer to the base layer and is connected to the gate electrode and made of polysilicon. The interlayer insulating film is formed to cover the base layer, the impurity region, the gate electrode, and the connection wiring. The first contact hole is formed at a first region including the interlayer insulating film to expose the base layer and the impurity region. The second contact hole is formed at a second region including the interlayer insulating film to expose the connection wiring. The oxide film is formed by thermal oxidation at a portion of the connection wiring exposed from the second contact hole. The metal layer is formed at a portion of the semiconductor substrate exposed from the first contact hole. The metal silicide film is formed by reacting the metal layer with the semiconductor substrate by heating. The unreacted layer that is a portion of the metal layer is removed. The unreacted layer is different from the metal silicide film. The electrode is formed to be electrically connected to the base layer and the impurity region through the first contact hole. The gate wiring is formed to be electrically connected to the connection wiring through the second contact hole. The gate wiring has a portion made of a material capable of deoxidizing the oxide film formed on the connection wiring to remove oxygen from the oxide film. In the formation of the gate wiring or after the formation of the gate wiring, the oxide film is deoxidized to remove oxygen from the oxide film into the gate wiring by heat treatment of the gate wiring to remove the oxide film.

[0011] According to the above method, the oxide film is removed by removing oxygen from the oxide film into the gate wiring at the time of heat treatment of the gate wiring. Therefore, without an additional process of removing the oxide film, it is possible to suppress a case where a manufacturing process takes a long time. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: - Figure 1 is a sectional view of a semiconductor substrate according to an embodiment of the present disclosure;

[0013] Figure 1 is a cross-sectional view of a SiC semiconductor device according to the first embodiment;

[0014] Figure 2A is a cross-sectional view showing Figure 1 manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0015] Figure 2B is a cross-sectional view showing Figure 2A manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0016] Figure 2C is a cross-sectional view showing Figure 2B manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0017] Figure 2D is a cross-sectional view showing Figure 2C manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0018] Figure 2E is a cross-sectional view showing Figure 2D manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0019] Figure 2F is a cross-sectional view showing Figure 2E manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0020] Figure 2G is a cross-sectional view showing Figure 2F manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0021] Figure 2H is a cross-sectional view showing Figure 2G manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0022] Figure 2I is a cross-sectional view showing Figure 2H manufacturing steps of the SiC semiconductor device shown in Fig. 1;

[0023] Figure 3 is a schematic view illustrating components of an interface between a semiconductor substrate and a gate insulating film;

[0024] Figure 4 illustrates a relationship between a thickness of an oxide film and a threshold value;

[0025] Figure 5 is a cross-sectional view of a SiC semiconductor device according to the second embodiment;

[0026] Figure 6A is a cross-sectional view showing Figure 5A cross-sectional view of a manufacturing process of a SiC semiconductor device;

[0027] Figure 6B is a cross-sectional view of a manufacturing process of a SiC semiconductor device showing Figure 6A the continuation of

[0028] Figure 6C is a cross-sectional view of a manufacturing process of a SiC semiconductor device showing Figure 6B the continuation of

[0029] Figure 6D is a cross-sectional view of a manufacturing process of a SiC semiconductor device showing Figure 6C the continuation of DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the same reference numbers are assigned to the same or equivalent portions to describe the same portions.

[0031] (First Embodiment)

[0032] A first embodiment will be described with reference to the accompanying drawings. The present embodiment describes an inverted MOSFET having a trench gate structure formed as a SiC semiconductor device. The structure of the SiC semiconductor device will be described below.

[0033] As Figure 1 shown, the SiC semiconductor device includes a semiconductor substrate 10 made of SiC. The semiconductor substrate 10 in the SiC semiconductor device includes an n + type substrate 11 made of SiC. In the present embodiment, the substrate 11 has an off-angle of 0-8 degrees with respect to, for example, a (0001) Si plane, and the substrate 11 has an n-type impurity concentration of, for example, 1.0 x 10 19 / cm 3 with a thickness of approximately 50 micrometers (pm) to 300 micrometers (pm) of, for example, nitrogen or phosphorus. In the present embodiment, a drain region is included in the substrate 11.

[0034] On the surface of the substrate 11, an n - type drift layer 12 made of SiC, and a p-type base layer 13 are formed by, for example, epitaxial growth. Hereinafter, the surface of the semiconductor substrate 10 closer to the base layer 13 side will be referred to as a first surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 closer to the substrate 11 side will be referred to as a second surface 10b of the semiconductor substrate 10.

[0035] The drift layer 12 has, for example, an n-type impurity concentration of approximately 1.0 x 10 15 / cm 3to 50.0 x 10 15 / cm 3 of n-type impurity concentration and a thickness of about 5 μm to 50 μm. The base layer 13 is formed on a part of the drift layer 12. The base layer 13 has, for example, a p-type impurity concentration of about 2.0 x 10 17 / cm 3 and a thickness of about 0.5 μm to 2 μm.

[0036] n + -type source regions 14 and p + -type contact regions 15 are formed at a surface layer portion of the base layer 13. The source regions 14 are formed in contact with side surfaces of the trenches 16, and the contact regions 15 are formed at a side opposite to the trenches 16 to sandwich the source regions 14. The source regions 14 have, for example, an n-type impurity concentration of 1.0 x 10 21 / cm 3 at the surface layer portion, in other words, a surface concentration. The contact regions 15 have, for example, a p-type impurity concentration of 1.0 x 10 21 / cm 3 at the surface layer portion, in other words, a surface concentration. In the present embodiment, the source regions 14 correspond to impurity regions. The contact regions 15 can be considered as regions of the base layer 13 having a higher impurity concentration. In other words, the contact regions 15 can be considered as a part of the base layer 13.

[0037] In the semiconductor substrate 10, the trenches 16 penetrate the source regions 14 and the base layer 13 and reach the drift layer 12. Each of the trenches 16 has, for example, a width of 6 μm. Although only a single trench 16 is shown in Figure 1 , a plurality of trenches 16 are provided at equal intervals in the right-and-left direction of Figure 1 to form a stripe pattern.

[0038] Each of the trenches 16 is filled with a gate insulating film 17 formed to cover a wall surface of each of the trenches 16, and a gate electrode 18 made of polysilicon or the like is formed on the gate insulating film 17. Thus, a trench gate structure is formed. In the present embodiment, a part of the wall surface of the trench 16 which is in contact with the base layer 13 corresponds to a surface of the base layer which is sandwiched between the impurity region and the drift layer.

[0039] The gate insulating film 17 is also formed on a surface other than the inner wall surface of the trench 16. The gate insulating film 17 is formed from the inner wall surface of the trench 16 over the first surface 10a of the semiconductor substrate 10. At a part of the gate insulating film 17 formed at the first surface 10a of the semiconductor substrate 10, a contact hole 17a for exposing the source regions 14 and the contact regions 15 is formed.

[0040] On a portion of the gate insulating film 17 formed at the first surface 10a of the semiconductor substrate 10, a connection wiring 19 connected to the gate electrode 18 is formed. The connection wiring 19 is formed by patterning the polysilicon formed on the first surface 10a of the semiconductor substrate 10 when the polysilicon is arranged at the trench 16 to form the gate electrode 18. The connection wiring 19 is electrically connected to the gate electrode 18 in a different cross section. Figure 1

[0041] When the polysilicon formed on the first surface 10a of the semiconductor substrate 10 is patterned to form the connection wiring 19, the polysilicon embedded in the trench 16 has a portion to be removed located closer to the aperture side of the trench 16. The aperture of the trench 16 can also be referred to as the opening of the trench 16. Therefore, the gate electrode 18 is not embedded on the side closer to the aperture of the trench 16. In other words, the gate insulating film 17 located on the side closer to the aperture of the trench 16 is exposed from the gate electrode 18. Although not particularly limited, for example, the trench 16 is in a state such that the gate electrode 18 is not arranged at a portion of the trench 16 about 50 nanometers (nm) to 100 nanometers (nm) from the aperture of the trench 16.

[0042] The interlayer insulating film 20 is formed on the first surface 10a of the semiconductor substrate 10 to cover, for example, the gate electrode 18 and the gate insulating film 17. The interlayer insulating film 20 for covering the gate electrode 18 is arranged to be embedded in the aperture of the trench 16. The interlayer insulating film 20 according to the present embodiment is made of boron phosphorus silicon glass (BPSG).

[0043] A contact hole 20a for exposing the source region 14 and the contact region 15 is connected to the contact hole 17a and formed at the interlayer insulating film 20. The contact hole 20a formed at the interlayer insulating film 20 functions as a single contact hole together with the contact hole 17a formed at the gate insulating film 17. Hereinafter, the contact hole 17a and the contact hole 20a are collectively referred to as a first contact hole 21a.

[0044] A second contact hole 21b for exposing the connection wiring 19 is formed at the interlayer insulating film 20. The pattern of the first contact hole 21a and the pattern of the second contact hole 21b are arbitrary. For example, the pattern can be a pattern having an array of a plurality of square shapes, a pattern having an array of a rectangular linear shape, or a pattern having an aligned linear shape.

[0045] A source electrode 22 is formed on the interlayer insulating film 20. The source electrode 22 is electrically connected to the source region 14 and the contact region 15 through the first contact hole 21a. A gate wiring 23 is formed on the interlayer insulating film 20. The gate wiring 23 is electrically connected to the connection wiring 19 through the second contact hole 21b.

[0046] ​The gate wiring 23 is made of a material capable of removing oxygen from the oxide film. In other words, the gate wiring 23 is made of a material capable of reducing oxygen in the oxide film or deoxidizing the oxide film. In this embodiment, the gate wiring 23 is made of aluminum or a material with aluminum as the main component. The source electrode 22 is not particularly limited. In this embodiment, the source electrode 22 and the gate wiring 23 are formed in the same process. Similar to the gate wiring 23, the source electrode 22 according to this embodiment is made of aluminum or a material with aluminum as the main component.

[0047] The source electrode 22 may be made of a different material than the gate wiring 23, and may not be made of a material capable of removing oxygen from the oxide film. In this embodiment, the source electrode 22 corresponds to an electrode.

[0048] A metal silicide film 24 is formed on the portion of the semiconductor substrate 10 exposed from the first contact hole 21a. The metal silicide film 24 reduces the contact resistance between the source region 14 and the contact region 15. The source electrode 22 is electrically connected to the source region 14 and the contact region 15 through the metal silicide film 24. The metal silicide film 24 according to this embodiment is made of, for example, nickel silicon (NiSi). The metal silicide film 24 corresponds to the first silicide film.

[0049] A drain electrode 25 electrically connected to the substrate 11 is formed on the side closer to the second surface 10b of the semiconductor substrate 10. In the SiC semiconductor device according to this embodiment, a MOSFET having an n-channel type inverted trench gate structure is formed using such a structure.

[0050] In such a SiC semiconductor device, when a voltage greater than or equal to a predetermined threshold voltage is applied to the gate electrode 18 while the voltage applied to the source electrode 22 is lower than the voltage applied to the drain electrode 25, an n-type inversion layer, i.e., a channel, is formed at the portion of the base layer 13 that contacts the trench 16. Electrons are supplied from the source region 14 through the inversion layer to the drift layer 12, thereby turning on the SiC semiconductor device.

[0051] The following reference Figures 2A to 2I Describes a method for manufacturing SiC semiconductor devices.

[0052] like Figure 2A As shown, a base layer 13, a source region 14, a contact region 15, a trench 16, a gate insulating film 17, a gate electrode 18, and a connection wiring 19 are formed on a semiconductor substrate 10 made of SiC. In this process, the gate insulating film 17 formed on the wall surface of the trench 16 is interconnected with the gate insulating film 17 formed on the first surface 10a of the semiconductor substrate 10.

[0053] In this embodiment, after forming the trench 16, polysilicon is formed, for example, by chemical vapor deposition (CVD), to form a gate electrode 18 for embedding in the trench 16, and the polysilicon is deposited on the first surface 10a of the semiconductor substrate 10. Next, the polysilicon formed on the first surface 10a of the semiconductor substrate 10 is patterned to form connection wiring 19 connected to the gate electrode 18. The portion of the polysilicon embedded in the trench 16 located closer to the apertures of the trench 16 is removed. Therefore, the gate electrode 18 is not embedded closer to the apertures of the trench 16.

[0054] Although not specifically shown, the dangling bonds at the interface between the semiconductor substrate 10 and the gate insulating film 17 are terminated by a nitrogen termination process in this embodiment using heat treatment in an oxygen-nitrogen atmosphere (i.e., a NO atmosphere). The dangling bonds at the interface between the base layer 13 and the gate insulating film 17 are terminated by nitrogen. As a result, the threshold voltage can be reduced by lowering the interface potential.

[0055] like Figure 2B As shown, an interlayer insulating film 20 is formed, for example, by CVD, to cover, for example, the gate electrode 18 and the connection wiring 19. The interlayer insulating film 20 is arranged to be embedded in a portion of the trench 16 closer to the aperture of the trench 16.

[0056] like Figure 2C As shown, for example, a first contact hole 21a for exposing the source region 14 and the contact region 15 and a second contact hole 21b for exposing the connection wiring 19 are simultaneously formed by etching using a mask (not shown).

[0057] like Figure 2D As shown, an oxide film 30 with a thickness of approximately 1 nm to 10 nm is formed on the portion of the connecting wiring 19 exposed from the second contact hole 21b by thermal oxidation. The oxide film 30 is formed, for example, by dry oxidation at 700°C for 40 minutes or by high-temperature oxidation (pyrooxidation) at 700°C for 5 minutes.

[0058] During the formation of the oxide film 30 in this process, oxygen may enter the semiconductor substrate 10 through the gate insulating film 17 from the side closer to the trench 16 aperture where the gate electrode 18 is not located. In this case, because the oxide film 30 is relatively thick, oxygen can easily enter the semiconductor substrate 10. Figure 3 As shown, when oxygen enters the semiconductor substrate 10, the nitrogen that was terminated at the interface with the gate insulating film 17 in the semiconductor substrate 10 is replaced by oxygen, and the interface state becomes higher, thereby the threshold voltage also becomes higher. Figure 4As shown, the inventors of the present application have carefully studied and confirmed that because the thickness of the oxide film 30 is greater than 10 nm, the threshold voltage rises to a value that is 10% or more higher than the reference value. The reference value described herein is the threshold value in the case where the thickness of the oxide film 30 is 0 nm. In other words, the threshold value of the voltage is 1. However, the threshold value can have an error of about 10% with respect to the reference value. Therefore, in the present embodiment, the thickness of the oxide film 30 is formed to be 10 nm or less.

[0059] As described above, the semiconductor substrate 10 according to the present embodiment is made of SiC, which is a material that is not possible to be oxidized compared to silicon. When the oxide film 30 is formed as a thin film of 10 nm or less, the oxide film is not substantially formed at the portion of the first surface 10a of the semiconductor substrate 10 that is exposed from the first contact hole 21a.

[0060] As Figure 2E shown, a metal layer 31, for example, nickel, is formed at the portion exposed from the first contact hole 21a by, for example, sputtering. Before performing this process, wet etching can be performed to remove the oxide film that can be formed at the portion of the first surface 10a of the semiconductor substrate 10 that is exposed from the first contact hole 21a, for example, if necessary.

[0061] As Figure 2F shown, the semiconductor substrate 10 exposed from the first contact hole 21a reacts with the metal layer 31 to form a metal silicide film 24 by heat treatment at about 700 to 800°C under a nitrogen atmosphere. At this time, because the oxide film 30 is formed on the connection wiring 19 exposed from the second contact hole 21b, it is possible to suppress the diffusion of atoms included in the metal layer 31 into, for example, the connection wiring 19.

[0062] In the present embodiment, because a nickel film is formed as the metal layer 31, a metal silicide film 24 made of nickel silicon is formed. The portion of the metal layer 31 that does not react with the semiconductor substrate 10, that is, SiC, remains as an unreacted metal layer 31a.

[0063] As Figure 2G shown, the unreacted metal layer 31a is removed by, for example, wet etching. Subsequently, although not specifically shown, the contact resistance between the metal silicide film 24 and the semiconductor substrate 10, in other words, between the source region 14 and the contact region 15, is further reduced by heat treatment at about 950 to 1050°C.

[0064] As Figure 2HAs shown, after the metal layer is formed on the interlayer insulating film 20 by, for example, CVD, the metal layer is patterned by, for example, etching using a mask (not shown) to form the source electrode 22 and the gate wiring 23. As described above, the gate wiring 23 is made of a material capable of removing oxygen from the oxide film 30. In the present embodiment, since the source electrode 22 and the gate wiring 23 are formed by patterning a common metal layer, the material of the source electrode 22 is the same as the material of the gate wiring 23.

[0065] As Figure 2I shown, the film quality of each of the source electrode 22 and the gate wiring 23 is stabilized by heating the gate wiring 23 to a temperature equal to or lower than the melting point of the gate wiring 23 and higher than or equal to the temperature of, for example, soldering, which is a subsequent process. The oxide film 30 formed on the connection wiring 19 at this time is made of a material capable of removing oxygen from the oxide film 30. Therefore, the oxide film 30 can be removed by delivering oxygen to the gate wiring 23. In other words, in the present embodiment, the stabilization of the film quality of the gate wiring 23 and the removal of the oxide film 30 are performed in the same process. In the present embodiment, this process corresponds to heat treatment of the gate wiring 23. As described above, the SiC semiconductor device according to the present embodiment is manufactured.

[0066] As described above, according to the present embodiment, the gate wiring 23 is made of a material capable of removing oxygen from the oxide film 30. When heat treatment for stabilizing the film quality of the gate wiring 23 is performed, the oxide film 30 is removed by removing oxygen from the oxide film 30 into the gate wiring 23. Therefore, there is no additional process for removing the oxide film 30, and thus it is possible to suppress a case where the manufacturing process takes a longer time.

[0067] In the present embodiment, when the oxide film 30 is formed by performing nitrogen termination treatment after the gate electrode 18 is formed, the thickness of the oxide film 30 is set to be less than or equal to 10 nm. Therefore, it is possible to suppress a case where nitrogen at the interface of the base layer 13 and the gate insulating film 17 is replaced with oxygen, and it is possible to suppress a case where the on-resistance increases due to an increase in the interface potential.

[0068] (Second Embodiment)

[0069] A second embodiment will be described below. In contrast to the first embodiment, a barrier metal film is formed. Other configurations are the same as those of the first embodiment, and thus a description of the same configurations will be omitted below.

[0070] In the semiconductor device according to the present embodiment, as Figure 5As shown, the source electrode 22 and the gate wiring 23 each have barrier metal films 22a and 23a, and each has main wiring portions 22b and 23b. The main wiring portions 22b and 23b are stacked on the barrier metal films 22a and 23a, respectively. The main wiring portion 23b is made of a material having, for example, aluminum or an alloy with aluminum as the main component. The barrier metal films 22a and 23a are made of a material used to suppress the diffusion of aluminum from the main wiring portions 22b and 23b into, for example, the connecting wiring 19. The barrier metal films 22a and 23a are made of a material capable of removing oxygen from the oxide film 30 and more difficult for atoms to diffuse compared to the main wiring portions 22b and 23b. According to this embodiment, the barrier metal films 22a and 23a are made of, for example, titanium.

[0071] A metal silicide film 26 is formed between the barrier metal film 23a of the gate wiring 23 and the connection wiring 19. The metal silicide film 26 reduces the contact resistance between the barrier metal film 23a and the connection wiring 19. According to this embodiment, the metal silicide film 26 is made of titanium silicon. The metal silicide film 26 corresponds to a second metal silicide film.

[0072] The configuration of the SiC semiconductor device according to this embodiment has been described above. The following refers to... Figures 6A to 6D A method for manufacturing a SiC semiconductor device according to this embodiment is described.

[0073] In this embodiment, when through Figure 2G After the unreacted metal layer 31a is removed in the process shown, a barrier metal layer 40 is formed by, for example, a CVD method, as described above. Figure 6A As shown. The barrier metal layer 40 is made of a material that diffuses almost no atoms compared to the main wiring portion 23b. In this embodiment, a titanium layer is formed as the barrier metal layer 40.

[0074] like Figure 6B As shown, heat treatment is performed in a nitrogen atmosphere at approximately 700 to 800°C. As a result, the oxide film 30 is removed by delivering oxygen to the barrier metal layer 40. Because the heat treatment is performed at 700 to 800°C, the connection wiring 19 reacts with the barrier metal layer 40 to form a metal silicide film 26. Since the barrier metal layer 40 is made of a material from which atoms are difficult to diffuse, the diffusion of atoms contained in the barrier metal layer 40 into, for example, the connection wiring 19 can be suppressed in this process. In other words, the barrier metal layer 40 is made of a material capable of removing oxygen from the oxide film 30 because this material makes it difficult for atoms to diffuse into, for example, the connection wiring 19 when the metal silicide film 26 is formed. In this embodiment, this process corresponds to the heat treatment of the gate wiring 23.

[0075] like Figure 6CThe main wiring layer 41 included in the main wiring portions 22b, 23b is formed as shown. The main wiring layer 41 is formed of a metal material such as aluminum or copper. Figure 6D The barrier metal layer 40 and the main wiring layer 41 are patterned by, for example, etching using a mask (not shown) to form the source electrode 22 and the gate wiring 23 as shown.

[0076] Although not particularly shown, the SiC semiconductor device according to the present embodiment is manufactured by performing similar procedures to those in the first embodiment to stabilize the film quality of each of the source electrode 22 and the gate wiring 23. In the present embodiment, since the oxide film has been removed, the oxide film 30 is not removed in this procedure. Figure 2I

[0077] According to the present embodiment, as described above, the barrier metal layer 40, that is, the barrier metal film 23a included in the gate wiring 23 is made of a material capable of removing oxygen from the oxide film 30. At the time of performing the heat treatment for forming the metal silicide film 26, the oxide film 30 is removed by entering oxygen from the oxide film 30 into the barrier metal layer 40. Therefore, a separate procedure for removing the oxide film 30 is not required, and thus, similar advantageous effects to those of the first embodiment can be obtained.

[0078] (Other Embodiments)

[0079] Although the present disclosure has been described in accordance with the embodiments, it should be understood that the present disclosure is not limited to such embodiments or constructions. The present disclosure includes various modifications and variations of the various embodiments described herein. In addition, while various elements of the embodiments have been shown and described as being combined in various combinations and configurations, other combinations and configurations, including more, less, or only a single element, are also within the spirit and scope of the disclosure.

[0080] In the above-described embodiments, a MOSFET having an n-channel trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type has been described. However, a semiconductor device formed of a MOSFET having a p-channel trench gate structure in which the conductivity type of each component is reversed with respect to the n-channel type can also be used. In addition to the MOSFET, the semiconductor device can be formed of an IGBT having the same structure. In the case of the IGBT, the n + type substrate 11 is changed to a p + type collector layer. Other than this, the IGBT is similar to the MOSFET described in the first embodiment.

[0081] Each of the above-described embodiments describes a semiconductor device including a trench gate structure. However, the semiconductor device can also have a planar gate structure.

[0082] ​In each of the embodiments, the oxide film 30 formed in manufacturing the semiconductor device can have a thickness of 10 nm or more. Even if such an oxide film 30 is formed, an additional process for removing the oxide film 30 does not need to be performed in the first and second embodiments. Thus, the manufacturing process can be shortened.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, the method comprising: preparing a semiconductor substrate made of silicon carbide, the semiconductor substrate including a substrate, a drift layer, a base layer, and an impurity region, the substrate having a first conductivity or a second conductivity, the drift layer having the first conductivity and formed on the substrate, the base layer having the second conductivity and formed on the drift layer, the impurity region having the first conductivity and formed at a surface layer portion of the base layer, the preparation of the semiconductor substrate including forming a gate insulating film at a portion of the base layer between the drift layer and the impurity region, forming a gate electrode on the gate insulating film, and forming a connection wiring over a surface of a side of the semiconductor substrate closer to the base layer, the connection wiring connected to the gate electrode and made of polysilicon; forming an interlayer insulating film to cover the base layer, the impurity region, the gate electrode, and the connection wiring; forming a first contact hole at a first region including the interlayer insulating film to expose the base layer and the impurity region; forming a second contact hole at a second region including the interlayer insulating film to expose the connection wiring; forming an oxide film at a portion of the connection wiring exposed from the second contact hole by thermal oxidation; forming a metal layer at a portion of the semiconductor substrate exposed from the first contact hole; reacting the metal layer with the semiconductor substrate by heating to form a metal silicide film; removing an unreacted metal layer as a portion of the metal layer different from the metal silicide film; forming an electrode electrically connected to the base layer and the impurity region through the first contact hole; and forming a gate wiring electrically connected to the connection wiring through the second contact hole, the gate wiring having a portion made of a material capable of deoxidizing the oxide film formed on the connection wiring to remove oxygen from the oxide film, wherein, in or after the formation of the gate wiring, the oxide film is deoxidized to remove oxygen from the oxide film into the gate wiring to remove the oxide film by heat treatment of the gate wiring, wherein the preparation of the semiconductor substrate further includes terminating dangling bonds at an interface between the semiconductor substrate and the gate insulating film with nitrogen after the formation of the gate electrode, and wherein, in the formation of the oxide film, the oxide film is formed to have a thickness of 10 nanometers or less.

2. The method according to claim 1, wherein the heat treatment of the gate wiring includes stabilizing a film quality of the gate wiring after the formation of the gate wiring, and wherein the oxide film is removed in the stabilizing of the film quality of the gate wiring.

3. The method according to claim 1, wherein the metal silicide film is a first metal silicide film, wherein the formation of the gate wiring includes: forming a main wiring layer; ​ forming a barrier metal layer before formation of the main wiring layer, the barrier metal layer being made of a material capable of deoxidizing the oxide film to remove oxygen from the oxide film, the material being more difficult to diffuse atoms than the main wiring layer; and patterning the barrier metal layer and the main wiring layer to form the gate wiring, wherein heat treatment of the gate wiring includes, after formation of the barrier metal layer and before formation of the main wiring layer, forming a second metal silicide film by reacting the barrier metal layer with the connection wiring, and wherein the oxide film is removed in the formation of the second metal silicide film.

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