Signal synchronization system, method, device and electronic equipment

Abstract

The present application discloses a signal synchronization system, method, device and electronic device. The system includes: a control module and a remote module, wherein the control module is used to collect time-division duplex switch signals and transmit data frames containing time-division duplex switch signals and reference clocks to the remote module, wherein the reference clock is the clock corresponding to the time-division duplex switch signal when it is collected; the remote module is used to synchronize the clock in the remote module with the reference clock in the data frame, parse the data frame, obtain the alignment information of the time-division duplex switch signal, and output the time-division duplex switch signal according to the alignment information. The present application solves the technical problem in the prior art that the time-division duplex switch signal in the passive optical transmission network has output asynchronism, resulting in signal interference.

Description

Technical Field

[0001] The present application relates to the field of wireless communications, and in particular, to a signal synchronization system, method, device and electronic equipment. Background Art

[0002] Since the 5G distributed coverage system based on fiber-to-the-home (FTTH) passive optical network uses FTTH passive optical network transmission, the installation distance of different distribution units (DU units) may be close, and the fiber optic jumper path of the centralized unit (CU unit) is different, resulting in a large difference in fiber optic transmission distance; if the difference in fiber optic transmission distance between two DU units and a CU unit at a close distance exceeds 4km, the time division duplexing (TDD) signal delay difference between the two DU units will exceed the uplink and downlink protection interval of the TDD system, resulting in crosstalk between the uplink and downlink signals of the two DU units, affecting the uplink noise floor of the DU units.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide a signal synchronization system, method, device and electronic device to at least solve the technical problem in the prior art that time division duplex switch signals in a passive optical transmission network have output asynchrony, resulting in signal interference.

[0005] According to one aspect of an embodiment of the present application, a signal synchronization system is provided, comprising: a control module and a remote module, wherein the control module is used to collect time-division duplex switch signals and transmit data frames containing the time-division duplex switch signals and a reference clock to the remote module, wherein the reference clock is a clock corresponding to when the time-division duplex switch signals are collected; and the remote module is used to synchronize the clock in the remote module with the reference clock in the data frame, parse the data frame, obtain alignment information of the time-division duplex switch signal, and output the time-division duplex switch signal according to the alignment information.

[0006] Optionally, the control module includes a crystal oscillator, a first field programmable gate array and a first optical module, the crystal oscillator is used to provide a reference clock, the first field programmable gate array is used to collect time division duplex switch signals based on the reference clock, and the first optical module is used to convert data frames into optical signals and transmit them to the remote module, wherein the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal.

[0007] Optionally, the first field programmable gate array is further used to send a data packet consisting of a time division duplex frame header signal, a time slot length signal and a control command to the first optical module, wherein the control command stores alignment information of the time division duplex switch signal.

[0008] Optionally, the first field programmable gate array is also used to determine a frame starting point, wherein the frame starting point is a transition point between the longest uplink time slot within a preset acquisition time length and the downlink time slot; based on the frame starting point, the length of each uplink time slot and the length of the downlink time slot after the frame starting point within the preset acquisition time length are determined; a time slot length signal is determined based on the uplink time slot length and the downlink time slot length; and a data frame is determined based on the time slot length signal and the time division duplex frame header signal.

[0009] Optionally, the remote module includes a phase-locked loop, a second field programmable gate array and a second optical module, the second optical module is used to receive the data frame sent by the first optical module, the phase-locked loop synchronizes the clock in the remote module to the reference clock in the data frame, the second field programmable gate array is used to parse the data frame, obtain the alignment information of the time division duplex switch signal, and adjust the time division duplex switch signal according to the alignment information and then output it.

[0010] Optionally, the second field programmable gate array is further used to separate the time division duplex frame header signal and the time slot length signal from the data frame, and determine the time division duplex switch signal according to the time division duplex frame header signal and the time slot length signal.

[0011] Optionally, the time division duplex switch signal consists of multiple subframes, each subframe consists of multiple symbols, the first symbol of the first subframe of the multiple subframes is used to transmit the frame header signal of the data frame, the first symbols of other subframes of the multiple subframes are used to transmit the time slot length signal, the second symbol of each subframe is used to transmit the time division duplex frame header signal, the third symbol of each subframe is used to transmit the control command, and the fourth symbol of each subframe is used to transmit the data of the remote module, wherein the other subframes are subframes other than the first subframe in the multiple subframes.

[0012] Optionally, different remote modules occupy frames with different symbols, and the frame sequence numbers occupied by the remote modules are allocated by the control module.

[0013] Optionally, the remote module determines the transmission delay between the remote module and the control module within the occupied frame sequence number; and determines the time to output the time division duplex switch signal based on the transmission delay.

[0014] According to another aspect of an embodiment of the present application, a signal synchronization method is also provided, including: receiving a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; after synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain alignment information of the time division duplex switch signal; and outputting the time division duplex switch signal based on the alignment information.

[0015] According to another aspect of the embodiment of the present application, a signal synchronization device is also provided, including: a receiving unit, used to receive a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; a parsing unit, used to synchronize the clock in the remote end with the reference clock in the data frame, and then parse the data frame to obtain alignment information of the time division duplex switch signal; and an output unit, used to output the time division duplex switch signal according to the alignment information.

[0016] According to another aspect of the embodiment of the present application, there is also provided an electronic device, including: a memory for storing program instructions; a processor, connected to the memory, for executing program instructions to implement the following functions: receiving a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; after synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain alignment information of the time division duplex switch signal; and outputting the time division duplex switch signal based on the alignment information.

[0017] According to another aspect of the embodiments of the present application, a non-volatile storage medium is provided, which includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the above-mentioned signal synchronization method by running the computer program.

[0018] In an embodiment of the present application, the aligned output of the time-division duplex switch signal is achieved through a control module and a remote module. The control module is used to collect the time-division duplex switch signal and transmit a data frame containing the time-division duplex switch signal and a reference clock to the remote module, wherein the reference clock is a clock corresponding to when the time-division duplex switch signal is collected; the remote module is used to synchronize the clock in the remote module to the reference clock in the data frame, and then parse the data frame to obtain the alignment information of the time-division duplex switch signal, thereby achieving the purpose of outputting the time-division duplex switch signal based on the alignment information, thereby achieving the technical effect of reducing signal interference, and further solving the technical problem of the output asynchronism of the time-division duplex switch signal in the passive optical transmission network in the prior art, which leads to signal interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is an application architecture diagram of a passive optical distribution system of related technology;

[0021] Figure 2is a structural diagram of a signal synchronization system according to an embodiment of the present application;

[0022] Figure 3a is a partial architecture diagram of a signal synchronization system according to an embodiment of the present application;

[0023] Figure 3b is a complete architecture diagram of a signal synchronization system according to an embodiment of the present application;

[0024] Figure 4 is a flow chart of a signal synchronization method according to an embodiment of the present application;

[0025] Figure 5 is a structural diagram of a signal synchronization device according to an embodiment of the present application;

[0026] Figure 6 It is a hardware structure block diagram of a computer terminal (or electronic device) for implementing a signal synchronization method according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] First, some nouns or terms that appear in the process of explaining the embodiments of the present application are subject to the following explanations:

[0030] Fiber to the Home (FTTH) is a transmission method for optical fiber communication. Specifically, FTTH refers to installing the optical network unit (ONU) at the home or enterprise user. It is the optical access network application type closest to the user in the optical access series except FTTD (fiber to the desktop). The significant technical features of FTTH are that it not only provides a larger bandwidth, but also enhances the transparency of the network to the data format, rate, wavelength and protocol, relaxes the requirements on environmental conditions and power supply, and simplifies maintenance and installation.

[0031] Time Division Duplexing (TDD) refers to the use of time staggering to distinguish uplink (mobile to base station) and downlink (base station to mobile) services to avoid interference. In a TDD mode mobile communication system, reception and transmission are in different time slots of the same frequency channel (i.e., carrier), and the reception and transmission channels are separated by guaranteed time.

[0032] MDAS (Multiservice Distributed Access System Solution) is a multi-service distribution system that can support multiple operators, multiple standards, multiple carriers, and integrate WLAN systems to solve voice and data service needs in one step. Compared with traditional analog distribution systems, it also has the characteristics of hybrid networking, delay compensation, automatic carrier tracking, and low uplink noise floor.

[0033] SERDES: It is the abbreviation of SERializer / DESerializer. It is a mainstream time division multiplexing (TDM) and point-to-point (P2P) serial communication technology. That is, multiple low-speed parallel signals are converted into high-speed serial signals at the sending end, and then passed through the transmission media (optical cable or copper wire), and finally the high-speed serial signals are converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology makes full use of the channel capacity of the transmission media, reduces the number of transmission channels and device pins required, and increases the transmission speed of the signal, thereby greatly reducing the communication cost.

[0034] The 5G distributed coverage system based on ftth passive optical network is a new architecture with low complexity. It uses core components to achieve the extended coverage of 4G+5G MIMO (multiple input multiple output) signals transmitted by optical fiber. During construction and installation, the system can use the existing ftth passive optical network transmission without re-implementing optical fiber wiring installation, which greatly reduces the construction difficulty and cost of 5G signal coverage.

[0035] Compared with the traditional MDAS optical distribution system, this system has a simplified product hardware architecture, does not rely on imported components, and has strong supplyability. At the same time, it can make full use of the existing ftth optical network transmission to reduce construction costs. It can use a single optical fiber to transmit 4G+5G MIMO signals, which improves the utilization rate of optical fiber resources. Compared with micro-distribution systems, this system has a wider coverage and uses optical fiber transmission for better signal quality.

[0036] The passive optical distribution system in the related art consists of a CU unit (centralized unit) and a DU unit (distributed unit). The application architecture is as follows: Figure 1 The transponder (HUB) is connected to the CU unit through a network cable, and the CU unit is connected to the passive optical network through an optical fiber. The passive optical network contains multiple optical splitters. Figure 1 Only two optical splitters are shown in the figure. Different optical splitters are connected through optical fibers. The optical splitters are connected to the DU unit through optical fibers and output MIMO signals.

[0037] Traditional MDAS systems generally adopt a three-level architecture of AU (access unit)-EU (extension unit)-RU (remote unit), and the optical transmission network is generally newly built and dedicated. RUs with a closer installation distance are generally directly connected to the EU through optoelectronic composite cables. Therefore, the time delay between RUs with a closer distance is smaller and no crosstalk will occur. The traditional micro-step system uses feeder lines to extend coverage, which has a shorter transmission and coverage distance and will not cause crosstalk problems.

[0038] In the related technology, since the 5G distributed coverage system based on FTTH passive optical network uses FTTH passive optical network transmission, the installation distance of different DU units may be relatively close, and the difference in optical fiber transmission distance due to different optical fiber jumper paths with the CU unit may be relatively large; if the difference in optical fiber transmission distance between two DU units with similar distances and the CU unit exceeds 4km, the TDD signal delay difference between the two DU units will exceed the uplink and downlink protection interval of the TDD system, resulting in crosstalk between the uplink and downlink signals of the two DU units, affecting the uplink noise floor of the DU unit.

[0039] In order to solve the above problems, the embodiments of the present application provide corresponding solutions, which are described in detail below.

[0040] Figure 2 is a structural diagram of a signal synchronization system according to an embodiment of the present application, such as Figure 2As shown, the signal synchronization system 200 includes: a control module 202 and a remote module 204, wherein the control module is used to collect the time division duplex switch signal and transmit the data frame containing the time division duplex switch signal and the reference clock to the remote module, wherein the reference clock is the clock corresponding to when the time division duplex switch signal is collected; the remote module is used to synchronize the clock in the remote module to the reference clock in the data frame, parse the data frame, obtain the alignment information of the time division duplex switch signal, and output the time division duplex switch signal according to the alignment information.

[0041] In an embodiment of the present application, the control module may be a TDD synchronization control module or a TDD-CU module, the remote module may be a TDD synchronization remote module or a TDD-RU module, and the signal synchronization system may be referred to as a passive optical distribution system. Alignment information refers to the amount of advance or delay adjustment, because the transmission delays of various RU units after transmission through different optical fiber paths are different, and each remote end needs to align the TDD switch signal, so it is necessary to adjust the original switch signal of each RU unit.

[0042] In the above-mentioned signal synchronization system, the control module includes a crystal oscillator, a first field programmable gate array and a first optical module. The crystal oscillator is used to provide a reference clock, the first field programmable gate array is used to collect time division duplex switch signals according to the reference clock, and the first optical module is used to convert data frames into optical signals and transmit them to the remote module, wherein the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal.

[0043] In the above signal synchronization system, the first field programmable gate array is also used to send a data packet consisting of a time division duplex frame header signal, a time slot length signal and a control command to the first optical module, wherein the control command stores alignment information of the time division duplex switch signal.

[0044] In an embodiment of the present application, the TDD-CU module is composed of a crystal oscillator (OSC), an FPGA (i.e., the first field programmable gate array mentioned above), and an optical module (i.e., the first optical module mentioned above). The crystal oscillator provides a reference clock for the FPGA, which is the system reference clock. The FPGA uses the reference clock to perform timed sampling of the input TDD switch signal according to the preset acquisition time. The preset acquisition time can be, for example, 10ms. It should be noted that the preset acquisition time is configurable and is not limited here. After sampling, the TDD frame header signal (i.e., the time division duplex frame header signal mentioned above) and each time slot length signal are obtained, and then the TDD frame header signal, the time slot length signal and the control instruction are packaged, and after framing, they are sent to the SERDES interface through GTX (high-speed serial transceiver), and then converted into an optical signal through the first optical module and transmitted to the TDD-RU module. At the same time, the TDD-CU module also receives access requests from different TDD-RU modules, generates control instructions after processing, and then sends them to each TDD-RU module. The TDD-CU module processes the access request as follows: Figure 3a The TDD-CU includes optical modules, SERDES, GTX, data deframing, command parsing, and DU access processing, thereby realizing the processing of access requests.

[0045] In the above-mentioned signal synchronization system, the first field programmable gate array is also used to determine the frame starting point, wherein the frame starting point is the transition point between the longest uplink time slot within the preset acquisition time length and the downlink time slot; based on the frame starting point, the length of each uplink time slot and the length of the downlink time slot after the frame starting point within the preset acquisition time length are determined; the time slot length signal is determined based on the uplink time slot length and the downlink time slot length; and the data frame is determined based on the time slot length signal and the time division duplex frame header signal.

[0046] In the embodiment of the present application, the input TDD switch signal is sampled at the TDD-CU end, and after finding the longest uplink time slot within the preset acquisition time length (such as 10ms), the transition point from the uplink time slot to the downlink time slot is marked as the frame start point; starting from the start point, the lengths of the subsequent downlink time slots and uplink time slots are measured in sequence until the measurement ends at the end of the above preset acquisition time length, and the obtained time slot lengths are recorded as L1, L2...LN. Optionally, for the first operator network, N is generally 8, and for the second operator network, N is generally 4.

[0047] At the TDD-CU end, the sampled time slot length signal and the time division duplex frame header signal are encapsulated into a data frame and transmitted to the TDD-RU end via optical fiber.

[0048] In the above-mentioned signal synchronization system, the remote module includes a phase-locked loop, a second field programmable gate array and a second optical module. The second optical module is used to receive the data frame sent by the first optical module. The phase-locked loop synchronizes the clock in the remote module to the reference clock in the data frame. The second field programmable gate array is used to parse the data frame to obtain the alignment information of the time division duplex switch signal, and adjust the time division duplex switch signal according to the alignment information and then output it.

[0049] In the above signal synchronization system, the second field programmable gate array is also used to separate the time division duplex frame header signal and the time slot length signal from the data frame, and determine the time division duplex switch signal according to the time division duplex frame header signal and the time slot length signal.

[0050] In the embodiment of the present application, the TDD-RU module is composed of a phase-locked loop (PLL), an FPGA (i.e., the second field programmable gate array), and an optical module (i.e., the second optical module). The FPGA receives the data frame from the TDD-CU through the second optical module, first recovers the reference clock in the data frame and outputs it to the PLL for re-locking, and then uses the clock output by the PLL re-locking as the system reference clock of the FPGA to achieve synchronization with the TDD-CU module clock. The process of recovering the reference clock is as follows: Figure 3a The optical module, SERDES, GTX, and clock recovery included in the TDD-RU in the FPGA are used to recover the reference clock; then the FPGA re-data frame separates the control command from the TDD frame header signal and the time slot length signal, and recovers the TDD frame header signal and the time slot length signal to the TDD switch signal, and then parses the control command to obtain the TDD switch alignment information. The DU switch adjusts the TDD switch signal according to the alignment information and reorganizes it for output. It should be noted that the above process of separating the control command from the TDD frame header signal and the time slot length signal is as follows: Figure 3a The optical module, SERDES, GTX, data de-framing, and command parsing included in the TDD-RU can separate the control command from the TDD frame header signal and the time slot length signal. Figure 3a After the optical module, SERDES, GTX, data deframing and command parsing included in the TDD-RU are processed, the TDD frame header signal and time slot length signal are obtained. This process is symmetrical with the framing process of the CU module.

[0051] In the above-mentioned signal synchronization system, the time division duplex switch signal is composed of multiple subframes, each subframe is composed of multiple symbols, the first symbol of the first subframe of the multiple subframes is used to transmit the frame header signal of the data frame, the first symbol of other subframes of the multiple subframes is used to transmit the time slot length signal, the second symbol of each subframe is used to transmit the time division duplex frame header signal, the third symbol of each subframe is used to transmit the control command, and the fourth symbol of each subframe is used to transmit the data of the remote module, wherein the other subframes are subframes other than the first subframe in the multiple subframes.

[0052] In the above signal synchronization system, different remote modules occupy frames with different symbols, and the frame numbers occupied by the remote modules are allocated by the control module.

[0053] In an embodiment of the present application, the data frame structure of the time division duplex switch signal (i.e., TDD switch signal) is as follows: a data frame is a symbol every 0.1us, and each symbol transmits 16 bits of data; every 10 symbols constitute a subframe (1us), every 128 subframes constitute a frame (128us), and every 128 frames constitute a superframe (16.384ms). The first symbol of the first subframe of each frame is fixed to transmit the data frame header, and the first symbols of other subframes transmit the time slot length information or the time slot length signal in turn; the second symbol of each subframe is fixed to transmit the TDD frame header information; the third symbol of each subframe is fixed to transmit the control command transmitted by the TDD-CU end, and the control signaling transmitted by different subframes is different; the fourth symbol of each subframe is used to transmit data on the TDD-RU end, and different TDD-RUs occupy symbols of different frames. The frame number occupied by the TDD-RU end is allocated by the TDD-CU end.

[0054] In the above signal synchronization system, the remote module determines the transmission delay between the remote module and the control module within the occupied frame sequence number; and determines the time to output the time division duplex switch signal based on the transmission delay.

[0055] In an embodiment of the present application, the TDD-CU assigns different frame numbers to different TDD-RUs according to the different access orders of the TDD-RU end. The RU access order refers to the order in which each RU is connected to the CU for the first time through the optical fiber. Because each RU is installed in a different position, there is a time difference when it is first connected to the CU, so there is a sequence; the TDD-RU measures the transmission delay Δt from the TDD-RU to the TDD-CU end in the frame number assigned to it; the TDD-RU outputs the TDD switch signal obtained by parsing the data frame to other modules in advance after Δt, and the other modules, for example Figure 3b Toggle the TDD switch in .

[0056] Figure 3ais a partial architecture diagram of a signal synchronization system according to an embodiment of the present application, such as Figure 3a As shown, the corresponding functions in the above control module and the remote module can be realized, so that the TDD uplink and downlink switch signals are synchronously output at the TDD-RU end, and the TDD uplink and downlink switch signals are also TDD switch signals.

[0057] Figure 3b This is a complete architecture diagram of a signal synchronization system according to an embodiment of the present application, which can also be understood as an architecture diagram of a 5G minimalist distributed coverage system based on FTTH passive optical network. Figure 3b As shown in the figure, the system consists of a CU unit, a passive optical network, and a DU unit. The CU unit consists of a 5G synchronization unit, a TDD switch, an LNA, an ATT, an RF optical modulator, an RF optical demodulator, and a wavelength division multiplexer. The CU unit supports 5G MIMO signal input, modulates the 5G MIMO downlink signal and the 5G synchronization switch signal into optical signals of different bands, outputs them to the ftth passive optical division network, and then transmits them to the DU unit; the CU unit also receives optical signals from the passive optical network, demodulates the optical signals of different bands and outputs them as MIMO uplink signals, and finally outputs them from the MIMO port.

[0058] The DU unit is composed of a TDD switch, LNA, ATT, PA, RF optical modulator, RF optical demodulator, and wavelength division multiplexer. The DU unit receives optical signals from the passive optical network, demodulates optical signals of different bands and outputs them as MIMO downlink signal output and TDD switch signals. The MIMO downlink signal is output from the MIMO port after passing through the ATT and PA modules and the TDD switch; at the same time, the uplink signal transmitted by the mobile terminal is received through the MIMO port, and the uplink modulation is converted into optical signals of different bands and output to the ftth passive optical division network, and then transmitted to the DU unit.

[0059] Figure 3a The modules correspond to Figure 3b The content of the dotted box in Figure 3a The TDD-RU end in the Figure 1 DU unit in the , and increase the TDD-CU end to Figure 1 The CU unit in the ORAS can reduce the signal interference of the entire signal synchronization system (i.e., the passive optical distribution system). It should be noted that the TDD synchronization control module (TDD-CU) module and the TDD synchronization remote module (TDD-RU) module can be used as part of the ORAS CU and DU equipment or as an independent module.

[0060] The embodiment of the present application can achieve high-precision synchronous output (with an error of less than 1us) of TDD uplink and downlink switch signals at different DU ends based on the ftth passive optical network 5G distributed coverage system, thereby avoiding uplink and downlink signal interference at the DU end caused by different paths of the passive optical transmission network and optimizing the ORAS uplink noise floor.

[0061] In the above-mentioned operating environment, an embodiment of the present application provides an embodiment of a signal synchronization method. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0062] Figure 4 is a flow chart of a signal synchronization method according to an embodiment of the present application, such as Figure 4 As shown, the method comprises the following steps:

[0063] Step S402, receiving a data frame sent by the control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected;

[0064] Step S404, after synchronizing the clock in the remote end to the reference clock in the data frame, parse the data frame to obtain the alignment information of the time division duplex switch signal;

[0065] Step S406: outputting a time division duplex switch signal according to the alignment information.

[0066] It should be noted that Figure 4 The signal synchronization method in can be applied to Figure 2 The signal synchronization system shown in the figure, therefore the relevant explanations in the above signal synchronization system are also applicable to the signal synchronization method, which will not be repeated here.

[0067] Figure 5 is a structural diagram of a signal synchronization device according to an embodiment of the present application, such as Figure 5 As shown, the device comprises:

[0068] The receiving unit 502 is used to receive a data frame sent by the control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected;

[0069] A parsing unit 504, configured to parse the data frame after synchronizing the clock in the remote end to the reference clock in the data frame to obtain the alignment information of the time division duplex switch signal;

[0070] The output unit 506 is configured to output a time division duplex switch signal according to the alignment information.

[0071] It should be noted that Figure 5 The signal synchronization device shown is used to perform Figure 4 The signal synchronization method shown, and Figure 2 The relevant explanations in the signal synchronization system shown are also applicable to the signal synchronization device and will not be repeated here.

[0072] Figure 6 FIG. 1 shows a hardware structure block diagram of a computer terminal (or electronic device) for implementing a signal synchronization method. Figure 6 As shown, the computer terminal 60 (or electronic device 60) may include one or more (602a, 602b, ..., 602n are used to illustrate) processors (the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 604 for storing data, and a transmission module 606 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 6 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 6 More or fewer components as shown, or with Figure 6 Different configurations are shown.

[0073] It should be noted that the one or more processors and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 60 (or electronic device). As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0074] The memory 604 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the signal synchronization method in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 604, that is, realizing the above-mentioned signal synchronization method. The memory 604 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 604 may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer terminal 60 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0075] The transmission module 606 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 60. In one example, the transmission device 606 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 606 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0076] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 60 (or electronic device).

[0077] It should be noted that, in some optional embodiments, the above Figure 6 The computer device (or electronic device) shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of hardware elements and software elements. It should be noted that Figure 6 This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the above-described computer device (or electronic device).

[0078] It should be noted that Figure 6 The processor in the electronic device shown is used to execute the following signal synchronization method: receiving a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; after synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain alignment information of the time division duplex switch signal; and outputting the time division duplex switch signal based on the alignment information.

[0079] An embodiment of the present application also provides a non-volatile storage medium, which includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the following signal synchronization method by running the computer program: receiving a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; after synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain alignment information of the time division duplex switch signal; and outputting the time division duplex switch signal based on the alignment information.

[0080] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0081] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0083] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0084] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0085] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0086] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A signal synchronization system, characterized in that: include: control module and remote module, wherein, The control module is used to collect the time division duplex switch signal and transmit the data frame containing the time division duplex switch signal and the reference clock to the remote module, wherein the reference clock is the clock corresponding to the time division duplex switch signal when it is collected; The remote module is used to parse the data frame after synchronizing the clock in the remote module to the reference clock in the data frame, obtain the alignment information of the time division duplex switch signal, and output the time division duplex switch signal according to the alignment information; The control module includes a crystal oscillator, a first field programmable gate array and a first optical module, the crystal oscillator is used to provide the reference clock, the first field programmable gate array is used to collect the time division duplex switch signal according to the reference clock, and the first optical module is used to convert the data frame into an optical signal and transmit it to the remote module, wherein the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal.

2. The system according to claim 1, characterized in that The first field programmable gate array is further used to send a data packet consisting of the time division duplex frame header signal, the time slot length signal and a control command to the first optical module, wherein the control command stores alignment information of the time division duplex switch signal.

3. The system according to claim 1, characterized in that The first field programmable gate array is also used to determine a frame starting point, wherein the frame starting point is a transition point between the longest uplink time slot within a preset acquisition time length and the downlink time slot; based on the frame starting point, the length of each uplink time slot and the length of each downlink time slot after the frame starting point within the preset acquisition time length are determined; the time slot length signal is determined based on the uplink time slot length and the downlink time slot length; and the data frame is determined based on the time slot length signal and the time division duplex frame header signal.

4. The system according to claim 1, characterized in that The remote module includes a phase-locked loop, a second field programmable gate array and a second optical module. The second optical module is used to receive the data frame sent by the first optical module. The phase-locked loop synchronizes the clock in the remote module to the reference clock in the data frame. The second field programmable gate array is used to parse the data frame to obtain the alignment information of the time division duplex switch signal, and adjust the time division duplex switch signal according to the alignment information and then output it.

5. The system according to claim 4, characterized in that The second field programmable gate array is also used to separate the time division duplex frame header signal and the time slot length signal from the data frame, and determine the time division duplex switch signal according to the time division duplex frame header signal and the time slot length signal.

6. The system according to claim 1, characterized in that The time division duplex switch signal is composed of multiple subframes, each subframe is composed of multiple symbols, the first symbol of the first subframe of the multiple subframes is used to transmit the frame header signal of the data frame, the first symbol of the other subframes of the multiple subframes is used to transmit the time slot length signal, the second symbol of each subframe is used to transmit the time division duplex frame header signal, the third symbol of each subframe is used to transmit the control command, and the fourth symbol of each subframe is used to transmit the data of the remote module, wherein the other subframes are subframes of the multiple subframes except the first subframe.

7. The system according to claim 6, characterized in that The symbols of the frames occupied by different remote modules are different, and the frame sequence numbers occupied by the remote modules are allocated by the control module.

8. The system according to claim 7, characterized in that The remote module determines the transmission delay between the remote module and the control module within the occupied frame sequence number; and determines the time to output the time division duplex switch signal according to the transmission delay.

9. A signal synchronization method, characterized in that: include: Receiving a data frame sent by the control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; After synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain the alignment information of the time division duplex switch signal; outputting the time division duplex switch signal according to the alignment information; The control end includes a crystal oscillator, a first field programmable gate array and a first optical module, the crystal oscillator is used to provide the reference clock, the first field programmable gate array is used to collect the time division duplex switch signal according to the reference clock, and the first optical module is used to convert the data frame into an optical signal and transmit it to the remote end, wherein the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal.

10. A signal synchronization device, characterized in that: include: A receiving unit, configured to receive a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, the reference clock being a clock corresponding to when the time division duplex switch signal is collected, the control end includes a crystal oscillator, a first field programmable gate array and a first optical module, the crystal oscillator is used to provide the reference clock, the first field programmable gate array is used to collect the time division duplex switch signal according to the reference clock, the first optical module is used to convert the data frame into an optical signal and transmit it to a remote end, the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal; A parsing unit, configured to parse the data frame after synchronizing the clock in the remote end to the reference clock in the data frame to obtain the alignment information of the time division duplex switch signal; An output unit is used to output the time division duplex switch signal according to the alignment information.

11. An electronic device, characterized in that: include: A memory for storing program instructions; A processor, connected to the memory, is used to execute program instructions to implement the following functions: receiving a data frame sent by a control end, wherein the data frame includes a time division duplex switch signal and a reference clock, and the reference clock is a clock corresponding to when the time division duplex switch signal is collected; after synchronizing the clock in the remote end to the reference clock in the data frame, parsing the data frame to obtain alignment information of the time division duplex switch signal; The time division duplex switch signal is output according to the alignment information, the control end includes a crystal oscillator, a first field programmable gate array and a first optical module, the crystal oscillator is used to provide the reference clock, the first field programmable gate array is used to collect the time division duplex switch signal according to the reference clock, the first optical module is used to convert the data frame into an optical signal and transmit it to the remote end, and the time division duplex switch signal includes a time division duplex frame header signal and a time slot length signal.

12. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the signal synchronization method described in claim 9 by running the computer program.

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