A slave device that implements SSI communication using a single SPI and IO interrupt

Abstract

The present invention relates to a slave device that implements SSI communication using a single SPI and IO interrupt. The device comprises a serial peripheral interface (SPI) and an IO interrupt interface. The SPI includes a signal input pin (SPI MOSI), a signal output pin (SPI MISO), and a clock signal input pin (SPI Clock). The IO interrupt interface is provided with an IO interrupt pin (IO EXIT) for receiving a frame synchronization signal. By combining the SPI and the IO interrupt interface, an external interface identical to that of an SSI slave is provided, achieving the same communication effect as the SSI protocol. Compared with the prior art, the present invention has the advantages of eliminating the need for additional pins and saving hardware resources.

Description

Technical Field

[0001] The present invention relates to a slave device, in particular to a slave device that realizes SSI communication through single SPI and IO interruption. Background Art

[0002] SSI (Synchronous Serial Interface) is a full-duplex serial interface characterized by a fast communication rate, usually up to 2Mbps and above. Figure 1 As shown, the SSI protocol timing diagram is as follows Figure 2 shown.

[0003] SPI (Serial Peripheral Interface) is also a full-duplex synchronous communication bus interface. The SPI slave diagram is as follows: Figure 3 As shown, the SPI protocol timing diagram is as follows Figure 4 shown.

[0004] Chips supporting the SSI protocol are relatively rare, such as Atmel's SAM4S series, and are also relatively expensive. Chip selection is limited, and availability and use are often restricted, making porting and platform migration difficult. Therefore, finding a low-cost alternative to SSI slave devices has become a pressing technical challenge. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a slave device that realizes SSI communication through single SPI and IO interrupt.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] According to one aspect of the present invention, a slave device that implements SSI communication via a single SPI and IO interrupt is provided, comprising a serial peripheral interface SPI and an IO interrupt interface, wherein the serial peripheral interface SPI comprises a signal input pin SPI MOSI, a signal output pin SPI MISO, and a clock signal input pin SPI Clock, and the IO interrupt interface is provided with an IO interrupt pin IO EXIT for receiving a frame synchronization signal;

[0008] By combining a serial peripheral interface SPI and an IO interrupt interface, it provides an external interface identical to that of an SSI slave and achieves the same communication effect as the SSI protocol.

[0009] As a preferred technical solution, the clock signal input pin SPI Clock is connected to the external SSI protocol clock signal output end, and is used to receive the SSI protocol clock signal sent externally.

[0010] As a preferred technical solution, the signal input pin SPI MOSI is connected to an external SSI protocol data output terminal for receiving SSI protocol data sent externally.

[0011] As a preferred technical solution, the signal output pin SPI MISO is connected to an external SSI protocol data input terminal for sending SSI protocol data to the outside.

[0012] As a preferred technical solution, the IO interrupt pin IO EXIT is connected to an external SSI protocol frame synchronization signal output terminal, and is used to receive an externally sent SSI protocol frame synchronization signal.

[0013] As a preferred technical solution, the IO interrupt pin IO EXIT is a pin that can capture the falling edge of the frame synchronization signal, and the transmission and stop of the SPI are enabled by capturing the falling edge of the frame synchronization signal.

[0014] As a preferred technical solution, the serial peripheral interface SPI is a serial peripheral interface using a DMA transmission mode.

[0015] As a preferred technical solution, the DMA transmission mode adopts a single mode or a cyclic mode.

[0016] As a preferred technical solution, the serial peripheral interface SPI is a serial peripheral interface that adopts an interrupt or blocking transmission mode.

[0017] As a preferred technical solution, the serial peripheral interface SPI is a serial peripheral interface with a customizable transmission data length.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] 1) Compared with using a dedicated SSI chip, the present invention only uses three SPI hardware pins and one IO interrupt pin to achieve the same effect as SSI communication, without occupying additional pins, thus saving hardware resources.

[0020] 2) The transmission data length of the slave device of the present invention can be customized, and can be processed regardless of the length of the data sent by the host.

[0021] 3) The SPI protocol is similar to the SSI protocol in part, but cannot be directly replaced. However, after the improvement of the solution of the present invention, communication can be carried out by replacing the SSI protocol with SPI.

[0022] 4) The SPI of the present invention can adopt DMA transmission mode, which can not only reduce the cost of chip CPU resources, but also realize continuous clock output.

[0023] 5) The SPI of the present invention is not limited to the DMA transmission mode, and can also adopt an interrupt or blocking transmission mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of an existing SSI slave;

[0025] Figure 2 This is the SSI protocol signal timing diagram;

[0026] Figure 3 This is a schematic diagram of an existing SPI slave;

[0027] Figure 4 This is the SPI protocol signal timing diagram;

[0028] Figure 5 is a schematic diagram of a slave device of the present invention;

[0029] Figure 6 This is a specific circuit diagram of the slave device of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0031] like Figure 5 and Figure 6 As shown, the present invention discloses a slave device that implements SSI communication using a single SPI and IO interrupt. The device includes a serial peripheral interface (SPI) and an IO interrupt interface. The SPI includes a signal input pin (SPIMOSI), a signal output pin (SPIMISO), and a clock signal input pin (SPIClock). The IO interrupt interface is provided with an IO interrupt pin (IOEXIT) for receiving a frame synchronization signal. The present invention combines an SPI with an IO interrupt, providing a frame synchronization function via the IO interrupt and data transmission via the SPI, thereby replacing the SSI slave communication mode with the SPI. Specifically, by combining a serial peripheral interface (SPI) and an IO interrupt interface, an external interface identical to that of an SSI slave is provided, achieving the same communication effect as the SSI protocol.

[0032] The clock signal input pin SPI Clock is connected to the external SSI protocol clock signal output end, and is used to receive the SSI protocol clock signal sent externally.

[0033] The signal input pin SPI MOSI is connected to an external SSI protocol data output terminal for receiving SSI protocol data transmitted externally. The signal output pin SPI MISO is connected to an external SSI protocol data input terminal for transmitting SSI protocol data externally. Specifically, the SSI protocol data input and output signals are connected to SPI MOSI and SPI MISO. Data communication is performed via SPI.

[0034] The IO interrupt pin IO EXIT is connected to the external SSI protocol frame synchronization signal output terminal and is used to receive the SSI protocol frame synchronization signal sent externally. The IO interrupt pin IO EXIT is a pin that can capture the falling edge of the frame synchronization signal. By capturing the falling edge of the frame synchronization signal, SPI transmission and stopping are enabled.

[0035] The SPI uses DMA transfer mode, which not only reduces CPU resource usage but also enables continuous clock output. DMA can operate in either single-shot (Normal) or circular (Circular) modes. In single-shot mode, the DMA is re-enabled after each interrupt, while in circular mode, re-enabling is not required.

[0036] In addition, the present application also provides another mode, wherein the serial peripheral interface SPI is a serial peripheral interface that adopts an interrupt or blocking transmission mode.

[0037] The present invention can customize the length of the slave's transmission data, and can process data of any length from the master. Compared to using a dedicated SSI chip, the present invention only uses three SPI hardware pins and one IO interrupt pin to achieve the same effect as SSI communication, eliminating the need for additional pins and saving hardware resources.

[0038] The present invention can use common chips that support SPI communication, such as ST (STMicroelectronics), GD (GigaDevice), SH (SinoWise Electronics), and 51 single-chip microcomputers. It is not limited to the chip having to support the SSI communication protocol, which greatly reduces the development cost and transplantation cost, greatly increases the selectivity, and is cheaper.

[0039] There is currently a severe shortage of chips in the international market. Choosing domestic chips makes them easier to obtain and can greatly reduce costs.

[0040] like Figure 6As shown, the slave device further includes an MCU connected to the serial peripheral interface SPI and the IO interrupt interface respectively, and the MCU is also connected to a power supply circuit and a crystal oscillator circuit, etc.

[0041] Explanation of special terms:

[0042] SSI (Synchronous Serial Interface);

[0043] SPI (Serial Peripheral Interface);

[0044] DMA (Direct Memory Access);

[0045] CS (Chip Select from device);

[0046] MISO (slave device data output);

[0047] MOSI (slave data input);

[0048] NSS (Negative Slave Select);

[0049] Frame Sync (frame synchronization signal);

[0050] EXIT (external interrupt pin);

[0051] IO (Input / Output pin).

[0052] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A slave device that implements SSI communication via a single SPI and IO interrupt, characterized in that: It includes a serial peripheral interface SPI and an IO interrupt interface, wherein the serial peripheral interface SPI includes a signal input pin SPIMOSI, a signal output pin SPIMISO and a clock signal input pin SPIClock, and the IO interrupt interface is provided with an IO interrupt pin IO EXIT for receiving a frame synchronization signal; By combining a serial peripheral interface SPI and an IO interrupt interface, it provides the same external interface as the SSI slave and achieves the same communication effect as the SSI protocol; The IO interrupt pin IO EXIT is connected to the external SSI protocol frame synchronization signal output end and is used to receive the SSI protocol frame synchronization signal sent externally; the IO interrupt pin IO EXIT is a pin that can capture the falling edge of the frame synchronization signal, and by capturing the falling edge of the frame synchronization signal, the SPI transmission and stop are enabled; the serial peripheral interface SPI is a serial peripheral interface that adopts the DMA transmission mode; the serial peripheral interface SPI is a serial peripheral interface that adopts the interrupt or blocking transmission mode.

2. A slave device that implements SSI communication using a single SPI and IO interrupt according to claim 1, characterized in that: The clock signal input pin SPI Clock is connected to the external SSI protocol clock signal output end, and is used to receive the SSI protocol clock signal sent externally.

3. A slave device for implementing SSI communication using a single SPI and IO interrupt according to claim 1, characterized in that: The signal input pin SPI MOSI is connected to an external SSI protocol data output terminal and is used to receive SSI protocol data sent externally.

4. The slave device for implementing SSI communication using a single SPI and IO interrupt according to claim 1, wherein: The signal output pin SPI MISO is connected to the data input terminal of the external SSI protocol and is used to send SSI protocol data to the outside.

5. The slave device for implementing SSI communication via single SPI and IO interrupt according to claim 1, characterized in that: The DMA transmission mode adopts a single mode or a cyclic mode.

6. A slave device that realizes SSI communication through single SPI and IO interruption according to claim 1, characterized in that: The serial peripheral interface SPI is a serial peripheral interface whose transmission data length can be customized.

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