A non-resident data cross-clock domain method based on co-frequency and out-of-phase clocks

Abstract

The present invention discloses a method for non-resident data crossing clock domain based on co-frequency and out-of-phase clocks. The method mainly includes the processing of data crossing clock domain under co-frequency and out-of-phase clocks and the performance test of the data transmission system after the processing: the master station design of the data transmission system is based on the UDP protocol, and the slave station design is based on the EtherCAT protocol; the IP core FIFO method and the asynchronous dual-port RAM method are called to process the cross-clock domain part of the resident data involved in the master station; the cross-clock domain transmission of non-resident data of the slave station is processed by using a two-frequency enable latching method. The method adopts a two-frequency enable latching algorithm to solve the problem of data crossing clock domains. The proposed method can enable data to be correctly transmitted under co-frequency and out-of-phase clocks, reduce the packet loss rate of the data transmission system, and improve the certainty and reliability of network transmission.

Description

Technical Field

[0001] The invention belongs to the field of industrial field bus, and in particular relates to a non-resident data cross-clock domain method based on same-frequency and different-phase clocks in field bus communication. Background Art

[0002] As the complexity of industrial field environment deepens, the number of connected equipment control instruments increases significantly, and the real-time requirements of data transmission are also increasing. In order to design a fieldbus transmission system with high bandwidth, low latency and determinism, the EtherCAT Ethernet transmission technology with a very short real-time response time, which can reach the ns level, is adopted. In the system of data transmission between the master station based on the UDP protocol and the slave station based on the EtherCAT protocol, data transmission across clock domains between the master station and the slave station, and between the slave stations, will be involved, which brings about the problem of data crossing clock domains. The main reason for the problem of data crossing clock domains is that when data is transmitted under two different clocks, although the clock signals have the same frequency, the phase relationship between them is uncertain, which will cause the data to be very likely to not meet the setup and hold time, thereby generating metastable phenomena. These erroneous data states will be transmitted to the downstream system, seriously causing the entire system to paralyze. In order to design a high-performance transmission system with the above high bandwidth, low latency and determinism, the problem of data crossing clock domains must be solved first to ensure the deterministic requirements of data transmission.

[0003] Traditional data cross-clock domain methods mainly include asynchronous FIFO, handshake mechanism method, tight coupling method, etc. The asynchronous FIFO method is the most commonly used data cross-domain processing method, but its logic generation of empty and full signals is complex, and some signals are difficult to control accurately. For the handshake mechanism method, although it can make the data transmitted correctly, the transmission delay is very high, which is not suitable for the transmission of high-speed data systems. The tight coupling method can make the data transmitted stably under the asynchronous clock, but it uses at least 3 storage units, and the resource utilization is low. Therefore, a data cross-clock domain method with high resource utilization and stability is needed. Summary of the invention

[0004] The purpose of the present invention is to solve the problem of data crossing clock domains in a data transmission system between a master station based on UDP protocol and a slave station based on EtherCAT protocol. A non-resident data crossing clock domain method based on the same frequency and different phase clocks is proposed. The method is mainly to solve the problem of data crossing clock domains directly between slave stations. The method has high resource utilization and is stable and accurate.

[0005] In order to achieve the above objectives, the invention adopts the following technical solutions:

[0006] Step 1: Design a master station data transmission system based on UDP protocol and a slave station data transmission system based on EtherCAT protocol;

[0007] Step 2, calling the IP core FIFO method and the asynchronous dual-port RAM method to process the cross-clock domain part of the resident data involved in the master station;

[0008] Step three, use the newly proposed two-division frequency enabling latching method to process the cross-clock domain transmission of the slave station's non-resident data, and the cross-clock domain part of the data involved in the slave station.

[0009] In the specific implementation, the following steps are also performed for test evaluation:

[0010] Step 4: Write the test software and set the number of tests;

[0011] Step 5, calculating the number of times data frames are sent and received;

[0012] Step 6: Finally, the data packet loss rate is calculated to evaluate the performance of the entire data system.

[0013] The asynchronous transmission of data described in the present invention refers to the cross-clock transmission of data.

[0014] In the master-slave station data transmission system, the transmission between the master station and the slave station and between the slave stations adopts the EtherCAT protocol, and the transmission between the external computer and the master station adopts the UDP protocol.

[0015] The master station includes an Ethernet message receiving buffer module rcv_buffer, an ARP message receiving module arp_rcv, an IP message receiving module ip_rcv, a buffer connection module nwk_tx_abt, a UDP message receiving module udp_rcv, a UDP message sending module udp_send, an ARP message sending module arp_send, an IP message sending module ip_send, an ARP cache module Mac_cache, an icmp reply message module icmp_reply and an Ethernet message sending module mac_tx_abt;

[0016] The output end of the Ethernet receiving message buffer module rcv_buffer is respectively connected to the input end of the ARP message receiving module arp_rcv and the IP message receiving module ip_rcv, the output end of the IP message receiving module ip_rcv is respectively connected to the input end of the UDP message receiving module udp_rcv and the icmp reply message module icmp_reply, the output end of the icmp reply message module icmp_reply and the output end of the UDP message sending module udp_send are respectively connected to the two input ends of the buffer connection module nwk_tx_abt;

[0017] The output end of the ARP message receiving module arp_rcv is respectively connected to the input end of the ARP cache module Mac_cache and an input end of the ARP message sending module arp_send. At the same time, an output end of the ARP cache module Mac_cache is connected to another input end of the ARP message sending module arp_send. The output ends of the ARP cache module Mac_cache and the buffer connection module nwk_tx_abt are respectively connected to the two input ends of the IP message sending module ip_send. The output ends of the IP message sending module ip_send and the ARP message sending module arp_send are respectively connected to the two input ends of the Ethernet message sending module mac_tx_abt.

[0018] In the step 2, for the data sent by the computer to the main station, an IP core is called in the Ethernet receiving message buffer module rcv_buffer of the main station to cache the data in the asynchronous FIFO storage module, and all the data are converted to the sending clock domain of the main station network port 0 and transmitted to the modules at all levels behind the Ethernet receiving message buffer module rcv_buffer until the data is transmitted to the UDP message receiving module udp_rcv;

[0019] At the same time, an asynchronous dual-port RAM storage module is written in the UDP message receiving module udp_rcv, and the data part of the UDP message (custom sub-message content) is cached in the asynchronous dual-port RAM storage module, completing the cross-clock domain processing of the data in the clock domain sent by the master station network port 0 to the data in the clock domain sent by the master station network port 1. After that, the data in the clock domain sent by the master station network port 1 is encapsulated with the EtherCAT protocol and finally sent from the UDP message receiving module udp_rcv to the slave station.

[0020] The master station has two Ethernet ports, which can be named port 0 and port 1. Each port has a sending clock domain and a receiving clock domain. The reception of data sent from other stations is completed in the receiving clock domain. If this station wants to send data to other stations, it needs to be completed in the sending clock domain. The master station port 0 is connected to the computer port, the master station port 1 is connected to the slave station port 0, the slave station port 1 is connected to the next slave station port 0, and so on.

[0021] In the step 3, a two-way frequency division enabling latching cross-clock domain method circuit is constructed in the transmission between slave stations, including a receiving domain rx domain, a sending domain tx domain, a storage unit RAM, three multiplexers, three D flip-flops, a shift register composed of two D flip-flops and three AND gates; the receiving domain rx domain and the sending domain tx domain are respectively connected to the storage unit RAM, the receiving domain rx domain is respectively connected to two multiplexers, three D flip-flops, and two AND gates, the above D flip-flops are respectively connected to the storage unit RAM, the shift register, and the third AND gate (AND gate connected to shift[0]), the shift register is respectively connected to the sending domain tx domain, the storage unit RAM, and the third AND gate (AND gate connected to shift[0]), the two multiplexers connected to the receiving domain rx domain are respectively connected to the two D flip-flops, the two D flip-flops are respectively connected to the two AND gates connected to the receiving domain rx domain, and the receiving domain rx domain is respectively connected to the receiving domain rx domain. The two AND gates connected to the domain are both connected to the storage unit RAM, and the remaining multiplexers are respectively connected to the storage unit RAM, the data reading end rdata of the storage unit RAM, and the third AND gate (the AND gate connected to shift[0]).

[0022] The described two-division frequency enabling latch cross-clock domain method circuit, the clock output terminal, the enable signal output terminal and the data output terminal of the receiving domain rx domain are respectively connected to the clock receiving terminal rx_clk, the write enable signal writing terminal wr_en and the data writing terminal wr_data of the storage unit RAM, and the clock sending terminal tx_clk and the data reading terminal rdata of the RAM are respectively connected to the clock input terminal and the data input terminal of the sending domain tx domain;

[0023] The clock output terminal of the receiving domain rx domain is respectively connected to the clock trigger terminals of the two D flip-flops, the enable signal output terminal of the receiving domain rxdomain is respectively connected to the selection control terminals of the first multiplexer and the second multiplexer and one input terminal of each of the first and second AND gates, and the enable signal output terminal of the receiving domain rx domain is connected to the input terminal D of the above D flip-flop;

[0024] The output terminals of the first multiplexer and the second multiplexer are connected to the input terminals D of the two D flip-flops, and the output terminals Q of the two D flip-flops are respectively connected to the other input terminals of the first AND gate and the second AND gate, and at the same time, the output terminals Q of the two D flip-flops are respectively connected to the input terminals 1 of the first multiplexer and the second multiplexer, and the high-level signal is connected as an input. This statement is incorrect and does not need to be explained. The signal of the input terminal 1 has been determined by the signal output by the output terminals Q of the two D flip-flops. The input terminal 0 of the first multiplexer is connected to input a low-level signal, and the input terminal 0 of the second multiplexer is connected to input a high-level signal.

[0025] The output terminal Q of the above D flip-flop is respectively connected to the enable signal reading terminal rd_en of the storage unit RAM and an input terminal of the third AND gate (the AND gate connected to shift[0]), the clock sending terminal of the storage unit RAM is respectively connected to the clock triggering terminal of the above D flip-flop and the clock triggering terminals of the two D flip-flops in the shift register, the output terminal of a D flip-flop in the shift register is connected to an input terminal of the third AND gate (the AND gate connected to shift[0]), and the output terminal of the third AND gate (the AND gate connected to shift[0]) is connected to the selection control terminal of the third multiplexer;

[0026] The storage unit RAM is internally divided into a first storage unit RAM[1] and a second storage unit RAM[0], the output ends of the first AND gate and the second AND gate are respectively connected to the write ends of the first storage unit RAM[1] and the second storage unit RAM[0], the read ends of the first storage unit RAM[1] and the second storage unit RAM[0] are respectively connected to the 1-way input end and the 0-way input end of the third multiplexer, the output end of the third multiplexer is connected to the data read end rdata of the RAM and the data input end of the sending domain txdomain, and the data tx_data is sent.

[0027] In the shift register, the input terminal D of the first D flip-flop is connected to the output terminal Q of the second D flip-flop, and the input terminal D of the second D flip-flop is connected to the output terminal Q of the first D flip-flop.

[0028] When the receiving domain rx domain receives the data stream, the receiving enable signal rx_valid in the data stream is sent to the above D flip-flop, the first multiplexer and the second multiplexer respectively, the receiving clock rx_clk in the data stream is sent to the two D flip-flops respectively, and the receiving data rx_data in the data stream is sent to the first storage unit RAM[1] and the second storage unit RAM[0] for storage;

[0029] first,

[0030] If the receiving enable signal rx_valid is at a high level, the receiving enable signal rx_valid will act on the first multiplexer and the second multiplexer, so that when the receiving clock rx_clk received by the two D flip-flops is at a rising edge, the outputs of the first multiplexer and the second multiplexer are inverted and jump, and the output ends of the two D flip-flops output two latch enable signals latch_0 and latch_1 with the same frequency and opposite phases;

[0031] When the latch enable signal is obtained, the receiving enable signal rx_valid is directly connected to the write enable signal writing terminal wr_en of the storage unit RAM. The receiving enable signal rx_valid and the latch enable signals latch_0 and latch_1 are logically processed through the first and second AND gates respectively:

[0032] When the output of the first AND gate is at a high level and the output of the second AND gate is at a low level, the storage unit RAM selects to store the received data rx_data in the first storage unit RAM[1];

[0033] When the output of the first AND gate is at a low level and the output of the second AND gate is at a high level, the storage unit RAM selects to store the received data rx_data in the second storage unit RAM[0];

[0034] Secondly,

[0035] When the receiving enable signal rx_valid is valid, that is, at a high level, the receiving enable signal rx_valid is input to the upper D flip-flop, and the output signal of the output terminal Q of the upper D flip-flop is directly used as the enable read signal of the storage unit RAM;

[0036] Then,

[0037] The enable read signal rd_en is input into the two D flip-flops of the shift register.

[0038] In the initial state, the state of one flip-flop is 0, which represents the low level of the input, and the state of the other flip-flop is 1, which represents the high level of the input;

[0039] At the rising edge of each transmit clock tx clk, the outputs of the two D flip-flops interact to implement a shift operation; the entire shift register outputs the lower bit shift[0] of the total state of the two flip-flops to one input terminal of the third AND gate;

[0040] at last,

[0041] The read enable signal rd_en of the storage unit RAM and the lower bit shift[0] output by the shift register are ANDed through the third AND gate:

[0042] When the output of the third AND gate is at a high level, the data in the second storage unit RAM[0] is selected and read out through the third multiplexer;

[0043] When the output of the third AND gate is at a low level, the data in the first storage unit RAM[1] is selected and read out through the third multiplexer;

[0044] The data Data_out output by the third multiplexer is used as data synchronized across clock domains.

[0045] The frequencies of the two latch enable signals latch_0 and latch_1 are exactly half of the frequency of the receiving clock rx_clk.

[0046] The transmit clock tx clk and the receive clock rx_clk are both generated by a crystal oscillator.

[0047] The method of the present invention mainly includes the performance test of the data transmission system after the cross-clock domain processing and the processed data under the same frequency and different phase clocks. The specific steps are: building a master station based on the UDP protocol and a slave station data transmission system based on the EtherCAT protocol; analyzing the data cross-clock domain transmission part involved in the data transmission system and the data transmission characteristics of each part; according to the characteristics of the data transmission of each part, the cross-clock domain method of the asynchronous IP core FIFO and the asynchronous dual-port RAM method are called for the cross-clock domain transmission of resident data, and the newly proposed two-division frequency enabling latch method is used for the cross-clock domain part of the non-resident data between the slave stations; finally, the test software is written to test the performance of the entire data transmission system.

[0048] The beneficial effects of the present invention are:

[0049] The method of the present invention can improve the reliability of network data transmission and reduce the packet loss rate during data transmission.

[0050] This method adopts a two-frequency enable latch algorithm to solve the problem of data crossing clock domains. The proposed method can enable data to be correctly transmitted under the same frequency and different phase clocks, reduce the packet loss rate of the data transmission system, and improve the certainty of network transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1It is a flow chart of a non-resident data cross-clock method based on clocks with the same frequency and different phases;

[0053] Figure 2 This is the hardware platform architecture diagram of the experiment;

[0054] Figure 3 This is the main station function module diagram based on UDP protocol;

[0055] Figure 4 This is a circuit diagram of a two-frequency division enabling latch crossing clock domain method;

[0056] Figure 5 It is the signal timing diagram of the divide-by-two frequency enabling latch crossing clock domain method;

[0057] Figure 6 This is a performance comparison chart of the system test when the slave station uses three methods to perform data crossing the clock domain. DETAILED DESCRIPTION

[0058] The purpose of the present invention is to analyze whether the establishment and holding time of data during cross-clock domain transmission meets the requirements, and proposes a non-resident data cross-clock domain method based on the same frequency and different phase, which can correctly transmit data from one clock domain to another clock domain. After the data cross-clock domain processing, the packet loss rate of the entire data system is greatly reduced, the certainty of network transmission is improved, and the delay time of data transmission is reduced.

[0059] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

[0060] Figure 1 The present invention is a flowchart of a method for implementing a non-resident data cross-clock domain method based on the same frequency and different phase in one embodiment of the present invention. The method includes the following steps: first, a master station based on the UDP protocol and a slave station data transmission system based on the EtherCAT protocol are built; then the asynchronous IP core FIFO method and the asynchronous dual-port RAM method are called to process the cross-clock domain part of the resident data of the master station; then the two-division frequency enabling latch method is used to process the data cross-clock domain problem between the slave stations; the test software is written for the entire system, and the number of tests is set until the number of tests reaches the set value; the packet loss rate of the test results and some other network performance parameters are checked.

[0061] The present invention will be further described below in conjunction with specific examples. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0062] Example

[0063] In order to evaluate the performance of the proposed two-way frequency-division-enabled latching method, the UDP protocol master station and the EtherCAT protocol transmission slave station were first programmed in the Quartus II 13.0 software using the Verilog language. Figure 2 The hardware experimental platform shown in the figure realizes the communication of the entire master-slave data transmission system. The specific test software settings are as follows: the number of tests is 10,000.

[0064] Step 1: Build a master station based on UDP protocol and a slave station data transmission system based on EtherCAT protocol.

[0065] In this embodiment, the main station of the transmission system is first designed. The various modules of the main station design are as follows: Figure 3 As shown in the figure, the entire protocol stack can complete the ARP message transmission, ICMP message transmission and UDP message loopback experiment. The PC sends a UDP message to the master station, and the UDP data part is a custom sub-message.

[0066] The master station includes an Ethernet receiving message buffer module rcv_buffer, an ARP message receiving module arp_rcv, an IP message receiving module ip_rcv, a buffer connection module nwk_tx_abt, a UDP message receiving module udp_rcv, a UDP message sending module udp_send, an ARP message sending module arp_send, an IP message sending module ip_send, an ARP cache module Mac_cache, an icmp reply message module icmp_reply and an Ethernet sending message module mac_tx_abt;

[0067] The output end of the Ethernet receiving message buffer module rcv_buffer is respectively connected to the input end of the ARP message receiving module arp_rcv and the IP message receiving module ip_rcv, the output end of the IP message receiving module ip_rcv is respectively connected to the input end of the UDP message receiving module udp_rcv and the icmp reply message module icmp_reply, the output end of the icmp reply message module icmp_reply and the output end of the UDP message sending module udp_send are respectively connected to the two input ends of the buffer connection module nwk_tx_abt;

[0068] The output end of the ARP message receiving module arp_rcv is respectively connected to the input end of the ARP cache module Mac_cache and an input end of the ARP message sending module arp_send. At the same time, an output end of the ARP cache module Mac_cache is connected to another input end of the ARP message sending module arp_send. The output ends of the ARP cache module Mac_cache and the buffer connection module nwk_tx_abt are respectively connected to the two input ends of the IP message sending module ip_send. The output ends of the IP message sending module ip_send and the ARP message sending module arp_send are respectively connected to the two input ends of the Ethernet message sending module mac_tx_abt.

[0069] In this embodiment, the main station of the transmission system is first designed. The various modules of the main station design are as follows: Figure 3 As shown,

[0070] The entire protocol stack can complete the ARP message transmission, ICMP message transmission and UDP message loopback experiment. The PC sends a UDP message to the master station, and the UDP data part is a custom sub-message.

[0071] The Ethernet receiving message buffer module rcv_buffer receives the data packets transmitted from the Ethernet, namely the Ethernet message Mac_rx. The master station uses the Ethernet receiving message buffer module rcv_buffer to identify the frame type of the data packets transmitted from the Ethernet, and divides the data messages into two categories: IP message data_ip and ARP message data_arp. The UDP message is encapsulated in the IP message data part. The entire IP message will be identified by the IP message receiving module ip_rcv to obtain the UDP message and then transmitted to the UDP message receiving module udp_rcv. In the UDP message receiving module udp_rcv, the useful custom sub-message is encapsulated with the EtherCAT protocol and sent to the next slave station.

[0072] At the same time, the ARP message data_arp is sent to the ARP message receiving module arp_rcv for identification and is divided into the mac address wr_mac_ip and the reply enable signal reply_send_en. The mac address wr_mac_ip is cached in the ARP cache module Mac_cache. The mac address rd_mac cached in the ARP cache module Mac_cache is then sent to the IP message sending module ip_send. The reply enable signal reply_send_en is sent to the ARP message sending module arp_send.

[0073] The messages returned from the station are returned to the UDP message receiving module udp_rcv, and then these messages are transmitted to the UDP message sending module udp_send, and then transmitted to the IP message sending module ip_send through the buffer connection module nwk_tx_abt, which will encapsulate the IP message header and Ethernet message header for the entire message. Finally, the encapsulated Ethernet standard data packet arp_mac_tx_tdata is transmitted back to the computer through the Ethernet message sending module mac_tx_abt, realizing a data transmission process.

[0074] Figure 3 In the above, Rx represents the receiving end, Tx represents the sending end; icmp_data represents the icmp message data, and udp_rcv_data represents the upd message receiving data.

[0075] Step 2: Call the IP core FIFO method and the asynchronous dual-port RAM method to process the data crossing clock domain part involved in the master station;

[0076] In step 2, for the data sent by the computer to the master station, an IP core is called in the Ethernet receiving message buffer module rcv_buffer of the master station to cache the data in the asynchronous FIFO storage module, and all the data are converted to the sending clock domain of the master station network port 0 and transmitted to the modules at all levels behind the Ethernet receiving message buffer module rcv_buffer until the data is transmitted to the UDP message receiving module udp_rcv;

[0077] At the same time, an asynchronous dual-port RAM storage module is written in the UDP message receiving module udp_rcv, and the data part of the UDP message is cached in the asynchronous dual-port RAM storage module, completing the cross-clock domain processing of the data in the clock domain sent by the master station network port 0 to the data in the clock domain sent by the master station network port 1. After that, the data in the clock domain sent by the master station network port 1 is encapsulated with the EtherCAT protocol and finally sent from the UDP message receiving module udp_rcv to the slave station.

[0078] For the data returned by the slave station, the programmed asynchronous dual-port RAM storage module is still used to process the data across clock domains, completing the entire master station data across clock domains processing.

[0079] Step 3, using the newly proposed two-division frequency enabling latching method to process the non-resident data transmission across clock domains of the slave station;

[0080] The proposed new method is for clocks with the same frequency and different phases, and the data transmission method is non-resident. The proposed method chooses to use RAM as the data storage unit, and uses the idea of ​​a two-frequency enable signal to access data. At the same time, in order to reduce the use of complex counter logic, a shift register is used to read data. The structure of the new method of crossing clock domains with the same frequency and different phases and non-resident data is as follows: Figure 4 shown.

[0081] The proposed new method is for clocks with the same frequency but different phases and the data transmission mode is non-resident. A binary frequency division enabling latch cross-clock domain method circuit is constructed in the transmission between slave stations, including a receiving domain rx domain, a sending domain tx domain, a storage unit RAM, three multiplexers, three D flip-flops, a shift register composed of two D flip-flops, and three AND gates; the receiving domain rx domain and the sending domain tx domain are respectively connected to the storage unit RAM, the receiving domain rx domain is respectively connected to two multiplexers, three D flip-flops, and two AND gates, the above D flip-flops are respectively connected to the storage unit RAM, the shift register, and the third AND gate (AND gate connected to shift[0]), the shift register is respectively connected to the sending domain tx domain, the storage unit RAM, and the third AND gate (AND gate connected to shift[0]), the two multiplexers connected to the receiving domain rx domain are respectively connected to the two D flip-flops, the two D flip-flops are respectively connected to the two AND gates connected to the receiving domain rx domain, the two AND gates connected to the receiving domain rx domain are both connected to the storage unit RAM, and the remaining multiplexers are respectively connected to the storage unit RAM, the data reading end rdata of the storage unit RAM, and the third AND gate (AND gate connected to shift[0]).

[0082] In the circuit of the two-division frequency enable latch cross-clock domain method, the clock output terminal, the enable signal output terminal and the data output terminal of the receiving domain rx domain are respectively connected to the clock receiving terminal rx_clk, the enable signal writing terminal wr_en and the data writing terminal wr_data of the storage unit RAM, and the clock sending terminal tx_clk and the data reading terminal rdata of the RAM are respectively connected to the clock input terminal and the data input terminal of the sending domain txdomain;

[0083] The clock output terminal of the receiving domain rx domain is respectively connected to the clock trigger terminals of the two D flip-flops, the enable signal output terminal of the receiving domain rxdomain is respectively connected to the selection control terminals of the first multiplexer and the second multiplexer and one input terminal of each of the first and second AND gates, and the enable signal output terminal of the receiving domain rx domain is connected to the input terminal D of the above D flip-flop;

[0084] The output terminals of the first multiplexer and the second multiplexer are connected to the input terminals D of the two D flip-flops, and the output terminals Q of the two D flip-flops are respectively connected to the other input terminals of the first AND gate and the second AND gate, and at the same time, the output terminals Q of the two D flip-flops are respectively connected to the input terminals 1 of the first multiplexer and the second multiplexer, and the high-level signal is connected as an input. This statement is incorrect and does not need to be explained. The signal of the input terminal 1 has been determined by the signal output by the output terminals Q of the two D flip-flops. The input terminal 0 of the first multiplexer is connected to input a low-level signal, and the input terminal 0 of the second multiplexer is connected to input a high-level signal.

[0085] The output terminal Q of the above D flip-flop is respectively connected to the enable signal reading terminal rd_en of the storage unit RAM and an input terminal of the third AND gate, the clock sending terminal of the storage unit RAM is respectively connected to the clock triggering terminal of the above D flip-flop and the clock triggering terminals of the two D flip-flops in the shift register, the output terminal of a D flip-flop in the shift register is connected to an input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the selection control terminal of the third multiplexer;

[0086] The storage unit RAM is internally divided into a first storage unit RAM[1] and a second storage unit RAM[0]. The output ends of the first AND gate and the second AND gate are respectively connected to the write ends of the first storage unit RAM[1] and the second storage unit RAM[0]. The read ends of the first storage unit RAM[1] and the second storage unit RAM[0] are respectively connected to the 1-way input end and the 0-way input end of the third multiplexer. The output end of the third multiplexer is connected to the data read end rdata of the RAM and the data input end of the transmission domain tx domain, and the data tx_data is transmitted.

[0087] Figure 4 In the example, RAM[1] represents the first storage unit in the storage unit RAM, and RAM[0] represents the second storage unit in the storage unit RAM.

[0088] In the shift register, the input terminal D of the first D flip-flop is connected to the output terminal Q of the second D flip-flop, and the input terminal D of the second D flip-flop is connected to the output terminal Q of the first D flip-flop.

[0089] When the receiving domain rx domain receives a data stream from the previous slave station or master station, the receiving enable signal rx_valid in the data stream is sent to the above D flip-flop, the first multiplexer and the second multiplexer respectively, the receiving clock rx_clk in the data stream is sent to the two D flip-flops respectively, and the receiving data rx_data in the data stream is sent to the first storage unit RAM[1] and the second storage unit RAM[0] for storage; the receiving data rx_data is written into the storage unit RAM through the receiving domain rx domain.

[0090] first,

[0091] If the receiving enable signal rx_valid is at a high level, the receiving enable signal rx_valid will act on the first multiplexer and the second multiplexer, so that when the receiving clock rx_clk received by the two D flip-flops is at a rising edge, the outputs of the first multiplexer and the second multiplexer are inverted and jump, and the output ends of the two D flip-flops output two latch enable signals latch_0 and latch_1 with the same frequency and opposite phases;

[0092] Such a circuit structure generates two different latch enable signals latch_0 and latch_1 , and the frequencies of the two latch enable signals latch_0 and latch_1 are exactly half of the frequency of the receiving clock rx_clk.

[0093] If the receive enable signal rx_valid is at a low level, it means that the received data is invalid and the state of the circuit will not jump as expected.

[0094] When the latch enable signal is obtained, the receiving enable signal rx_valid is directly connected to the write enable signal writing terminal wr_en of the storage unit RAM. The receiving enable signal rx_valid and the latch enable signals latch_0 and latch_1 are logically processed through the first and second AND gates respectively:

[0095] When the output of the first AND gate is at a high level and the output of the second AND gate is at a low level, the storage unit RAM selects to store the received data rx_data in the first storage unit RAM[1];

[0096] When the output of the first AND gate is at a low level and the output of the second AND gate is at a high level, the storage unit RAM selects to store the received data rx_data in the second storage unit RAM[0];

[0097] Secondly,

[0098] Data transmission is non-resident, and there is no need to wait until all data is received before reading and sending. When the receive enable signal rx_valid is valid, that is, it is at a high level, the receive enable signal rx_valid is input to the above D flip-flop, and the output signal of the output terminal Q of the above D flip-flop is directly used as the enable read signal of the storage unit RAM; in this way, a D flip-flop is used to synchronize the receive enable signal to the transmit clock domain, and synchronize to the transmit clock domain. The synchronized signal is used as the enable read signal rd_en of the storage unit RAM.

[0099] Then,

[0100] With the read enable signal, a signal is also needed to index the storage unit RAM.

[0101] The enable read signal rd_en is input into the two D flip-flops of the shift register.

[0102] In the initial state, the state of one flip-flop is 0, which represents the low level of the input, and the state of the other flip-flop is 1, which represents the high level of the input;

[0103] The initial states of the two flip-flops are set to "01". At the rising edge of each transmit clock tx clk (generated automatically by the crystal oscillator after power-on), the outputs of the two D flip-flops interact to implement a shift operation. The total state of the two D flip-flops of the entire shift register cycles between the two states of "01" and "10". The entire shift register outputs the lower bit shift[0] of the total state of the two D flip-flops to an input of the third AND gate; that is, the lower bit output of the shift register is used as an input shift[0] in the third AND gate.

[0104] at last,

[0105] The read enable signal rd_en of the storage unit RAM and the lower bit shift[0] output by the shift register are ANDed through the third AND gate:

[0106] When the output of the third AND gate is at a high level, the data in the second storage unit RAM[0] is selected and read out through the third multiplexer;

[0107] When the output of the third AND gate is at a low level, the data in the first storage unit RAM[1] is selected and read out through the third multiplexer;

[0108] The data Data_out output by the third multiplexer is the data after cross-clock domain synchronization, and can be directly transmitted to the next slave station as the transmission data tx_data in the transmission clock domain.

[0109] To further explain Figure 4The changes of signals at each pin in the circuit and the timing of data cross-clock domain processing are as follows: Figure 5 As shown. When data reception is valid, the receive enable signal rx_valid is at a high level, and the received data rx_data is connected to the data write terminal wr_data of the storage unit RAM. The wr_data data changes at the falling edge of the receive clock rx_clk and remains stable at the rising edge. If latch_1 is detected to be at a high level at the rising edge of the receive clock rx_clk, the stable wr_data data is stored in the second storage unit RAM[0]. When latch_0 is detected to be at a high level, the stable wr_data data is stored in the first storage unit RAM[1]. When the two latch enable signals latch_0 and latch_1 are both at a low level at the rising edge of the receive clock rx_clk, the data in the first storage unit RAM[1] and the second storage unit RAM[0] remain unchanged, and the two storage units alternately access the received data.

[0110] Since the data transmission mode is non-resident, the data stays in the slave station for a very short time. Therefore, when the received data is valid, that is, when the receive enable signal rx_valid is high, a D flip-flop is used to process the single-bit signal rx_valid across clock domains, and synchronize the receive enable signal rx_valid from the receive clock rx_clk domain to the transmit clock tx_clk domain. The synchronized signal is the enable read signal rd_en. Then, according to the enable read signal rd_en and the state value of the shift register, the data in the storage unit RAM is read.

[0111] If the read enable signal rd_en is detected as high level at the rising edge of the transmit clock tx_clk and the state of the shift register is "01", shift[0]=="1", the data is read from the second storage unit RAM[0] and output. If the read enable signal rd_en is detected as high level at the rising edge of the transmit clock tx_clk and the state of the shift register is "10", the data is read from the first storage unit RAM[1] and output. The timing diagram assumes that a total of four data are sent, and the initial state of the shift register is set to "01". The figure assumes that the phase difference between the receive clock and the transmit clock is 90°.

[0112] Step 4: Write the test software and set the number of tests;

[0113] The test software can automatically adjust the test times. It can also customize the content of the sent data and display the execution status of the output after the slave station receives the command, so as to further judge the correctness of the data transmission between each station. The test software also tests the average cycle period of the master station and the network jitter performance.

[0114] Step 5, calculating the number of times data frames are sent and received;

[0115] For each complete frame of data sent, the count is increased by one, and for the number of received data frames, the count is increased by one only after the data comparison is correct.

[0116] Step 6: The data packet loss rate is finally calculated to evaluate the performance of the entire data system;

[0117] For the data transmission system after cross-clock domain processing, its packet loss rate is tested, and the network performance of slave cross-clock domain processing using different methods is compared. The specific test results are as follows: Figure 5 It can be seen that the proposed two-division frequency enabling latching method can achieve 100% data correct transmission, and its network delay and jitter time are relatively short. At the same time, it only requires two units of data cache space, which greatly improves the cache unit resource utilization.

Claims

1. A non-resident data cross-clock domain method based on the same frequency and different phase clocks, characterized in that The method comprises the following steps: Step 1: Design a master station data transmission system based on UDP protocol and a slave station data transmission system based on EtherCAT protocol; Step 2, calling the IP core FIFO method and the asynchronous dual-port RAM method to process the cross-clock domain part of the resident data involved in the master station; In the step 2, for the data sent by the computer to the main station, an IP core is called in the Ethernet receiving message buffer module rcv_buffer of the main station to cache the data in the asynchronous FIFO storage module, and all the data are converted to the sending clock domain of the main station network port 0 and transmitted to the modules at all levels behind the Ethernet receiving message buffer module rcv_buffer until the data is transmitted to the UDP message receiving module udp_rcv; At the same time, an asynchronous dual-port RAM storage module is written in the UDP message receiving module udp_rcv, and the data part of the UDP message is cached in the asynchronous dual-port RAM storage module, completing the cross-clock domain processing of the data in the clock domain sent by the master station network port 0 to the data in the clock domain sent by the master station network port 1. After that, the data in the clock domain sent by the master station network port 1 is encapsulated with the EtherCAT protocol and finally sent from the UDP message receiving module udp_rcv to the slave station; Step 3, using a two-frequency division enabling latching method to process the cross-clock domain transmission of the slave station non-resident data; In the step three, a two-way frequency division enabling latching cross-clock domain method circuit is constructed in the transmission between slave stations, including a receiving domain rx domain, a sending domain tx domain, a storage unit RAM, three multiplexers, three independent D flip-flops, a shift register composed of two D flip-flops and three AND gates; the receiving domain rx domain and the sending domain tx domain are respectively connected to the storage unit RAM, the receiving domain rx domain is respectively connected to the first multiplexer, the second multiplexer, the three independent D flip-flops, the first AND gate, and the second AND gate, the first independent D flip-flop is respectively connected to the storage unit RAM, the shift register, and the third AND gate, the shift register is respectively connected to the sending domain tx domain, the storage unit RAM, and the third AND gate, the first multiplexer and the second multiplexer connected to the receiving domain rxdomain are respectively connected to the second independent D flip-flop and the third independent D flip-flop, the second independent D flip-flop and the third independent D flip-flop are respectively connected to the first AND gate and the second AND gate connected to the receiving domain rx domain, and the receiving domain rx The first AND gate and the second AND gate connected to the domain are both connected to the storage unit RAM, and the third multiplexer is respectively connected to the storage unit RAM, the data reading end rdata of the storage unit RAM, and the third AND gate; The described two-division frequency enabling latch cross-clock domain method circuit, the clock output end of the receiving domain rx domain is connected to the clock receiving end rx_clk of the storage unit RAM, the enable signal output end of the receiving domain rx domain is connected to the write enable signal writing end wr_en of the storage unit RAM, the data output end of the receiving domain rx domain is connected to the data writing end wr_data of the storage unit RAM; the clock sending end tx_clk of the RAM is connected to the clock input end of the sending domain tx domain, and the data reading end rdata of the RAM is connected to the data input end of the sending domain tx domain; The clock output terminal of the receiving domain rx domain is respectively connected to the clock trigger terminals of the second independent D flip-flop and the third independent D flip-flop, the enable signal output terminal of the receiving domain rx domain is respectively connected to the selection control terminals of the first multiplexer and the second multiplexer and one input terminal of each of the first and second AND gates, and the enable signal output terminal of the receiving domain rx domain is connected to the input terminal D of the first independent D flip-flop; The output terminals of the first multiplexer and the second multiplexer are connected to the input terminals D of the second independent D flip-flop and the third independent D flip-flop respectively, the output terminals Q of the second independent D flip-flop and the third independent D flip-flop are connected to the other input terminals of the first AND gate and the second AND gate respectively, and the output terminals Q of the second independent D flip-flop and the third independent D flip-flop are connected to the 1-way input terminals of the first multiplexer and the second multiplexer respectively, the 0-way input terminal of the first multiplexer is connected to the input of a low level signal and the 0-way input terminal of the second multiplexer is connected to the input of a high level signal; The output terminal Q of the first independent D flip-flop is respectively connected to the enable signal reading terminal rd_en of the storage unit RAM and an input terminal of the third AND gate, the clock sending terminal of the storage unit RAM is respectively connected to the clock triggering terminal of the first independent D flip-flop and the clock triggering terminals of the two D flip-flops in the shift register, the output terminal of the second D flip-flop in the shift register is connected to an input terminal of the third AND gate, and the output terminal of the third AND gate is connected to the selection control terminal of the third multiplexer; The storage unit RAM is internally divided into a first storage unit RAM[1] and a second storage unit RAM[0], the output ends of the first AND gate and the second AND gate are respectively connected to the write ends of the first storage unit RAM[1] and the second storage unit RAM[0], the read ends of the first storage unit RAM[1] and the second storage unit RAM[0] are respectively connected to the 1-way input end and the 0-way input end of the third multiplexer, the output end of the third multiplexer is connected to the data read end rdata of the RAM and the data input end of the sending domain tx domain, and the data tx_data is sent; In the shift register, the input terminal D of the first D flip-flop is connected to the output terminal Q of the second D flip-flop, and the input terminal D of the second D flip-flop is connected to the output terminal Q of the first D flip-flop; When the receiving domain rx domain receives the data stream, the receiving enable signal rx_valid in the data stream is sent to the first independent D flip-flop, the first multiplexer and the second multiplexer respectively, the receiving clock rx_clk in the data stream is sent to the second independent D flip-flop and the third independent D flip-flop respectively, and the receiving data rx_data in the data stream is sent to the first storage unit RAM[1] and the second storage unit RAM[0] for storage; first, If the receiving enable signal rx_valid is at a high level, the receiving enable signal rx_valid will act on the first multiplexer and the second multiplexer, so that when the receiving clock rx_clk received by the second independent D flip-flop and the third independent D flip-flop is at a rising edge, the outputs of the first multiplexer and the second multiplexer are inverted and jump, and the output ends of the second independent D flip-flop and the third independent D flip-flop output two latch enable signals latch_0 and latch_1 with the same frequency and opposite phases; When the latch enable signal is obtained, the receiving enable signal rx_valid is directly connected to the write enable signal writing terminal wr_en of the storage unit RAM. The receiving enable signal rx_valid and the latch enable signals latch_0 and latch_1 are respectively processed logically through the first AND gate or the second AND gate: When the output of the first AND gate is at a high level and the output of the second AND gate is at a low level, the storage unit RAM selects to store the received data rx_data in the first storage unit RAM[1]; When the output of the first AND gate is at a low level and the output of the second AND gate is at a high level, the storage unit RAM selects to store the received data rx_data in the second storage unit RAM[0]; Secondly, When the receiving enable signal rx_valid is valid, that is, at a high level, the receiving enable signal rx_valid is input to the first independent D flip-flop, and the output signal of the output terminal Q of the first independent D flip-flop is directly used as the enable read signal of the storage unit RAM; Then, The enable read signal rd_en is input into the two D flip-flops of the shift register. In the initial state, the state of one D flip-flop is 0, which represents the low level of the input, and the state of the other D flip-flop is 1, which represents the high level of the input; At the rising edge of each transmit clock tx clk, the outputs of the two D flip-flops interact to implement a shift operation; the entire shift register outputs the lower bit shift[0] of the total state of the two flip-flops to one input terminal of the third AND gate; at last, The read enable signal rd_en of the storage unit RAM and the lower bit shift[0] output by the shift register are ANDed through the third AND gate: When the output of the third AND gate is at a high level, the data in the second storage unit RAM[0] is selected and read out through the third multiplexer; When the output of the third AND gate is at a low level, the data in the first storage unit RAM[1] is selected and read out through the third multiplexer; The data Data_out output by the third multiplexer is used as data synchronized across clock domains; The frequencies of the two latch enable signals latch_0 and latch_1 are half the frequency of the reception clock rx_clk.

2. The method for non-resident data crossing clock domains based on same-frequency but different-phase clocks according to claim 1 is characterized in that: In the master station data transmission system based on UDP protocol and slave station data transmission based on EtherCAT protocol, the EtherCAT protocol is used for transmission between the master station and the slave station and between the slave stations.

3. The method for non-resident data crossing clock domains based on same-frequency but different-phase clocks according to claim 1 is characterized in that: The master station includes an Ethernet message receiving buffer module rcv_buffer, an ARP message receiving module arp_rcv, an IP message receiving module ip_rcv, a buffer connection module nwk_tx_abt, a UDP message receiving module udp_rcv, a UDP message sending module udp_send, an ARP message sending module arp_send, an IP message sending module ip_send, an ARP cache module Mac_cache, an icmp reply message module icmp_reply and an Ethernet message sending module mac_tx_abt; The output end of the Ethernet receiving message buffer module rcv_buffer is respectively connected to the input end of the ARP message receiving module arp_rcv and the IP message receiving module ip_rcv, the output end of the IP message receiving module ip_rcv is respectively connected to the input end of the UDP message receiving module udp_rcv and the icmp reply message module icmp_reply, the output end of the icmp reply message module icmp_reply and the output end of the UDP message sending module udp_send are respectively connected to the two input ends of the buffer connection module nwk_tx_abt; The output end of the ARP message receiving module arp_rcv is respectively connected to the input end of the ARP cache module Mac_cache and an input end of the ARP message sending module arp_send. At the same time, an output end of the ARP cache module Mac_cache is connected to another input end of the ARP message sending module arp_send. The output ends of the ARP cache module Mac_cache and the buffer connection module nwk_tx_abt are respectively connected to the two input ends of the IP message sending module ip_send. The output ends of the IP message sending module ip_send and the ARP message sending module arp_send are respectively connected to the two input ends of the Ethernet message sending module mac_tx_abt.

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