Counting circuit, memory device and system

By introducing a clock control unit into the counting circuit, clock control signals with different signal values ​​are generated to control the number of latches of the output unit, thus solving the power consumption limitation problem, improving the performance of the storage device and reducing the cost.

CN114640343BActive Publication Date: 2026-03-31YANGTZE MEMORY TECH CO LTD
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Patent Information

Application Number
CN202210126463.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-02-10
Publication Date
2026-03-31
Estimated Expiration
2042-03-31

AI Technical Summary

Technical Problem

With the development of technology, power consumption has become a constraint on further improving the performance of counting circuits. In existing counting circuits, the number of latches by the flip-flops is positively correlated with power consumption, which limits the performance of memory devices.

Method used

By introducing a clock control unit into the counting circuit, clock control signals with different signal values ​​are generated to control the number of latches of the output unit, thereby reducing latch operations and thus reducing power consumption.

Benefits of technology

It effectively reduces the power consumption of the counting circuit, improves the performance of the memory device, saves chip area, and reduces costs.

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Abstract

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.
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