Counting circuit, memory device and system

Abstract

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a counting circuit, a storage device, and a system. Background Technology

[0002] In address generation or counting circuits, a clock signal can trigger a flip-flop link to automatically increment or count the address. Depending on the clock input method, counting can be categorized as synchronous or asynchronous. With continuous advancements in technology, power consumption remains a limiting factor for further improvements in the performance of counting circuits. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a counting circuit is provided, the counting circuit comprising: a clock source, a clock control unit, and N output units; wherein N is a positive integer;

[0004] The output terminal of the clock source is coupled to the input terminal of the clock control unit, the clock input terminal of the first output unit, and the clock input terminal of the Mth output unit, respectively, to provide a clock signal; where M is a positive integer less than N;

[0005] The input terminal of the clock control unit is also coupled to the output terminal of the first output unit to the output terminal of the Mth output unit, respectively;

[0006] The output terminal of the clock control unit is respectively coupled to the clock input terminal of the (M+1)th output unit to the clock input terminal of the Nth output unit;

[0007] The clock control unit is configured to generate a clock control signal based on the received clock signal and the output values ​​of the first to the Mth output units, and output the clock control signal to the clock input terminals of the (M+1)th to the Nth output units; wherein the clock control signal has a first signal value and a second signal value with different signal values.

[0008] The (M+1)th to the Nth output units are configured to latch when the received clock control signal switches from the second signal value to the first signal value;

[0009] The (M+1)th to the Nth output units are also configured to maintain their current state value unchanged when the received clock control signal is the second signal value.

[0010] In some embodiments, the clock control unit is specifically configured to generate the clock control signal having the first signal value when the rising edge of the received clock signal is reached and the output values ​​of the first output unit to the Mth output unit are all at a logic high level.

[0011] The clock control unit is further configured to generate the clock control signal having the second signal value when the rising edge of the received clock signal is reached and at least one of the output values ​​of the first output unit to the Mth output unit is at a logic low level.

[0012] In some embodiments, the clock control unit includes: an inverter, a first logic circuit, an enable flip-flop, and a second logic circuit; wherein,

[0013] The input terminal of the inverter is coupled to the output terminal of the clock source, and the output terminal of the inverter is coupled to the clock input terminal of the enable trigger.

[0014] The input terminal of the first logic circuit is coupled to the output terminal of the first output unit to the output terminal of the Mth output unit, and the output terminal of the first logic circuit is coupled to the data input terminal of the enable flip-flop; the output terminal of the enable flip-flop is coupled to the first input terminal of the second logic circuit.

[0015] The second input terminal of the second logic circuit is coupled to the output terminal of the clock source, and the output terminal of the second logic circuit is coupled to the clock input terminals of the (M+1)th output unit to the Nth output unit;

[0016] The inverter is configured to output an inverted clock signal based on the received clock signal;

[0017] The first logic circuit is configured to generate a first logic signal when the output terminals of the first output unit to the Mth output unit are all output at a logic high level.

[0018] The first logic circuit is further configured to generate a second logic signal with a signal value different from the first logic signal when at least one logic low level is output at the output terminal of the first output unit to the output terminal of the Mth output unit.

[0019] The enable trigger is configured to generate a first enable signal based on the received first logic signal at the rising edge of the inverted clock signal.

[0020] The enable trigger is further configured to generate a second enable signal with a different signal value from the first enable signal based on the received second logic signal at the rising edge of the inverted clock signal.

[0021] The second logic circuit is configured to generate the clock control signal having the first signal value based on the received first enable signal at the rising edge of the clock signal.

[0022] The second logic circuit is further configured to generate the clock control signal having the second signal value based on the received second enable signal at the rising edge of the clock signal.

[0023] In some embodiments, the first logic circuit includes: a first AND gate;

[0024] The second logic circuit includes a second AND gate.

[0025] In some embodiments, the output unit includes a trigger.

[0026] In some embodiments, the trigger includes a D-type trigger.

[0027] In some embodiments, the counting circuit further includes:

[0028] An adder, wherein the input terminals of the adder are respectively coupled to the output terminals of the N output units, and the output terminals of the adder are respectively coupled to the input terminals of the N output units.

[0029] In some embodiments, the adder includes N adding units;

[0030] The input terminal of the kth addition unit is coupled to the output terminal of the first output unit to the kth output unit;

[0031] The output of the kth addition unit is coupled to the input of the kth output unit; where k is a positive integer less than or equal to N.

[0032] According to a second aspect of the present disclosure, a storage device is provided, comprising:

[0033] A storage cell array, comprising multiple rows of storage cells;

[0034] The peripheral circuitry, coupled to the memory cell array, includes the counting circuitry described in the above embodiments.

[0035] According to a third aspect of the present disclosure, a storage system is provided, comprising:

[0036] The storage device as described in the above embodiments; and

[0037] A memory controller is coupled to the memory device and configured to control the memory device.

[0038] In this embodiment of the present disclosure, the clock control unit generates a clock control signal based on the clock signal output from the received clock source and the output values ​​of the first output unit to the Mth output unit, and outputs the clock control signal to the clock input terminals of the (M+1)th output unit to the Nth output unit.

[0039] Generally, power consumption is positively correlated with the number of latches of the output units in a counting circuit. Compared to each output unit latching once at each clock edge of the clock signal output from the clock source, in this embodiment, the (M+1)th to Nth output units latch when the received clock control signal switches from the second signal value to the first signal value. Within one cycle of the clock control signal, the number of times the clock control signal switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal. Therefore, the number of latches of the (M+1)th to Nth output units is reduced, thus effectively reducing the power consumption of the counting circuit. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the circuit structure of a counting circuit according to an exemplary embodiment;

[0041] Figure 2 yes Figure 1 A timing diagram of a counting circuit;

[0042] Figure 3 This is a block diagram of another counting circuit according to an exemplary embodiment;

[0043] Figure 4a This is a first schematic diagram of the circuit structure of another counting circuit according to an exemplary embodiment;

[0044] Figure 4b This is a second schematic diagram of the circuit structure of another counting circuit according to an exemplary embodiment;

[0045] Figure 5 yes Figure 4b A timing diagram of another counting circuit;

[0046] Figure 6 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0047] Figure 7 This is a partial cross-sectional view of a memory cell array including NAND memory strings, according to an embodiment of the present disclosure;

[0048] Figure 8 This is a block diagram of a memory including a memory cell array and peripheral circuitry, according to embodiments of the present disclosure.

[0049] Figure 9This is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0050] Figure 10a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0051] Figure 10b This is a schematic diagram of a solid-state drive (SSD) according to an embodiment of the present disclosure. Detailed Implementation

[0052] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0053] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0054] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0055] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0056] Counting circuits have a wide range of applications. They can be used not only to count the number of clock pulses, but also for frequency division, timing, and generating clock pulses to meet the needs of applications such as digital measurement, calculation, program control, event statistics, and system timing.

[0057] This disclosure describes embodiments using a memory counting circuit. However, this disclosure is not limited thereto.

[0058] Figure 1 This is a schematic diagram of a counting circuit according to an exemplary embodiment. (Refer to...) Figure 1 As shown, the counting circuit 100 includes a clock source and n+1 flip-flops, where n is a positive integer. The output of the clock source is coupled to the clock inputs of the n+1 flip-flops to provide a clock signal Clk. The counting circuit 100 also includes a combinational logic unit, the inputs of which are coupled to the outputs of the n+1 flip-flops, and the outputs of which are coupled to the inputs of the n+1 flip-flops.

[0059] The working principle of the counting circuit 100 is as follows: n+1 flip-flops can be denoted as D0, D1, D2, ..., Dn. The explanation will focus on D0, D1, D2, ..., Dn as rising-edge flip-flops. Flip-flops D0 to Dn are configured to latch on the rising edge of the first level when the clock signal output from the received clock source is at the first level; flip-flops D0 to Dn are also configured to maintain their current state value when the received clock signal is at the second level; where the second level is different from the first level.

[0060] Here, the outputs of n+1 flip-flops are connected sequentially to output an n+1-bit binary sequence CA.<n:0> To the input of the combinational logic unit, the combinational logic unit processes the sequence CA<n:0> After performing logical operations, the output is an n+1 bit binary sequence CA1.<n:0> and the n+1 bit binary sequence CA1<n:0> Starting from bit zero, the corresponding inputs are placed into the input terminals D0, D1, D2, ..., Dn. For example, the output binary sequence CA1<n:0> The output can be 0000…0110 (n+1 bits in total). Then, the zeroth bit 0 is output to the input of flip-flop D0, the first bit 1 is output to the input of flip-flop D1, the second bit 1 is output to the input of flip-flop D2, the third bit 0 is output to the input of flip-flop D3, and so on until the (n+1)th bit 0 is output to the input of flip-flop Dn.

[0061] Figure 2 This is a timing diagram of a counting circuit according to an exemplary embodiment. (Refer to...) Figure 2 When the initial output value of each flip-flop is 0, at each rising edge of the clock signal Clk output by the clock source, each flip-flop D0, D1, D2, ..., Dn is latched once, and the output of the n+1 flip-flops finally outputs an n+1 bit binary sequence CA.<n:0> To the combinational logic unit. The combinational logic unit can be an "increment 1" logic circuit, and the input and output sequences of the combinational logic unit satisfy the logical expression CA1.<n:0> =CA<n:0> +1. Combinational logic unit for sequence CA<n:0> After performing the "add 1" logical operation, we get CA1.<n:0> .

[0062] It is important to emphasize that CA<n:0> The count value and CA1<n:0> The count value is an n+1 bit binary sequence consisting of 0s and 1s. For ease of reading, the n+1 bit binary sequence is converted to decimal to obtain CA.<n:0> The count value and CA1<n:0> The count value. Specifically, CA<n:0> The count values ​​follow the sequence 0, 1, 2, 3, 4, 5, 6, ..., 2 n+1 -1, CA1<n:0> The count values ​​follow the sequence 1, 2, 3, 4, 5, 6, ..., 2n+1 The count value is represented in decimal here.

[0063] Generally speaking, power consumption is positively correlated with the number of times the flip-flops in the counting circuit latch. In this counting circuit 100, each flip-flop latches once at each clock edge of the clock signal output by the clock source, causing all flip-flops in the counting circuit to generate a large amount of power consumption in each clock cycle, thereby greatly limiting the performance of the memory device.

[0064] In view of this, embodiments of the present disclosure provide another counting circuit.

[0065] Figure 3 This is a block diagram illustrating another counting circuit according to an exemplary embodiment. (Refer to...) Figure 3 As shown, the counting circuit includes: a clock source 301, a clock control unit 302, and N output units 303; where N is a positive integer;

[0066] The output terminal of clock source 301 is coupled to the input terminal of clock control unit 302, the clock input terminal of the first output unit, and the clock input terminal of the Mth output unit, respectively, to provide clock signals; where M is a positive integer less than N;

[0067] The input terminal of the clock control unit 302 is also coupled to the output terminal of the first output unit to the output terminal of the Mth output unit, respectively;

[0068] The output terminal of the clock control unit 302 is coupled to the clock input terminal of the (M+1)th output unit to the clock input terminal of the Nth output unit, respectively.

[0069] The clock control unit 302 is configured to generate a clock control signal based on the received clock signal and the output values ​​of the first output unit to the Mth output unit, and output the clock control signal to the clock input terminals of the (M+1)th to the Nth output units; wherein the clock control signal has a first signal value and a second signal value with different signal values.

[0070] The (M+1)th to the Nth output units are configured to latch when the received clock control signal switches from the second signal value to the first signal value;

[0071] The (M+1)th to the Nth output units are also configured to maintain their current state values ​​when the received clock control signal is the second signal value.

[0072] In this embodiment, the output terminals of the N output units 303 are output in parallel. The counting circuit counts the first signal value or the second signal value in the clock signal input to the clock source 301 one by one through the N output units 303, and outputs the count value to realize the counting function. In addition, the N output units 303 in the counting circuit can also adopt other connection methods to realize forward counting or reverse counting, and this disclosure is not limited to this.

[0073] In some embodiments, refer to Figure 3 The input terminal of the clock control unit 302 is also coupled to the output terminals of the first output unit and the Mth output unit, respectively. The clock control unit 302 can receive the output values ​​of the first output unit to the Mth output unit, where M is a positive integer less than N, and the value of M can be 1, 2, 3 to N-1. This embodiment is described with M=2 and N=8. However, this disclosure is not limited thereto.

[0074] Here, the clock control signal generated by the clock control unit 302 has two states: a first signal value and a second signal value. This will be described with the first signal value being a logic high level and the second signal value being a logic low level. However, this disclosure is not limited to this. The specific generation process of the clock control signal will be explained from two aspects below.

[0075] Firstly, the clock control unit 302 receives the output values ​​of the first and second output units. When both output values ​​are at a logic high level, a first logic signal is generated. The clock control unit 302 then generates a clock control signal with a first signal value based on the received clock signal and the first logic signal. The clock input terminals of the third to eighth output units are latched when the received clock control signal switches from a second signal value to a first signal value. That is, latching occurs on the rising edge of the clock control signal. The rising edge is the process of switching from a logic low level (e.g., 0) to a logic high level (e.g., 1).

[0076] Secondly, the clock control unit 302 receives the output values ​​of the first and second output units, whereby a second logic signal is generated when at least one logic low level is present, and the generated signal value differs from the first logic signal. The clock control unit 302 generates a clock control signal with the second signal value based on the received clock signal and the second logic signal. When the clock input terminals of the third to eighth output units receive the second signal value (i.e., a logic low level), their current state values ​​remain unchanged. Specifically, when the third to eighth output units receive a logic low-level clock control signal, they do not trigger latching. At this time, the outputs of the third to eighth output units do not change with the input signals at the data input terminals of the output units, remaining unchanged from the state value input when the previous clock control signal switched from the second signal value to the first signal value.

[0077] It is important to emphasize that the N output units 303 can be information storage devices with memory functions and two stable states, namely 0 and 1. Under the action of an external input signal, they can flip from one stable state to the other. The clock control unit 302 will only generate a clock control signal with a first signal value when the output values ​​of the first and second output units are both at a logic high level, so that the output units will latch when the clock control signal switches from the second signal value to the first signal value.

[0078] Reference Figure 5 For example, when M=2 and N=8, the clock period of the clock control signal Clk_gate output by the clock control unit 302 is denoted as T1, and the clock period of the clock signal Clk output by the clock source 301 is denoted as T2. When M=2, the clock period T1 is 4 times the clock period T2. Figure 5 As shown, within one clock cycle T1 of the clock control signal Clk_gate, the number of times the clock control signal Clk_gate output by the clock control unit 302 switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal Clk.

[0079] In this embodiment, a clock control unit 302 is added to the counting circuit. Compared to the clock signal output by clock source 301, where each output unit latches once at each clock edge, in this embodiment, the (M+1)th to Nth output units latch when the received clock control signal switches from the second signal value to the first signal value. Within one period T1 of the clock control signal, the number of times the clock control signal switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal Clk. Therefore, the number of latches by the (M+1)th to Nth output units is reduced, thus effectively reducing the power consumption of the counting circuit.

[0080] In some embodiments, the clock control unit is specifically configured to generate a clock control signal having a first signal value when the rising edge of the received clock signal is reached and the output values ​​of the first output unit to the Mth output unit are all at a logic high level.

[0081] The clock control unit is further configured to generate a clock control signal with a second signal value when the rising edge of the received clock signal is reached and at least one of the output values ​​of the first output unit to the Mth output unit is at a logic low level.

[0082] Specifically, when M=2 and N=8, the clock control unit generates a first logic signal with a logic high level or a second logic signal with a logic low level based on the two output values ​​of the first output unit and the second output unit. The outputs of the first to Nth output units are respectively the zeroth to the (N-1)th bit, and the initial state of the 8 output units is set to Q7…Q1Q0 = 00000000.

[0083] The output values ​​of the first output unit, the second output unit, and the clock control signal include the following four cases: 1) The initial output value of both the first and second output units is 0; in this case, the clock control unit performs a logical operation on 0 and 0 to generate a second logic signal with a low logic level. 2) The output value of both the first and second output units is 0; in this case, the clock control unit performs a logical operation on 0 and 1 to generate a second logic signal with a low logic level. 3) The output value of both the first and second output units is 1; in this case, the clock control unit performs a logical operation on 1 and 0 to generate a second logic signal with a low logic level. 4) The output value of both the first and second output units is 1; in this case, the clock control unit performs a logical operation on 1 and 1 to generate a first logic signal with a high logic level.

[0084] The outputs of the first and second output units can include four output scenarios: the first output unit outputs 0 and the second output unit outputs 0; the first output unit outputs 0 and the second output unit outputs 1; the first output unit outputs 1 and the second output unit outputs 0; and the first output unit outputs 1 and the second output unit outputs 1. The outputs of the first and second output units can occur in a cyclical manner according to these four scenarios.

[0085] In this embodiment, the clock control unit performs logical operations on the outputs from several output units to obtain a first logic signal or a second logic signal. Then, the clock control unit generates a clock control signal based on the received first or second logic signal. Compared to adding multiple flip-flops to reduce the number of latches required by the output units, this embodiment reuses the first to Mth output units used for counting, reducing the number of output units required by the clock control unit, ultimately reducing the area occupied by the counting circuit on the chip and saving costs.

[0086] Figure 4a This is a first schematic diagram illustrating the circuit structure of another counting circuit for a memory according to an exemplary embodiment. Figure 4b This is a second schematic diagram illustrating another circuit structure of a counting circuit for a memory according to an exemplary embodiment. (Refer to...) Figure 4a and Figure 4b The clock control unit includes: an inverter 41, a first logic circuit 42, an enable flip-flop 43, and a second logic circuit 44; wherein,

[0087] The input of inverter 41 is coupled to the output of the clock source, and the output of inverter 41 is coupled to the clock input of enable flip-flop 43.

[0088] The input terminal of the first logic circuit 42 is coupled to the output terminal of the first output unit to the output terminal of the Mth output unit; the output terminal of the first logic circuit 42 is coupled to the data input terminal of the enable flip-flop 43; the output terminal of the enable flip-flop 43 is coupled to the first input terminal of the second logic circuit 44.

[0089] The second input terminal of the second logic circuit 44 is coupled to the output terminal of the clock source, and the output terminal of the second logic circuit 44 is coupled to the clock input terminals of the (M+1)th output unit to the Nth output unit.

[0090] Inverter 41 is configured to output an inverted clock signal based on the received clock signal;

[0091] The first logic circuit 42 is configured to generate a first logic signal when the outputs of the first output unit to the Mth output unit are all logic high.

[0092] The first logic circuit 42 is also configured to generate a second logic signal with a signal value different from the first logic signal when at least one logic low level is output at the output terminal of the first output unit to the output terminal of the Mth output unit.

[0093] Enable trigger 43 is configured to generate a first enable signal based on the received first logic signal at the rising edge of the inverted clock signal;

[0094] The enable trigger 43 is also configured to generate a second enable signal with a different signal value from the first enable signal based on the received second logic signal at the rising edge of the inverted clock signal.

[0095] The second logic circuit 44 is configured to generate a clock control signal with a first signal value based on the received first enable signal at the rising edge of the clock signal.

[0096] The second logic circuit 44 is also configured to generate a clock control signal with a second signal value based on the received second enable signal at the rising edge of the clock signal.

[0097] Specifically, refer to Figure 4b When M=2 and N=8, the output terminals of the eight output units are connected in sequence, and finally the 8-bit binary sequence CA<7:0> is output to the input terminal of the combinational logic unit. After the combinational logic unit performs logical operations on the sequence CA<7:0>, it outputs the 8-bit binary sequence CA1<7:0>, and inputs the 8-bit binary sequence CA1<7:0> to the input terminals of D0, D1, D2, ..., D7 respectively, starting from the zeroth bit.

[0098] Figure 5 yes Figure 4b A timing diagram of another counting circuit. (Combined with...) Figure 4b and Figure 5 Let the initial state of the eight output units be Q7...Q1Q0 = 00000000. The first logic circuit 42 performs a logical AND operation on the outputs of the two flip-flops D0 and D1 from the output units. The initial output value of D0 is 0, and the initial output value of D1 is 0. At this time, the first logic circuit 42 generates a second logic signal with a logic low level. Then, the combinational logic unit performs a logical operation on the sequence 00000000 and outputs an eight-bit binary sequence 00000001. The eight-bit binary sequence 00000001 is then input to the data input terminals of D0, D1, D2, ..., D7, starting from the zeroth bit. At this time, the output value of D0 is 1, and the output value of D1 is 0. Performing a logical AND operation on the output values ​​of D0 and D1 yields a result of 0. At this time, the first logic circuit generates a second logic signal with a logic low level.

[0099] Similarly, after performing a logical operation on the sequence 00000001, the combinational logic unit outputs an 8-bit binary sequence 00000010. This 8-bit binary sequence 00000010 is then input to the data input terminals D0, D1, D2, ..., D7, starting from bit zero. The output value of D0 is 0, and the output value of D1 is 1. Performing a logical AND operation on the output values ​​of D0 and D1 yields a result of 0. At this point, the first logic circuit generates a second logic signal with a logic low level. Then, after performing a logical operation on the sequence 00000010, the combinational logic unit outputs an 8-bit binary sequence 00000011. This 8-bit binary sequence 00000011 is then input to the data input terminals D0, D1, D2, ..., D7, starting from bit zero. The output value of D0 is 1, and the output value of D1 is 1. Performing a logical AND operation on the output values ​​of D0 and D1 yields a result of 1. At this point, the first logic circuit generates a second logic signal with a logic high level. The output CA_0m of the first logic circuit cycles through the numbers 00, 01, 10, and 11 as described above.

[0100] Reference Figure 5 Inverter 41 outputs an inverted clock signal Clk_n to the clock input of enable flip-flop 43. When the output values ​​of D0 and D1 are both 1, the output CA_0m of the first logic circuit generates a logic high-level first logic signal, which is input to the data input of enable flip-flop 43. At the rising edge of the clock signal Clk_n, enable flip-flop 43 generates a logic high-level first enable signal en_gate based on the received first logic signal CA_0m. The second logic circuit 44 is configured to perform a logical AND operation on the clock signal Clk and the signal en_gate output by enable flip-flop 43 to obtain the clock control signal Clk_gate.

[0101] Combination Figure 4b and Figure 5 ,like Figure 5 As shown, within the clock cycle T1 of a counting circuit of the clock control signal Clk_gate, the number of times the clock control signal Clk_gate output by the clock control unit 302 switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal Clk, and the number of signals at the first signal value is less than the number of signals at the first signal value in the clock signal output by the clock source 301.

[0102] Compared to the clock signal Clk output from clock source 301, where each output unit latches once at each clock edge, in this embodiment, the (M+1)th to Nth output units latch when the received clock control signal Clk_gate switches from the second signal value to the first signal value. Within one period T1 of the clock control signal Clk_gate, the number of times the clock control signal Clk_gate switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal Clk, thus reducing the number of latches for the (M+1)th to Nth output units.

[0103] It should be emphasized that the inverter 41, the first logic circuit 42, the enable flip-flop 43, and the second logic circuit 44 in the above example are merely schematic representations of one configuration of the clock control unit, intended to convey this disclosure to those skilled in the art. However, this disclosure is not limited thereto. A clock control unit composed of enable flip-flops combined with different logic circuits can also be used to output the clock control signal Clk_gate to the clock input terminals of the (M+1)th to Nth output units.

[0104] It should be understood that a practical clock control unit may include multiple logic circuits. The number of enable flip-flops may also be set according to the number of output units included in the counting circuit in the actual memory.

[0105] In this embodiment, the M+1 to Nth output units latch when the received clock control signal Clk_gate switches from the second signal value to the first signal value. Within one period T1 of the clock control signal Clk_gate, the number of times the clock control signal Clk_gate switches from the second signal value to the first signal value is less than the number of clock edges of the clock signal Clk. Therefore, the number of latching operations of the M+1 to Nth output units is reduced, thus effectively reducing the power consumption of the counting circuit. Furthermore, compared to adding multiple flip-flops and multiple logic circuits, this embodiment uses an inverter 41, a first logic circuit 42, an enable flip-flop 43, and a second logic circuit 44 to form a simple clock control unit, reducing the area occupied by the counting circuit on the chip and saving costs.

[0106] In some embodiments, the first logic circuit 42 includes a first AND gate A1; the second logic circuit 44 includes a second AND gate A2.

[0107] In this embodiment of the disclosure, a first AND gate performs a bitwise AND operation on the outputs of several adjacent output units to obtain a first logic signal or a second logic signal. Then, the clock control unit generates an enable signal based on the received logic signal using an enable flip-flop. A second AND gate performs a bitwise AND operation on the clock signal and the enable signal to obtain a clock control signal.

[0108] Compared to adding multiple flip-flops and logic gates to reduce the number of latches for the output unit, the present invention uses AND gates to implement the functions of the first and second logic circuits, which can reduce the area occupied by the counting circuit on the chip and save costs.

[0109] In some embodiments, the output unit includes a trigger.

[0110] Here, the counting circuit is composed of flip-flops. The counting circuit uses N flip-flops to count the first or second signal value in the clock signal input from the clock source one by one, so as to output the count value and realize the counting function.

[0111] In some embodiments, the trigger includes a D-type trigger.

[0112] Here, each of the N output units can include a D-type flip-flop. The ports of the D-type flip-flop include a clock input Clk, a data input D, an output Q, and an inverting output Q. The triggering methods of the D-type flip-flop can include level triggering and edge triggering. Level triggering can be triggered when the clock pulse is at a logic high level, while edge triggering can be triggered on the rising edge of the clock signal. The specific triggering method is not limited.

[0113] It is understandable that the flip-flops in the output unit can be configured with different types and numbers according to the counting requirements and output change logic, and the specific structure is not limited. The output unit can be composed of various flip-flops with information storage functions, and the flip-flops can also include RS flip-flops, T flip-flops, and JK flip-flops, etc.

[0114] In some embodiments, the counting circuit further includes:

[0115] An adder has its inputs coupled to the outputs of N output units, and its outputs coupled to the inputs of N output units.

[0116] Here, refer to Figure 4b Taking N=8, and D0, D1, D2, ..., D7 as rising-edge flip-flops as an example, let's assume the initial state of each flip-flop is Q7...Q1Q0=00...0. The outputs of the 8 flip-flops are connected in parallel, outputting an 8-bit binary sequence CA<7:0> to the input of the adder. After performing logical operations on the 8-bit binary sequence CA<7:0>, the adder outputs an 8-bit binary sequence CA1<7:0>, and inputs the 8-bit binary sequence CA1<7:0> from the least significant bit to the data inputs of D0, D1, D2, ..., D7 respectively.

[0117] Combination Figure 4a , Figure 4band Figure 5 When the initial output value of each flip-flop is 0, at each rising edge of the clock signal Clk output from the clock source, each flip-flop D0, D1, D2, ..., D7 latches once. The outputs of the eight flip-flops finally output an 8-bit binary sequence CA<7:0> to the adder. The adder can be an "add 1" logic circuit, and the input and output sequences of the adder satisfy the logical operation CA1<7:0> = CA<7:0> + 1. After performing the "add 1" logic operation on the sequence CA<7:0>, the adder obtains CA1<7:0>. The count value of CA<7:0> follows the sequence 0, 1, 2, 3, 4, 5, 6, ..., 2. 8 The count values ​​of -1, CA1<7:0> follow the sequence 1, 2, 3, 4, 5, 6, ..., 2 8 The count value is represented in decimal here.

[0118] In this embodiment of the present disclosure, the counting circuit further includes an adder, which serves as a combinational logic unit in the counting circuit and is used to cooperate with the counting circuit to complete incremental counting.

[0119] In some embodiments, the adder includes N adding units;

[0120] The input terminal of the kth adder unit is coupled to the output terminal of the first output unit to the kth output unit;

[0121] The output of the k-th adder is coupled to the input of the k-th output unit; where k is a positive integer less than or equal to N.

[0122] In some embodiments, the counting circuit 100 further includes a combinational logic unit, which may include an adder, and the adder may include N adder units.

[0123] Here, we will use N=8 as an example, refer to... Figure 4b The outputs of the 8 flip-flops are output in parallel, producing an 8-bit binary sequence CA<7:0>.

[0124] Specifically, the eight adder units can be denoted as A0 to A7. The input of the k-th adder unit is coupled to the outputs of the first to the k-th flip-flops. The following example illustrates the logical operation of the adder units. For instance, adder unit A4 performs a logical operation based on the sequence CA<4:0> output by the flip-flops D0, D1, D2, D3 to D4, outputting the logically operated sequence CA1. <4> The input of flip-flop D4 is connected to the input terminal of flip-flop D4. Adder A5 performs a logical operation based on the sequence CA<5:0> output from the output terminals of flip-flops D0, D1, D2, D3, D4 to D5, and outputs the logically operated sequence CA1. <5> To the input terminal of flip-flop D5.

[0125] Furthermore, the combinational logic units in the counting circuit can be configured with different types and numbers of combinational logic circuits according to the counting requirements and the output change logic, and the specific structure is not limited.

[0126] Figure 6 This is a schematic diagram illustrating a memory 400 according to an embodiment of the present disclosure. (Refer to...) Figure 6 As shown, the memory 400 includes:

[0127] Storage cell array 401, which includes multiple rows of storage cells;

[0128] Multiple word lines 418 are coupled to multiple rows of memory cells respectively;

[0129] The peripheral circuit 300 is coupled to a plurality of word lines 418, including a counting circuit as described in the above embodiments, and is configured to control the memory cell array.

[0130] The memory cell array 401 may be a NAND flash memory cell array, wherein the memory cell array 401 is provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 that are series-coupled and vertically stacked. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0131] In some implementations, each storage cell 406 is a single-level cell having two possible storage states and thus being able to store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range.

[0132] In some implementations, each memory cell 406 is a cell capable of storing more than a single bit of data in more than four memory states. For example, it may store two bits per cell (also known as a multi-level cell), three bits per cell (also known as a three-level cell), or four bits per cell (also known as a four-level cell). Each multi-level cell may be programmed to take a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for the erase state.

[0133] like Figure 6 As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The source select gate 410 and drain select gate 412 may be configured to activate the selected NAND memory string 408 (column of the array) during read and program operations.

[0134] In some implementations, the sources of NAND memory strings 408 in the same block 404 are coupled via the same source line (SL) 414 (e.g., common SL). In other words, according to some implementations, all NAND memory strings 408 in the same block 404 have an array common source (ACS).

[0135] According to some implementations, the drain-select gate 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, and data can be read from or written to the bit line 416 via an output bus (not shown).

[0136] In some implementations, each NAND flash memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 412) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 412 via one or more DSG lines 413. And / or, in some implementations, each NAND flash memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 410) or a deselect voltage (e.g., 0V) to the corresponding source select gate 410 via one or more SSG lines 415.

[0137] like Figure 6 As shown, the NAND storage string 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line of the selected block and the unselected blocks on the same plane as the selected block.

[0138] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 is affected by read and program operations.

[0139] In some implementations, each word line 418 is coupled to a page 420 of memory cell 406, where page 420 is the basic data unit used for programming operations. The size of a page 420, in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 in the corresponding page 420, as well as gate lines coupled to the control gates. It is understood that a memory cell row is a plurality of memory cells 406 located on the same page 420.

[0140] Figure 7 A side view of a cross-section of an exemplary memory cell array 401 including NAND memory strings 408 is shown, according to some aspects of this disclosure. Figure 7 As shown, the NAND memory string 408 can extend vertically through the memory stack layer 504 above the substrate 502. The substrate 502 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0141] The memory stack layer 504 may include alternating gate conductive layers 506 and gate dielectric layers 508. The number of pairs of gate conductive layers 506 and gate dielectric layers 508 in the memory stack layer 504 determines the number of memory cells 406 in the memory cell array 401.

[0142] The gate conductive layer 506 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 506 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 506 includes a doped polysilicon layer. Each gate conductive layer 506 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 504 as a DSG line 413, at the bottom of the memory stack 504 as an SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0143] like Figure 7As shown, the NAND flash memory string 408 includes a channel structure 512 extending vertically through the memory stack layer 504. In some embodiments, the channel structure 512 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel 520) and one or more dielectric materials (e.g., as a storage film 518). In some embodiments, the semiconductor channel 520 includes silicon, for example, polysilicon. In some embodiments, the storage film 518 is a composite dielectric layer including a tunneling layer 526, a storage layer 524 (also referred to as a "charge trap / storage layer"), and a barrier layer 522. The channel structure 512 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 520, tunneling layer 526, storage layer 524, and barrier layer 522 are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The tunneling layer 526 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 524 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 522 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 518 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0144] According to some implementation methods, such as Figure 7 As shown, a well 514 (e.g., a P-well and / or an N-well) is formed in a substrate 502, and the source terminal of the NAND memory string 408 is in contact with the well 514. For example, a source line 414 may be coupled to the well 514 to apply an erase voltage to the well 514 (i.e., the source of the NAND memory string 408) during an erase operation. In some embodiments, the NAND memory string 408 also includes a channel plug 516 at the drain terminal of the NAND memory string 408. It should be understood that, although in Figure 7 Additional components, not shown, but which may form the memory cell array 401, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0145] Return to reference Figure 6 The peripheral circuitry 300 can be coupled to the memory cell array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. The peripheral circuitry 300 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 401 by applying voltage and / or current signals to each target memory cell 406 and sensing voltage and / or current signals from each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413.

[0146] The peripheral circuit 300 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 8 Some exemplary peripheral circuitry 300 is shown, including a page buffer / sensor amplifier 604, a column decoder / bit line (BL) driver 606, a row decoder / word line (WL) driver 608, voltage generation circuitry 310, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 8 Additional peripheral circuitry not shown.

[0147] Specifically, the counting circuit of this disclosure may be located in register 614, or the counting circuit of this disclosure may be located in column decoder / bit line (BL) driver 606 and row decoder / word line (WL) driver 608.

[0148] It is understandable that here, page buffer / sensor amplifier 604, column decoder / bit line (BL) driver 606, and row decoder / word line (WL) driver 608 can represent Figure 3 Multiple drive circuits are electrically connected to the voltage generation circuit 310.

[0149] Page buffer / sensor amplifier 604 can be configured to read data from and program (write) data to memory cell array 401 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 420 of memory cell array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generation circuit 310.

[0150] The line decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect block 404 of the memory cell array 401 and select / deselect word line 418 of block 404. The line decoder / word line driver 608 can also be configured to use the word line voltage (V) generated from the voltage generation circuit 310. WLThe line decoder / word line driver 608 can also select / deselect and drive SSG line 415 and DSG line 413. As described in detail below, the line decoder / word line driver 608 is configured to perform an erase operation on memory cell 406 coupled to one or more selected word lines 418. The voltage generation circuit 310 can be configured to be controlled by the control logic unit 612 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 401.

[0151] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 401.

[0152] It should be emphasized that the peripheral circuit 300 is configured to perform the read operation provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0153] Figure 9 This is a schematic diagram illustrating a memory system 700 according to an embodiment of the present disclosure. (Refer to...) Figure 9 As shown, the memory system 700 includes:

[0154] One or more memories 400 as described in any of the above embodiments;

[0155] A memory controller 706 is coupled to the memory 400 and configured to control the memory 400 to perform the read method as described in any of the above embodiments.

[0156] System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0157] like Figure 9 As shown, system 700 may include a host 708 and a storage subsystem 702, the storage subsystem 702 having one or more memories 400, and the storage subsystem also including a memory controller 706. The host 708 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 708 may be configured to send data to the memory 400. Alternatively, the host 708 may be configured to receive data from the memory 400.

[0158] Memory 400 can be any memory device disclosed in this disclosure. Memory 400 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0159] According to some implementations, the memory controller 706 is also coupled to the host 708. The memory controller 706 can manage data stored in the memory 400 and communicate with the host 708.

[0160] In some implementations, the memory controller 706 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0161] In some implementations, the memory controller 706 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0162] The memory controller 706 can be configured to control operations of the memory 400, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions relating to data stored or to be stored in the memory 400, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to handle error correction codes (ECC) relating to data read from or written to the memory 400.

[0163] The memory controller 706 can also perform any other suitable function, such as formatting the memory 400. The memory controller 706 can communicate with external devices (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0164] The memory controller 706 and one or more memories 400 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 700 can be implemented and packaged into different types of end electronic products.

[0165] In such Figure 10a In one example shown, the memory controller 706 and a single memory 400 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a connection between the memory card 802 and a host computer (e.g., Figure 9 The memory card connector 804 is coupled to the host 708 in the memory card connector.

[0166] In such Figure 10b In another example shown, the memory controller 706 and multiple memories 400 can be integrated into a solid-state drive (SSD) 806. The solid-state drive 806 may also include a connection between the solid-state drive 806 and a host (e.g., ...). Figure 9 The solid-state drive connector 808 is coupled to the host 708 in the memory card 802. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0167] It is understood that the memory controller 706 can perform the read method as provided in any embodiment of this disclosure.

[0168] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0169] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0170] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0171] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0172] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0173] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A counting circuit, characterized by, The counting circuit comprises a clock source, a clock control unit and N output units; wherein N is a positive integer; an output end of the clock source is coupled to an input end of the clock control unit, a clock input end of a first output unit to a clock input end of an Mth output unit, for providing a clock signal; wherein M is a positive integer less than N; an input end of the clock control unit is further coupled to an output end of the first output unit to an output end of the Mth output unit; an output end of the clock control unit is coupled to a clock input end of an M+1th output unit to a clock input end of an Nth output unit; the clock control unit is configured to generate a clock control signal according to the received clock signal and output values of the first output unit to the Mth output unit, and output the clock control signal to clock input ends of the M+1th output unit to the Nth output unit; wherein the clock control signal has first and second signal values with different signal values; the M+1th output unit to the Nth output unit is configured to latch when the received clock control signal switches from the second signal value to the first signal value; the M+1th output unit to the Nth output unit is further configured to keep the current state value unchanged when the received clock control signal is the second signal value.

2. The counting circuit of claim 1, wherein the clock control unit is specifically configured to generate the clock control signal with the first signal value when a rising edge of the received clock signal and the output values of the first output unit to the Mth output unit are all logic high levels; the clock control unit is further specifically configured to generate the clock control signal with the second signal value when a rising edge of the received clock signal and the output values of the first output unit to the Mth output unit have at least one logic low level.

3. A counting circuit according to claim 1 or 2, characterised in that, The clock control unit comprises an inverter, a first logic circuit, an enable flip-flop and a second logic circuit; wherein an input end of the inverter is coupled to an output end of the clock source, and an output end of the inverter is coupled to a clock input end of the enable flip-flop; input ends of the first logic circuit are coupled to output ends of the first output unit to the Mth output unit, and an output end of the first logic circuit is coupled to a data input end of the enable flip-flop; an output end of the enable flip-flop is coupled to a first input end of the second logic circuit; a second input end of the second logic circuit is coupled to an output end of the clock source, and output ends of the M+1th output unit to the Nth output unit are coupled to clock input ends of the M+1th output unit to the Nth output unit; the inverter is configured to output an inverted clock signal according to the received clock signal; The first logic circuit is configured to generate a first logic signal when outputs of the first output unit to the Mth output unit are all logic high. The first logic circuit is further configured to generate a second logic signal having a signal value different from the first logic signal when at least one of the outputs of the first output unit to the Mth output unit is logic low. The enable flip-flop is configured to generate a first enable signal according to the first logic signal received at a rising edge of the inverted clock signal. The enable flip-flop is further configured to generate a second enable signal having a signal value different from the first enable signal according to the second logic signal received at the rising edge of the inverted clock signal. The second logic circuit is configured to generate the clock control signal having the first signal value according to the first enable signal received at a rising edge of the clock signal. The second logic circuit is further configured to generate the clock control signal having the second signal value according to the second enable signal received at the rising edge of the clock signal.

4. The counting circuit of claim 3, wherein The first logic circuit comprises a first AND gate. The second logic circuit comprises a second AND gate.

5. The counting circuit of claim 1, wherein, The output unit comprises a flip-flop.

6. The counting circuit of claim 5, wherein, The flip-flop comprises a D-type flip-flop.

7. The counting circuit of claim 1, wherein, The counting circuit further comprises: a summer, inputs of the summer being coupled to outputs of the N output units respectively, and outputs of the summer being coupled to inputs of the N output units respectively.

8. The counting circuit of claim 7, wherein, The summer comprises N summation units. An input of a kth summation unit is coupled to outputs of the first output unit to the kth output unit. An output of the kth summation unit is coupled to an input of the kth output unit; wherein k is a positive integer less than or equal to N.

9. A memory device, comprising: It comprises: a memory cell array comprising a plurality of memory cell rows; a peripheral circuit coupled to the memory cell array, comprising the counting circuit of any one of claims 1 to 8.

10. A storage system, characterized by It comprises: the memory device of claim 9; and a memory controller coupled to the memory device and configured to control the memory device. ​

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