Integral type A / D converter and semiconductor device

Abstract

To provide an integral A / D converter in which a phase division circuit for generating a high-speed signal by appropriately combining a counter code signal is disposed at an appropriate interval and locally in a column, and which is capable of operating faster than a frequency of the counter code signal.SOLUTION: An integral A / D converter comprises a global counter which outputs a counter code signal including a multi-phase signal. The integral A / D converter also comprises: a ramp wave generation circuit which outputs a ramp wave voltage; a comparator which compares the ramp wave voltage with a pixel voltage; and a column circuit including a latch circuit which latches the counter code signal in output inversion timing of the comparator. For each column circuit, a latch circuit output value is defined as a digital conversion output value. A phase division circuit is further provided for outputting a phase division signal dividing a phase of the counter code signal to the latch circuit as an LSB of the digital conversion output value of the integral A / D converter. The phase division circuits are disposed with respect to a plurality of column circuits and the LSB is shared by a plurality of phase division circuits.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an integral A / D converter and a semiconductor device, and relates to a technique that is effective when applied to a configuration for locally generating a signal faster than a polyphase counter code signal from a globally transmitted polyphase counter code signal, for example. [Background technology]

[0002] The counter code signal of the global counter type A / D converter in the image sensor in Patent Document 1 is generated in the global counter and distributed to latch sections arranged in several thousand columns. The A / D converter in each column latches the counter code signal at the timing when the comparison result signal between the input analog signal and the RAMP wave is inverted, and converts the analog signal into a digital signal. Since the counter counts for each cycle of the global counter clock, the cycle of the global counter clock corresponds to the time of 1 LSB signal of the A / D converter.

[0003] The counter code signal in Patent Document 1 is achieved by combining counter code signals with the upper bits as Gray code and the lower bits as Johnson counter code, thereby lowering the frequency of the counter code signal. For example, the frequency of the counter code signal for a 1 GHz A / D converter is 125 MHz. As a result, the A / D converter is designed to enable long-distance, high-load transmission. However, because the Johnson counter code is used, the number of signals increases by one, and 14 counter code signals are used, resulting in a 2 13 Since it can represent 8192 different numbers, the A / D converter is a 13-bit A / D converter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-92091 A Summary of the Invention [Problem to be solved by the invention]

[0005] Despite the circuit innovations mentioned above, electronic devices using image sensors, etc., are becoming more and more sophisticated, and the specifications required for the A / D converter mounted on the sensor chip, which is the most important element, are also becoming more advanced. For example, there is a demand for a faster frequency of the counter code signal to realize a faster frame rate and multiple sampling to reduce noise.

[0006] On the other hand, in order to increase the number of pixels, it is required to extend the transmission distance of the counter code signal. Also, in order to increase the number of gradations and improve image quality, it is required to increase the number of bits of the counter code signal. Also, in order to prevent images with streaks and images with uneven image quality, it is required that the delay amount of the counter code signal be highly adjusted. However, if the frequency of the counter code signal is increased in the above-mentioned circuit configuration, it is necessary to shorten the transmission distance and reduce the number of conversion bits of the A / D converter, which creates a problem that it is not possible to meet the required specifications.

[0007] The present invention has been made in view of the above, and one of its objects is to provide a semiconductor device capable of operating at a speed higher than the frequency of the counter code signals by locally arranging phase division circuits in a column at appropriate intervals, the phase division circuits appropriately combining the counter code signals to generate a high-speed signal. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief outline of a representative invention among the inventions disclosed in the present application is as follows: A representative integral A / D converter includes a global counter that outputs a counter code signal including a multiphase signal, a ramp generating circuit that outputs a ramp voltage whose voltage value changes linearly with time, a comparator that compares the ramp voltage with a pixel voltage generated in a pixel, and a column circuit including a latch circuit that latches the counter code signal at the timing when the output of the comparator is inverted, and the integral A / D converter is an integral A / D converter in which the output value of the latch circuit is a digital conversion output value for each column circuit, and includes a phase division circuit that receives the counter code signal as an input, generates a phase division signal that divides the phase of the counter code signal, and outputs the phase division signal to the latch circuit as an LSB of the digital conversion output value of the integral A / D converter, the global counter is shared with a predetermined number of column circuits, and phase division circuits are arranged for a number of column circuits that is less than the predetermined number, and the LSB is shared by the multiple phase division circuits. Effect of the Invention

[0009] According to one embodiment, by placing phase division circuits locally at appropriate intervals within the column, which appropriately combine the counter code signals to generate high-speed signals, it is possible to operate at a speed faster than the frequency of the counter code signals. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram for explaining an overview of the operation of an A / D converter according to a first embodiment. [Diagram 2] 2 is a block diagram illustrating a specific configuration of an A / D converter according to the first embodiment. FIG. [Diagram 3] 4 is a flowchart showing an example of the operation of the A / D converter according to the first embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a phase division circuit according to the first embodiment. [Diagram 5] 5 is a timing chart of an example of the phase division circuit in FIG. 4; [Figure 6] 4 is a timing chart showing an example of an output bit pattern of the A / D converter according to the first embodiment. [Figure 7] 5A to 5C are diagrams illustrating an example of a simulation result of a Johnson counter code signal and a phase division signal generated by a phase division circuit according to the first embodiment. [Figure 8] FIG. 4 is a block diagram showing another example of the phase division circuit according to the first embodiment. [Figure 9] 9 is an example of a timing chart of the phase division circuit in FIG. 8. [Figure 10] FIG. 11 is a block diagram of an example of a phase division circuit according to a second embodiment. [Figure 11] 11 is a timing chart of an example of the phase division circuit in FIG. 10; [Figure 12] 10 is a timing chart showing an example of an output bit pattern of the A / D converter according to the second embodiment. [Figure 13] FIG. 11 is a block diagram of an example of a phase division circuit according to a third embodiment. [Figure 14] 11 is a timing chart showing an example of an output bit pattern of the A / D converter according to the third embodiment. [Figure 15] 11 is a timing chart showing a comparative example of output bit patterns of the A / D converter according to the comparative example and the present embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or complete modification, detail, supplementary explanation, etc. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number, etc.

[0012] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] Furthermore, although not particularly limited, the circuit elements constituting each functional block of the embodiment are formed on a semiconductor substrate such as single crystal silicon by known integrated circuit technology such as CMOS (complementary metal oxide semiconductor).

[0014] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. In all drawings for explaining the embodiment, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation, and may differ from the actual ratios.

[0015] (Embodiment 1) <Conceptual configuration of A / D converter in semiconductor device> 1 is a block diagram for explaining an outline of the operation of the A / D converter according to the first embodiment. The integral A / D converter 1000a includes a global counter 200, a ramp generator circuit 300, a comparator 400a, a latch circuit 510a, a latch circuit 540a, a latch circuit 600a, and a phase division circuit 100a. The latch circuit 600a is a latch circuit for the LSB. The latch circuit 510a and the latch circuit 540a are latch circuits for the middle bits above the LSB. Although the latch circuit for the higher bits is not shown, a Gray code signal GR is output from the global counter 200 as a signal for the higher bits.

[0016] A pixel output voltage level of a pixel of an imaging element such as an image sensor (not shown) is input as an electric signal Sin to a non-inverting input of the comparator 400a. A comparison voltage output from the ramp wave generating circuit 300 is input to an inverting input of the comparator 400a. At a latch timing when the pixel output voltage level of the imaging element and the comparison voltage match, the output level of the comparator 400a rises, and the counter code signal input to the latch circuit is latched and output in parallel as an output signal Sout. The latched counter code signal is the logic level of the latch timing of counter code signals such as counter code signal 1 and counter code signal 2 shown in FIG. 1. The logic level indicates the logic level of each bit value of the digital output value of the integral A / D converter 1000a.

[0017] It is preferable that the comparison voltage output from the ramp generating circuit 300 is a voltage that increases linearly with respect to time. Also, it is preferable that the noise level of the comparison voltage is smaller than the decision level of the LSB signal of the integral type A / D converter 1000a.

[0018] It is preferable that the most significant bit of the global counter 200 outputs a Gray code, the middle bit outputs a Johnson counter code, and the LSB signal is a locally multiplied signal generated from the Johnson counter code. For example, when the counter code signal 1 shown in FIG. 1 is a Johnson counter code and the counter code signal 2 is also a Johnson counter code, the LSB signal is a locally multiplied signal generated from the Johnson counter code. A Gray code (not shown) is output as the most significant bit. Details of the phase splitting circuit 100a will be described later. The locally multiplied signal means a phase split signal output from the phase splitting circuit, as will be described later.

[0019] The latch circuit 510a that latches the middle-higher bits has a function of latching the counter code signal 1 corresponding to the middle-higher bits of the integral A / D converter 1000a output from the global counter 200 at the timing when the input level of the comparator 400a becomes equal. For example, the counter code signal 1 is a Johnson counter code signal. The latch circuit 510a outputs the logic level of the latched counter code signal 1 as the logic level of the middle-higher bits of the integral A / D converter 1000a.

[0020] The latch circuit 520a, which latches the middle and lower bits, has a function of latching the counter code signal 2 corresponding to the middle and lower bits of the integral A / D converter 1000a output from the global counter 200 at the timing when the input level of the comparator 400a becomes equal. For example, the counter code signal 2 is also a Johnson counter code signal. The latch circuit 520a outputs the logic level of the latched counter code signal 2 as the logic level of the middle and lower bits of the integral A / D converter 1000a.

[0021] The phase division circuit 100a outputs a high-speed phase division signal that changes at the intermediate phase between the counter code signal 1 and the counter code signal 2 output from the global counter 200. Moreover, by combining the counter code signal 1 and the counter code signal 2 into a multi-phase clock signal that is a relatively low-speed signal based on a Johnson counter code signal, the counter code signal 1 and the counter code signal 2 can be made to be signals that can withstand relatively long-distance and high-load transmission. Moreover, by arranging the phase division circuit 100a adjacent to a circuit that requires high-speed operation, it becomes possible to supply a signal at high speed with little delay.

[0022] The counter code signal 1 and the counter code signal 2 are relatively low-speed multi-phase clock signals, and therefore can withstand relatively long-distance and high-load transmission. However, the phase division signal is a high-frequency signal compared to the counter code signal 1 and the counter code signal 2, and therefore is preferably transmitted over a short distance. For example, when the phase division signal is in the gigahertz band, it is desirable to arrange the phase division circuit 100a every one to several hundred column circuits, preferably every several tens to several hundred column circuits, from the global counter 200.

[0023] The latch circuit 600a that latches the LSB signal has a function of latching the phase division signal output from the phase division circuit 100a at the timing when the input levels of the comparator 400a become equal. The latch circuit 600a outputs the logic level of the latched phase division signal as the logic level of the LSB signal of the integral type A / D converter 1000a.

[0024] According to such a circuit example, a phase splitter circuit that generates a signal faster than a global counter code signal that determines the operating frequency of the semiconductor device is disposed in the column. Therefore, the semiconductor device can operate at a speed faster than the global counter code signal. Furthermore, since a plurality of relatively slow Johnson counter code signals can be used as the input of the phase splitter circuit, it is possible to endure long-distance transmission and high-load transmission. Furthermore, since the phase split signal of the phase splitter circuit outputs a high-speed signal that changes at the intermediate phase of the Johnson counter code signal, which is a multi-phase clock, it is possible to reduce the probability of miscounting. Furthermore, since the phase splitter circuit can be designed to be disposed adjacent to a circuit that requires high-speed operation as necessary, it is possible to supply the phase split signal over a short distance and with a low load.

[0025] <Specific Configuration of A / D Converter of Semiconductor Device> Fig. 2 is a block diagram for explaining a part of a specific configuration of the A / D converter according to embodiment 1. That is, Fig. 2 shows an example of a configuration in which the upper bits of the global counter 200 output a 9-bit Gray code signal, the middle bits output a 4-bit Johnson counter code signal, and the LSB signal of the A / D converter is generated from the 4-bit Johnson counter code signal.

[0026] A clock signal CLK having a constant period is input to the input of the global counter 200. The frequency of the clock signal CLK may be any frequency, but it does not preclude it from being a frequency in the gigahertz band. The clock signal CLK is converted into a Johnson counter code signal by the Johnson counter 210. As an example, when the clock signal CLK is 810 MHz, the Johnson counter code signal can be 202.5 MHz.

[0027] The global counter 200 includes a Johnson counter 210 , a binary counter 220 , a Gray code counter 230 , and a synchronization unit 240 .

[0028] The Johnson counter 210 receives a clock signal CLK and outputs a four-phase Johnson counter code signal, a Johnson counter code signal <0> Johnson Counter Code Signal <3> Generates a Johnson counter code signal. <0> and Johnson Counter Code Signal <1> The two clock signals CLK are out of phase with each other, and the Johnson counter code signal <1> and Johnson Counter Code Signal <2> The two clock signals CLK are out of phase with each other. Also, the Johnson counter code signal <0> and Johnson Counter Code Signal <2> This means that the clock signal CLK is out of phase with respect to four signals. Details will be described with reference to FIG.

[0029] The binary counter 220 receives a Johnson counter code signal corresponding to the fourth bit of the A / D converter output from the Johnson counter 210, for example, a Johnson counter code signal <3> A binary code signal is generated using the above as an input. A signal corresponding to the LSB signal of the A / D converter is generated in a phase division circuit 100a, which will be described later.

[0030] The Gray code counter 230 receives the binary code signal output from the binary counter 220 and outputs a nine-phase Gray code signal, for example, a Gray code signal <0> Gray code signal from <8> For example, the Gray code signal <8> corresponds to the MSB signal of the A / D converter.

[0031] The synchronization unit 240 synchronizes with the clock signal CLK input to the global counter 200 and generates a Gray code signal <0> Gray code signal from <8> and Johnson counter code signal <0> Johnson Counter Code Signal <3> The presence of the synchronization unit 240 enables the output value of the A / D converter to be accurately output in synchronization with the clock signal CLK.

[0032] The latch circuit 501a receives a Gray code signal <0> is input, and the latch circuit 509a receives the Gray code signal <8> That is, each of the latch circuits 501a to 509a receives the Gray code signal <0> Gray code signal from <8> Then, when the latch signal La rises, the latch circuit inputs the Gray code signal <0> Gray code signal from <8> The logic levels of the above signals are latched. The latched logic levels correspond to the logic levels of the upper 9 bits of the A / D converter, and become the output of the A / D converter. The latch signal La is the comparison result signal CMP, which is the output signal of the comparator 400a in FIG. 1, and FIG. 2 shows that the comparison result signal CMP, which is the latch signal La, is transmitted from the comparator (the comparator 400a in FIG. 1).

[0033] The latch circuit 510a receives the Johnson counter code signal <0> is input, and the latch circuit 520a receives the Johnson counter code signal <1> is input, and the latch circuit 530a receives the Johnson counter code signal <2> The latch circuit 540a receives the Johnson counter code signal <3> is input. Johnson counter code signal <0> Johnson Counter Code Signal <4> The latch circuits 510a to 540a receive the Johnson counter code signals La when the latch signal La rises. <0> Johnson Counter Code Signal <3> The latch circuit 510a latches the logic levels of the four middle bits immediately above the LSB of the A / D converter. The latched logic levels correspond to the logic levels of the four middle bits immediately above the LSB of the A / D converter, and become the output of the A / D converter. As described above, the latch signal La is also input to the latch circuit 510a. The latch signal La is the comparison result signal CMP, which is the output signal of the comparator 400a in FIG. 1, and FIG. 2 shows that the comparison result signal CMP, which is the latch signal La, is transmitted from the comparator (the comparator 400a in FIG. 1).

[0034] The phase splitter circuit 100a generates a Johnson counter code signal <0> Johnson Counter Code Signal <3> and generate a phase division signal whose phase changes at the intermediate position between adjacent Johnson counter code signals. For example, the phase division signal is a Johnson counter code signal <0> and Johnson Counter Code Signal <1> The phase changes at approximately the midpoint of the phase change position of the Johnson counter code signal. <1> and Johnson Counter Code Signal <2> The phase changes at approximately the midpoint of the phase change position of the Johnson counter code signal. <2> and Johnson Counter Code Signal <3> The phase changes at approximately the midpoint of the phase change position of the Johnson counter code signal. <3> and Johnson Counter Code Signal <0> The phase changes at approximately the middle of the phase change positions of the phase division circuit 100. An example of the phase division circuit 100a is a synchronous mirror delay (SMD) and a phase interpolator (PI).

[0035] The phase division signal is input to the latch circuit 600a, and when the latch signal La rises, the logic level of the phase division signal is latched. The latched logic level corresponds to the logic level of the LSB of the A / D converter, and becomes the output of the A / D converter. As described above, the latch signal La is also input to the latch circuit 600a. The latch signal La is the comparison result signal CMP, which is the output signal of the comparator 400a in FIG. 1, and FIG. 2 shows that the comparison result signal CMP, which is the latch signal La, is transmitted from the comparator (the comparator 400a in FIG. 1).

[0036] As described above and below, by placing an LSB phase division circuit every tens to hundreds of columns, the phase division signal, which is an LSB signal, can be transmitted over a short distance with low load and low delay.

[0037] Also, as is clear from FIG. 2, the counter code signal that is not input to the phase division circuit 100a and corresponds to the output value of the latch circuit which is the most significant bit of the digital conversion output value of the integral A / D converter is a Gray code signal.

[0038] <An example of the operation flow of the A / D converter of the semiconductor device> Fig. 3 is a flowchart showing an example of the operation of the A / D converter according to embodiment 1. The outline of the operation in Fig. 3 is a summary of the contents described in Figs.

[0039] In step S301, the arrangement of the phase splitter circuit is determined. The phase splitter circuit generates an LSB signal of an A / D converter that A / D converts a voltage generated in a pixel formed by a photodiode of the semiconductor device. The pixel may be, for example, a part of an image sensor formed in the semiconductor device. The phase splitter circuit is desirably arranged near a circuit part in the ADC that requires high-speed operation. In addition, the phase splitter circuit does not need to be arranged one-to-one with respect to the ADC of every column, and the effect of this embodiment can be achieved by arranging one phase splitter circuit at intervals of several tens to several hundreds of columns.

[0040] In step S302, the A / D converter inputs a clock signal CLK to the global counter. Note that the counter code signal output from the global counter is a signal that is counted up, so the count value proportional to the time until the values ​​of the signals input to the comparator become the same is the output value of the integral type A / D converter in this embodiment.

[0041] In step S303, the A / D converter uses a code such as a Gray code that changes few bits when changing to an adjacent value for the upper bits of the output value of the A / D converter. For example, the Gray code has the characteristic that only one bit always changes when changing from a certain value to an adjacent value, and the Hamming distance between adjacent codes is always 1. Therefore, even if there is a variation between the bits of the Gray code due to the influence of wiring delay or the like, the Gray code only causes a deviation of about one code, so that it is possible to reduce the influence of the upper bits. On the other hand, for the middle bits of the high frequency, the A / D converter uses a code such as a Johnson counter code that changes the code at a slower speed to reduce power consumption and can be realized with a simple circuit configuration such as a flip-flip. In the above case, the lower bits, excluding the upper bits and middle bits, from the output bits of the A / D converter indicate the LSB.

[0042] In step S304, the global counter synchronizes the counter code signal of the upper bit and the counter code signal of the middle bit, which are different counter code signals. For example, the global counter outputs the Gray code signal of the upper bit and the Johnson counter code signal of the middle bit in synchronization with the clock signal CLK input to the global counter 200. The Johnson counter code signal of the middle bit is a Johnson counter code signal <0> Johnson Counter Code Signal <3> Johnson counter code signal up to <0> Johnson Counter Code Signal <3> The Johnson counter code signals up to have a duty ratio of 1 / 2 and are out of phase with each other by two clock signals CLK.

[0043] In step S305, the phase splitter circuit 100a outputs the Johnson counter code signal <0> Johnson Counter Code Signal <3> is input, and a phase-divided signal is generated whose phase changes at the intermediate position between the phase changes of adjacent Johnson counter code signals. In other words, the phase-divided signal has a frequency twice that of the 4-bit Johnson counter code signal.

[0044] In step S306, the A / D converter sets the phase-divided signal, which is the signal with the highest frequency, as the LSB of the A / D converter. The phase-divided signal outputs a high-speed signal that changes at the intermediate phase of the Johnson counter code signal, which is a multi-phase clock, so that it is possible to reduce the probability of miscounting. In addition, the phase-divided circuit can be designed to be placed adjacent to a circuit that requires high-speed operation as necessary, so that it is possible to supply the phase-divided signal over a short distance with a low load.

[0045] In step S307, the A / D converter outputs the most significant bits of the Gray code or the like, the middle bits of the Johnson counter code or the like, and the LSB of the phase division signal of the phase division circuit 100a. This operation makes it possible to increase the execution speed of the A / D converter by more than twice the previous execution speed without increasing the frequency of the clock signal CLK input to the global counter 200. In addition, the execution speed of the A / D converter can be increased by more than twice the previous execution speed without increasing the frequency of the counter code signal output from the global counter 200 and transmitted over a long distance.

[0046] That is, the A / D converter according to this embodiment can meet user demands such as an improvement in the frame rate of an image sensor (not shown) connected to the input of the A / D converter, an increase in the number of pixels, and higher image quality. Furthermore, the A / D converter can be made faster without increasing the chip area of ​​the A / D converter or increasing assembly costs.

[0047] <An example of the phase splitter circuit 100a according to the first embodiment> 4 is a block diagram illustrating an example of a phase splitting circuit according to the first embodiment. The phase splitting circuit 100a according to the first embodiment splits four Johnson counter code signals having different phases. <0> from <3> The phase splitter circuit 100a functions as an SMD circuit that receives the Johnson counter code signal <0> A differentiator 110a[0] generates a pulse at the rising and falling edges of the Johnson counter code signal <1> The phase splitter circuit 100a also includes a differentiator 110a[1] that generates a pulse at the rising edge and the falling edge of the Johnson counter code signal <2> A differential 110a[2] generates a pulse at the rising and falling edges of the Johnson counter code signal <3> The Johnson counter code signal includes a differentiator 110a[3] that generates a pulse at the rising and falling edges of <0> The pulse signal is sig0, and the Johnson counter code signal is <1> The pulse signal is sig1, and the Johnson counter code signal is <2> The pulse signal is sig2, the Johnson counter code signal <3> The pulse signal is sig3.

[0048] The pulse signal sig0 and the pulse signal sig1 are input to the mirror delay unit a[0], and the mirror delay unit a[0] generates a pre-out signal [0] that rises at the intermediate phase between the pulse signal sig1 and the pulse signal sig2. That is, the mirror delay unit a[0] generates a pre-out signal [0] that rises at the intermediate phase between the pulse signal sig0 and the pulse signal sig1 (t diff ) phase difference (t diff The pre-out signal [0] is output with a delay of 1 / 2 from the rising edge of the pulse signal sig1.

[0049] In addition, the mirror delay unit a[1] receives the pulse signal sig1 and the pulse signal sig2, and generates a pre-out signal [1] that rises at the intermediate phase between the pulse signal sig2 and the pulse signal sig3. That is, the mirror delay unit a[1] generates a pre-out signal [1] that rises at the intermediate phase between the pulse signal sig1 and the pulse signal sig2 (t diff ) phase difference (t diffThe mirror delay unit a[1] outputs the pre-out signal [1] with a delay of 1 / 2 from the rising edge of the pulse signal sig2. Note that the internal circuit of the mirror delay unit a[1] is the same as that of the mirror delay unit a[0], so a detailed diagram is omitted.

[0050] Furthermore, the mirror delay unit a[2] receives the pulse signal sig2 and the pulse signal sig3 and generates a pre-out signal [2] that rises at the intermediate phase between the pulse signal sig3 and the pulse signal sig0. That is, the mirror delay unit a[2] generates a pre-out signal [2] that rises at the intermediate phase between the pulse signal sig2 and the pulse signal sig3 (t diff ) phase difference (t diff The mirror delay unit a[1] outputs the pre-out signal [2] with a delay of 1 / 2 from the rising edge of the pulse signal sig3. Note that the internal circuit of the mirror delay unit a[1] is the same as that of the mirror delay unit a[0], so a detailed diagram is omitted.

[0051] Furthermore, the mirror delay unit a[3] receives the pulse signal sig3 and the pulse signal sig0 and generates a pre-out signal [3] that rises at the intermediate phase between the pulse signal sig0 and the pulse signal sig1. That is, the mirror delay unit a[3] generates a pre-out signal [3] that rises at the intermediate phase between the pulse signal sig3 and the pulse signal sig0 (t diff ) phase difference (t diff The mirror delay unit a[3] outputs the pre-out signal [3] with a delay of 1 / 2 from the falling edge of the pulse signal sig0. Note that the internal circuit of the mirror delay unit a[3] is the same as that of the mirror delay unit a[0], so a detailed diagram is omitted.

[0052] <<An example of a mirror delay unit>> The mirror delay unit a[0] shown in FIG. 4 delays the delay signal C[0] to the delay signal C[n] by 2×clock signal CLK=t diff The mirror delay unit a[0] includes a front mirror delay line 130a[0] that generates a delay time of t diffA rear mirror delay line 150a[0] is provided to generate a delay time of 1 / 2. In addition, a Johnson counter code signal input to the front mirror delay line 130a[0] is provided.<n―1> A delayed signal C[n] of (n: natural number) and the adjacent Johnson counter code signal <n>The delay circuit 120a[0] includes a delay-difference detection circuit 140a[0] for detecting synchronization with the delay signal C[n] input to the delay-difference detection circuit 140a[0]. The delay circuit 120a[0] further includes a delay circuit 120a[0] for adjusting the timing of the delay signal C[n] input to the delay-difference detection circuit 140a[0].

[0053] The pulse signal sig0 generated at the rising and falling edges of the Johnson counter code signal [0] input to the mirror delay unit a[0] is transmitted through the front mirror delay line 130a[0] for t diff The pulse signal sig1 input to the delay difference detection circuit 140a[0] is delayed by t diff Therefore, a new pulse signal is formed by the pulse signal sig1 and the delayed signal C[n] input to the delay difference detection circuit 140a[0], and a pulse signal (t diff A delayed pre-out signal [0] of 1 / 2 is generated.

[0054] <<An example of a mixer>> The mixer 160a inputs the pre-out signal [0], the pre-out signal [1], the pre-out signal [2], and the pre-out signal [3], and outputs a phase division signal OUT whose phase is inverted at the midpoint between the phases of the adjacent pre-out signals. Therefore, the mixer 160a inverts the signal level at the rising edge of the pre-out signal [0] and maintains the inverted signal level, and returns the inverted signal level to the original signal level at the rising edge of the pre-out signal [1] and maintains the original signal level. Furthermore, the mixer 160a inverts the signal level at the rising edge of the pre-out signal [2] and maintains the inverted signal level, and returns the inverted signal level to the original signal level at the rising edge of the pre-out signal [3] and maintains the original signal level. The mixer 160a repeats the above operations, and outputs the repeated signal levels as the phase division signal OUT.

[0055] <An example of a timing chart of the phase division circuit according to the first embodiment> 5 is a timing chart of an example of the phase division circuit shown in FIG. 4. Johnson counter code signal [0], Johnson counter code signal [1], Johnson counter code signal [2], and Johnson counter code signal [3] are t diff In addition, one Johnson counter code signal has a half cycle of 4t diff The pulse signal sig0 is a pulse signal that starts from the rising and falling edges of the Johnson counter code signal [0] and continues for approximately (t diff The pulse signal sig1 has a high level period of about (t diff The delay signal C[n] is a pulse signal having a high level period of t / 2. The delay signal C[n] is a pulse signal having a high level period of t diff A delayed signal that starts from the rising edge and is approximately (t diff 4, the pulse signal sig1 and the delayed signal C[n] are AND-connected, and the Johnson counter code signal [1] to (t diff / 2) Generate a delayed pre-out signal PREOUT[0].

[0056] Although omitted in FIG. 5, the pulse signal sig2 and the delayed signal C[n] of the pulse signal sig1 are AND-connected. The AND-connected signal is then multiplied by the Johnson counter code signal [2] (t diff 5, the pulse signal sig3 and the delayed signal C[n] of the pulse signal sig2 are AND-connected. The AND-connected signal is then multiplied by the Johnson counter code signal [3] (t diff 5, the delayed signal C[n] of the pulse signal sig0 and the delayed signal C[n] of the pulse signal sig3 are AND-connected. The AND-connected signal is then delayed by the rear mirror delay line 150a[3] from the falling edge of the Johnson counter code signal [0] by (t diff / 2) A delayed pre-out signal PREOUT[3] is generated.

[0057] The phase division signal OUT in FIG. 5 has an initial state of "0", but transitions to a high level at the rising edge of the pre-out signal PREOUT[0], then maintains the high level, transitions to a low level at the rising edge of the pre-out signal PREOUT[1], and then maintains the low level. Then, transitions to a high level at the rising edge of the pre-out signal PREOUT[2], then maintains the high level, transitions to a low level at the rising edge of the pre-out signal PREOUT[3], and then maintains the low level. Thereafter, the phase division signal OUT repeats the above operation. That is, the phase division signal of the phase division circuit outputs a high-speed signal that changes at the intermediate phase of the Johnson counter code signal, which is a multi-phase clock, so that it is possible to reduce the probability of miscounting. In addition, the phase division circuit can be designed to be placed adjacent to a circuit that requires high-speed operation as necessary, so that it is possible to supply the phase division signal over a short distance and with a low load.

[0058] Therefore, it is preferable that the phase splitter circuit 100a is disposed in a column circuit that operates at a higher frequency than the operating frequency of the adjacent column circuit. In addition, the column circuit that operates at a higher frequency may not be a single column circuit, but may be multiple adjacent or neighboring column circuits, so that the phase splitter circuit 100a may be disposed within one to several hundred column circuits, preferably several tens to several hundreds of column circuits, from the corresponding column circuit.

[0059] <Example of Output Bit Pattern of A / D Converter According to First Embodiment> 6 is a timing chart showing an example of an output bit pattern of the A / D converter according to the first embodiment. That is, FIG. 6 shows the output bits, which will be described below, of the integral type A / D converter 1000a according to the first embodiment. That is, the output bits are a Johnson counter code signal JC that outputs the upper four middle bits from the LSB. <0> Johnson Counter Code Signal JC <3> , the most significant bit is 1 bit of the Gray code signal <3> , and a phase division signal OUT of the LSB signal. The LSB signal may also be called a local multiplication signal. That is, the counter code signal input to the phase division circuit 100a is a Johnson counter code signal, and adjacent Johnson counter code signals have a 1 / 8 cycle phase difference and a duty of 50%. Four Johnson counter code signals with 1 / 8 cycle phase differences are input in parallel to the phase division circuit 100a.

[0060] 6 indicates the number of clocks of the clock signal CLK input to the global counter 200. Therefore, when the counter value is "0", there is no input to the integral type A / D converter 1000a, so the phase division signal OUT="0" and the Johnson counter code signal JC <0> Johnson Counter Code Signal JC <3> = "0" and other bits = "0". Every time the counter value is incremented by two, a phase-divided signal is generated whose phase changes at the intermediate position where the phase of the adjacent Johnson counter code signal changes. In other words, the phase-divided signal is a signal having twice the frequency of the edge change of the Johnson counter code signal. In this way, the phase-divided signal outputs a high-speed signal that changes at the intermediate phase of the Johnson counter code signal, which is a multi-phase clock, making it possible to reduce the probability of miscounting. In addition, the phase-divided circuit can be designed to be placed adjacent to a circuit that requires high-speed operation as necessary, making it possible to supply the phase-divided signal over a short distance with a low load.

[0061] According to such an operation, the execution speed of the A / D converter can be more than twice as fast as the previous execution speed without increasing the frequency of the clock signal CLK input to the global counter 200. In addition, the execution speed of the A / D converter can be more than twice as fast as the previous execution speed without increasing the frequency of the counter code signal output from the global counter 200 and transmitted over a long distance. That is, the A / D converter according to this embodiment can meet user demands such as an improvement in the frame rate of an image sensor (not shown) connected to the input of the A / D converter, an increase in the number of pixels, and high image quality. In addition, the A / D converter can be made faster without increasing the chip area of ​​the A / D converter and the assembly cost.

[0062] <An example of Johnson counter code and phase division circuit simulation results> 7 is a diagram showing an example of a simulation result of the Johnson counter code signal and the phase division signal generated by the phase division circuit according to the first embodiment. Since the Johnson counter code signal is operated at approximately 125 MHz, the conversion time of the A / D converter operates in 2 n seconds using a four-phase Johnson counter code signal when the phase division signal is not used as the LSB signal. However, as can be seen from FIG. 7, it is possible to use the phase division signal generated by the phase division circuit as the LSB signal of the A / D converter. In this case, the conversion time of the A / D converter becomes 1 n seconds, and the execution speed of the A / D converter can be doubled from the previous execution speed.

[0063] <Another Example of the Phase Splitter Circuit According to the First Embodiment> 8 is a block diagram showing another example of the phase splitter circuit according to the first embodiment. The phase splitter circuit 100b according to the first embodiment splits four Johnson counter code signals having different phases, similarly to the phase splitter circuit 100a. <0> from <3> The phase splitter circuit 100b functions as an SMD circuit that receives the input of the delay difference detection circuit 140b[0] and outputs the pre-out signal PREOUT in synchronization with the falling edge of the Johnson counter code signal.

[0064] Since the configuration other than the D-type flip-flop is the same in the phase splitter circuit 100a and the phase splitter circuit 100b, the description will be omitted to avoid duplication. First, the mirror delay unit b[0] will be described. Johnson counter code signal <0> The delayed signal C[n] of the pulse signal sig0 is input to the clock terminal of the D-type flip-flop DFFbn[0]. The rising edge of the delayed signal C[n] (delay time (t diff ) + the delay time of the delay circuit 120b[0]), the pulse signal sig1 at the data input terminal is in a high state, so the output terminal signal Q[n] of the D-type flip-flop DFFbn[0] is in a high state. Also, immediately after the output terminal signal Q[n] becomes a high state, the Johnson counter code signal <1> Since the pulse signal sig1 is in a low state, the output of the AND circuit ANDbn[0] is also in a low state, and the phase division signal PREOUT[0] also outputs a low-level signal.

[0065] Johnson Counter Code Signal <0> The timing at which the pulse signal sig0, which is generated at the falling edge of t , is input to the AND circuit ANDbn[0] is also the timing at which the output terminal signal Q[n] of the D-type flip-flop DFFbn[0] is in a high state. Therefore, the output of the AND circuit ANDbn[0] is also in a high state, and the phase division signal PREOUT[0] is also in a high state (t diff / 2) between the pulse signal sig0 and the pulse signal sig1, and then outputs a high-level signal. diff ) phase difference (t diff The pre-out signal [0] is output with a delay of 1 / 2 from the rising edge of the pulse signal sig0. In this case, the pulse signal sig0 is the Johnson counter code signal <0> It is generated at the falling edge of

[0066] In addition, the mirror delay unit b[1] receives the pulse signal sig1 and the pulse signal sig2 and generates a pre-out signal [1] that rises at the intermediate phase between the pulse signal sig1 and the pulse signal sig2. That is, the mirror delay unit [1] generates a pre-out signal [1] that rises at the intermediate phase between the pulse signal sig1 and the pulse signal sig2. diff ) phase difference (t diff The pre-out signal [1] is output with a delay of 1 / 2 from the rising edge of the pulse signal sig1. In this case, the pulse signal sig1 is a Johnson counter code signal <1> The internal circuit of the mirror delay unit b[1] is the same as that of the mirror delay unit b[0], so a detailed diagram is omitted.

[0067] Furthermore, the mirror delay unit b[2] receives the pulse signal sig2 and the pulse signal sig3 and generates a pre-out signal [2] that rises at the intermediate phase between the pulse signal sig2 and the pulse signal sig3. That is, the mirror delay unit b[2] generates a pre-out signal [2] that rises at the intermediate phase between the pulse signal sig2 and the pulse signal sig3. diff ) phase difference (t diff The pre-out signal [2] is output with a delay of 1 / 2 from the rising edge of the pulse signal sig2. In this case, the pulse signal sig2 is a Johnson counter code signal <2> The internal circuit of the mirror delay unit [1] is the same as that of the mirror delay unit [0], so a detailed diagram is omitted.

[0068] Furthermore, the mirror delay unit b[3] receives the pulse signal sig3 and the pulse signal sig0 and generates a pre-out signal [3] that rises at the intermediate phase between the pulse signal sig3 and the pulse signal sig0. That is, the mirror delay unit b[3] generates a pre-out signal [3] that rises at the intermediate phase between the pulse signal sig3 and the pulse signal sig0. diff ) phase difference (t diff The pre-out signal [3] is output with a delay of 1 / 2 from the rising edge of the pulse signal sig3. In this case, the pulse signal sig3 is a Johnson counter code signal <3> The internal circuit of the mirror delay unit b[3] is the same as that of the mirror delay unit b[0], so a detailed diagram is omitted.

[0069] <<An example of a mixer>> The mixer 160b inputs the pre-out signal [0], the pre-out signal [1], the pre-out signal [2], and the pre-out signal [3], and outputs a phase division signal OUT whose phase is inverted at the midpoint between the phases of the adjacent pre-out signals. Therefore, the mixer 160b inverts the signal level at the rising edge of the pre-out signal [0] and maintains the inverted signal level, and returns the inverted signal level to the original signal level at the rising edge of the pre-out signal [1] and maintains the original signal level. Furthermore, the mixer 160b inverts the signal level at the rising edge of the pre-out signal [2] and maintains the inverted signal level, and returns the inverted signal level to the original signal level at the rising edge of the pre-out signal [3] and maintains the original signal level. The mixer 160b repeats the above operations, and outputs the repeated signal levels as the phase division signal OUT.

[0070] <An example of a timing chart of another phase division circuit according to the first embodiment> Fig. 9 is an example of a timing chart of the phase division circuit according to Fig. 8. In Fig. 9, the Johnson counter code signal [0], the Johnson counter code signal [1], the Johnson counter code signal [2], and the Johnson counter code signal [3] are diff In addition, one Johnson counter code signal has a half cycle of 4t diff The pulse signal sig0 is a pulse signal that starts from the rising and falling edges of the Johnson counter code signal [0] and continues for approximately (t diff The pulse signal sig1 has a high level period of about (t diff The delay signal C[n] is a pulse signal having a high level period of t / 2. The delay signal C[n] is a pulse signal having a high level period of t diff and a delayed signal delayed by the delay time of delay circuit 120b[0]. Delayed signal C[0] is a delayed signal during transmission through front mirror delay line 130b[0]. The output terminal signal Q[n] of D-type flip-flop DFFbn[0] outputs the signal level of pulse signal sig1 input to the D terminal at the rising edge of delayed signal C[n]. Therefore, as shown in FIG. 9, the output terminal signal Q[n] continues to output a high state, which is the signal level of pulse signal sig1, at the rising edge of delayed signal C[n]. The pre-out signal[0] is the sum signal of output terminal signal Q[n] and pulse signal sig0 amplified by rear mirror delay line 150b[0] (t diff / 2) A delayed signal.

[0071] The phase division signal OUT outputs a signal whose output signal level is inverted at the rising timing of adjacent pre-out signals among the pre-out signal [0], pre-out signal [1], pre-out signal [2], and pre-out signal [3] input to the mixer 160b. Therefore, the phase division signal OUT is a signal whose phase changes at the midpoint between the phase change points of adjacent Johnson counter code signals. Therefore, the phase division circuit 100a and the phase division circuit 100b have the function of outputting the same phase division signal OUT, except for the initial clock signal CLK portion (operation wake-up time) input to the global counter.

[0072] As described above, the integral A / D converter 1000a according to the first embodiment includes a global counter 200 that outputs a counter code signal including a Johnson counter code signal and a Gray code signal, which are multiple multiphase signals. The integral A / D converter also includes a column circuit 900a including a ramp generator circuit 300, a comparator 400a, and latch circuits 501a to 509a and 510a to 540a, and the output value of the latch circuit is set as a digital conversion output value for each column circuit 900a. The ramp generator circuit 300 outputs a ramp voltage whose voltage value changes linearly with time. The comparator 400a compares the ramp voltage with a pixel voltage generated in a pixel. The latch circuits 501a to 509a and 510a to 540a latch the counter code signal at the timing when the output of the comparator 400a is inverted.

[0073] The integral A / D converter 1000a includes a phase division circuit 100a that receives a counter code signal, generates a phase division signal that divides the phase of the counter code signal, and outputs the phase division signal to a latch circuit 600a as an LSB of a digitally converted output value of the integral A / D converter. The global counter 200 is provided for a predetermined number of column circuits 900. An example of the predetermined number is several thousand. That is, the global counter 200 may be provided for several thousand column circuits 900. In addition, the phase division circuit 100a may be provided for a number of column circuits that is less than the predetermined number, and the LSB signal may be provided by the multiple phase division circuits. An example of the multiple column circuits may be one to several hundred column circuits, preferably several tens to several hundred column circuits. The above configuration is common not only to the integral A / D converter of the first embodiment, but also to the integral A / D converters of the second and third embodiments described below.

[0074] According to the integral A / D converter configured as described above, by locally arranging phase division circuits at appropriate intervals within the column, which appropriately combine counter code signals to generate high-speed signals, it is possible to perform A / D conversion processing at a speed faster than the frequency of the counter code signals.

[0075] (Embodiment 2) <An example of a phase division circuit according to the second embodiment> 10 is a block diagram of an example of a phase splitter circuit according to the second embodiment. The phase splitter circuit 100c according to the second embodiment splits four Johnson counter code signals having different phases, similarly to the phase splitter circuit 100b according to the first embodiment. <0> from <3> The phase splitter circuit 100c functions as an SMD circuit that receives an input of the mixer 160c. The configuration of the phase splitter circuit 100c differs from that of the phase splitter circuit 100b in that the mixer 160c is included. The configurations of the phase splitter circuit 100b and the phase splitter circuit 100c are the same except for the mixer 160c, so descriptions thereof will be omitted to avoid duplication.

[0076] The mixer 160c of the phase splitter circuit 100c according to the second embodiment is configured to output a two-phase phase split signal. That is, the frequency of the phase split signal of the phase splitter circuit 100c is half the frequency of the phase split signals of the phase splitter circuits 100a and 100b according to the second embodiment. In this way, by lowering the frequency of the phase split signal, it is expected that the transmission of the phase split signal will be stabilized by reducing noise and erroneous transmission.

[0077] Specifically, the mixer 160c includes a mixer 161c and a mixer 162c. The mixer 161c receives the pre-out signal [0] and the pre-out signal [2], and outputs a phase division signal 0 OUT(0). The mixer 162c receives the pre-out signal [1] and the pre-out signal [3], and outputs a phase division signal 0 OUT(0).

[0078] The phase of the phase division signal 0 OUT(0) is inverted at the rising edge of the pre-out signal [0], and the phase returns to the original at the rising edge of the pre-out signal [2]. In other words, the phase of OUT(0) changes at the midpoint between the phase changes of the Johnson counter code signal [0] and the Johnson counter code signal [1], and the phase changes at the midpoint between the phase changes of the Johnson counter code signal [2] and the Johnson counter code signal [3].

[0079] In addition, the phase of the phase division signal 1 OUT(1) is inverted at the rising edge of the pre-out signal [1], and the phase returns to the original at the rising edge of the pre-out signal [3]. In other words, the phase of OUT(1) changes at the midpoint between the phase changes of the Johnson counter code signal [1] and the Johnson counter code signal [2], and the phase changes at the midpoint between the phase changes of the Johnson counter code signal [3] and the Johnson counter code signal [0].

[0080] In the second embodiment, the LSB is expressed by two bits by connecting phase division signals 0 OUT(0) and 1 OUT(1) in parallel, and the LSB frequency is lowered. As described above, by lowering the frequency of the phase division signal, it is expected that the transmission of the phase division signal will be stabilized by reducing noise and erroneous transmission.

[0081] <An example of a timing chart of the phase division circuit according to the second embodiment> Fig. 11 is a timing chart of an example of the phase division circuit according to Fig. 10. In Fig. 11, Johnson counter code signal [0], Johnson counter code signal [1], Johnson counter code signal [2], and Johnson counter code signal [3] are diff In addition, one Johnson counter code signal has a half cycle of 4t diff The pulse signal sig0 is a pulse signal that starts from the rising and falling edges of the Johnson counter code signal [0] and continues for approximately (t diff The pulse signal sig1 has a high level period of about (t diff The delay signal C[n] is a pulse signal having a high level period of t / 2. The delay signal C[n] is a pulse signal having a high level period of t diff and a delayed signal delayed by the delay time of delay circuit 120b[0]. Delayed signal C[0] is a delayed signal during transmission through front mirror delay line 130b[0]. The output terminal signal Q[n] of D-type flip-flop DFFbn[0] outputs the signal level of pulse signal sig1 input to the D terminal at the rising edge of delayed signal C[n]. Therefore, as shown in FIG. 10, the output terminal signal Q[n] continues to output a high state, which is the signal level of pulse signal sig1, at the rising edge of delayed signal C[n]. The pre-out signal[0] is the sum signal of output terminal signal Q[n] and pulse signal sig0 amplified by rear mirror delay line 150b[0] (t diff / 2) A delayed signal.

[0082] The phase of the phase division signal 0 OUT(0) is inverted at the rising edge of the pre-out signal [0] and returns to the original phase at the rising edge of the pre-out signal [2]. The phase division signal 1 OUT(1) is inverted at the rising edge of the pre-out signal [1] and returns to the original phase at the rising edge of the pre-out signal [3].

[0083] <Example of Output Bit Pattern of A / D Converter According to Second Embodiment> 12 is a timing chart showing an example of an output bit pattern of the A / D converter according to the second embodiment. That is, in FIG. 12, the Johnson counter code signal JC that outputs the upper 4 middle bits from the LSB of the A / D converter according to the second embodiment is <0> Johnson Counter Code Signal JC <3> , the most significant bit is 1 bit of the Gray code signal <3> , and the LSB phase division signal. The LSB phase division signal has two phases and is represented by phase division signals OUT(0) and OUT(1).

[0084] The counter value in the upper part of FIG. 12 indicates the number of clocks of the clock signal CLK input to the global counter 200. Therefore, when the counter value of the clock signal CLK is "0", there is also no input to the integral type A / D converter 1000a. Therefore, the phase division signals OUT(0) and (1)="0", the Johnson counter code signal JC <0> Johnson Counter Code Signal JC <3> = "0" and other bits = "0". Each time the counter value is incremented, a phase-divided signal whose phase changes at the intermediate position where the phase of the adjacent Johnson counter code signal changes is generated. That is, the phase-divided signal has a frequency twice as high as the edge change of the Johnson counter code signal. In this way, the phase-divided signal outputs a high-speed signal whose phase changes at the intermediate phase of the Johnson counter code signal, which is a multi-phase clock, so that the probability of miscounting can be reduced. In addition, the phase-divided circuit can be designed to be placed adjacent to a circuit that requires high-speed operation as necessary, so that the phase-divided signal can be supplied over a short distance and with a low load. Moreover, in this embodiment, the phase-divided signal is expressed by two phases, phase-divided signals OUT(0) and (1), so that the speed of the phase-divided signal can be reduced by half compared to the first embodiment in which the phase-divided signal is expressed by one phase.

[0085] Therefore, the phase division signal can be configured to receive counter code signals such as a plurality of Johnson counter code signals as input, and to represent the LSB by a single (embodiment 1) or multiple (embodiment 2, etc.) phase division signals.

[0086] According to such an operation, the execution speed of the A / D converter can be more than twice as fast as the previous execution speed without increasing the frequency of the clock signal CLK input to the global counter 200. In addition, the execution speed of the A / D converter can be more than twice as fast as the previous execution speed without increasing the frequency of the counter code signal output from the global counter 200 and transmitted over a long distance. That is, the A / D converter according to this embodiment can meet user demands such as an improvement in the frame rate of an image sensor (not shown) connected to the input of the A / D converter, an increase in the number of pixels, and high image quality. In addition, the A / D converter can be made faster without increasing the chip area of ​​the A / D converter and the assembly cost.

[0087] (Embodiment 3) <An example of a phase division circuit according to the third embodiment> 13 is a block diagram of an example of a phase splitter circuit according to the third embodiment. The phase splitter circuit 100d according to the third embodiment, like the phase splitter circuit 100c according to the second embodiment, outputs four Johnson counter code signals having different phases. <0> from <3> The phase splitter circuit 100d functions as an SMD circuit that receives the input of the mixer 160d and the mirror delay circuit 150d. The configurations of the phase splitter circuit 100d are different from those of the phase splitter circuit 100c in that the mixer 160d and the mirror delay circuit 150d are the same as those of the phase splitter circuit 100c and the phase splitter circuit 100d, and therefore descriptions thereof will be omitted to avoid duplication.

[0088] The mixer 160d of the phase splitting circuit 100d according to the third embodiment is configured to output a two-phase phase split signal, similar to the second embodiment. The mixer 160d inputs a pre-out signal [1], a pre-out signal [2], a pre-out signal [3], and a pre-out signal [4], and outputs a phase split signal 1 OUT(1). The phase split signal 1 OUT(1) is a signal whose phase changes at the midpoint between the phase change points of adjacent Johnson counter code signals, similar to the phase split signal in the first embodiment. Furthermore, the mixer 160d outputs a phase split signal 0 OUT(0). The phase split signal 0 OUT(0) is a signal whose phase changes at 1 / 4 and 3 / 4 phase points between the phase change points of adjacent Johnson counter code signals. That is, the two-phase phase split signal of the phase splitting circuit 100d according to the third embodiment divides the interval between the phase change points of adjacent Johnson counter code signals into four, thereby increasing the conversion speed of a conventional A / D converter by four times. However, since there is no change in the frequency of the Johnson counter code signal in the first, second and third embodiments, it is expected that there will be no change in the stability of the signal transmitted over a long distance.

[0089] The mirror delay circuit 150d[0] outputs a signal obtained by delaying the pulse signal sig1 by 1 / 4 phase to the mixer 160d. The mirror delay circuit 151d[0] outputs a signal obtained by delaying the pulse signal sig1 by 2 / 4 phase to the mixer 160d. The mirror delay circuit 152d[0] outputs a signal obtained by delaying the pulse signal sig1 by 3 / 4 phase to the mixer 160d. Similarly, the mirror delay unit d[1] outputs a signal obtained by delaying the pulse signal sig2, the mirror delay unit d[2] outputs a signal obtained by delaying the pulse signal sig3, and the mirror delay unit d[3] outputs a signal obtained by delaying the pulse signal sig0 by 1 / 4 phase, 2 / 4 phase, or 3 / 4 phase.

[0090] Mixer 160d outputs phase division signal 0 OUT(0) and phase division signal 1 OUT(1) based on the signals output from mirror delay circuit 150d[0] to mirror delay circuit 150d[3]. In other words, the phase division signal has multiple counter code signals as input, and by changing the delay time of the mirror delay circuit, it is possible to configure the phase of the phase division signal to change at any position between the phase change points of the multiple counter code signals.

[0091] <Example of Output Bit Pattern of A / D Converter According to Third Embodiment> 14 is a timing chart showing an example of an output bit pattern of the A / D converter according to the third embodiment. That is, FIG. 14 shows a Johnson counter code signal JC outputting the upper four middle bits from the LSB of the A / D converter according to the third embodiment. <0> Johnson Counter Code Signal JC <3> , the most significant bit is 1 bit of the Gray code signal <3> , and an LSB phase division signal. The LSB phase division signal has two phases and is represented by phase division signals OUT(0) and OUT(1). The LSB signal may also be referred to as a local multiplication signal.

[0092] 14 indicates the number of clocks of the clock signal CLK input to the global counter 200. Therefore, when the counter value of the clock signal CLK is "0", there is no input to the integral type A / D converter 1000a. In this case, the phase division signals OUT(0) and (1) are "0", the Johnson counter code signal JC <0> Johnson Counter Code Signal JC <3> = "0" and other bits = "0". Every time the counter value is incremented four times, the phase division signal OUT(1) generates a phase division signal whose phase changes at the intermediate position where the phase of the adjacent Johnson counter code signal changes. Also, every time the counter value is incremented twice, the phase division signal OUT(0) generates a phase division signal whose phase changes at the 1 / 4 phase point and the 3 / 4 phase point between the phase changes of the adjacent Johnson counter code signals. Therefore, when the phase division signals OUT(0) and OUT(1) are arranged in parallel, a signal whose phase changes at every 1 / 4 phase between the phase changes of the adjacent Johnson counter code signals appears. That is, the two-phase phase division signal of the phase division circuit 100d according to the third embodiment divides the interval between the phase change points of the adjacent Johnson counter code signals into four, thereby four times faster than the conversion speed of the conventional A / D converter. In this way, the phase division signal outputs a high-speed signal that changes by dividing the interval between the phase change points of the Johnson counter code signal, which is a multi-phase clock, into four, so that it is possible to reduce the probability of erroneous counting. In addition, since the phase division circuit can be designed to be placed adjacent to a circuit that requires high-speed operation as necessary, it is possible to supply the phase division signal over a short distance with a low load. Moreover, in this embodiment, the phase division signal is expressed by two phases, phase division signals OUT(0) and (1), so the speed of the phase division signal can be reduced by half compared to the embodiment in which the phase division signal is expressed by one phase.

[0093] According to such an operation, the execution speed of the A / D converter can be four times or more faster than the previous execution speed without increasing the frequency of the clock signal CLK input to the global counter 200. In addition, the execution speed of the A / D converter can be two times or more faster than the previous execution speed without increasing the frequency of the counter code signal output from the global counter 200 and transmitted over a long distance. That is, the A / D converter according to this embodiment can meet user demands such as an improvement in the frame rate of an image sensor (not shown) connected to the input of the A / D converter, an increase in the number of pixels, and high image quality. In addition, the A / D converter can be made faster without increasing the chip area of ​​the A / D converter and the assembly cost.

[0094] 15 is a timing chart showing a comparison between the output bit patterns of the A / D converter of the comparative example and the present embodiment. The upper part of FIG. 15 is a comparison example, which is an example of an output bit pattern of a conventional A / D converter, and shows the Johnson counter code signal JC <0> From J.C. <2> and Gray code signal GR <3> and G.R. <4> For comparison, the top row of the comparative example shows the counter value of the clock signal input to the global counter. That is, in the comparative example in the top row of FIG. 15, the Johnson counter code signal JC <0> One period of indicates the period of an 8 LSB signal.

[0095] 15 shows an example of an output bit pattern of an A / D converter including the phase division circuit 100a of the first embodiment. The phase division signal of the first embodiment changes its phase at the intermediate position where the phases of adjacent Johnson counter code signals change, and therefore, conversion speed is twice as fast as that of the A / D converter of the comparative example. That is, the Johnson counter code signal JC, which is a long-distance transmission signal, <0> One period of indicates the period of a 16 LSB signal.

[0096] ​The middle and lower parts of Fig. 15 show an example of an output bit pattern of an A / D converter including the phase division circuit 100c of the second embodiment. The phase division signal of the second embodiment changes phase at the intermediate position where the phases of two adjacent Johnson counter code signals change, so that it is possible to perform conversion twice as fast as the A / D converter of the comparative example, and the frequency of the phase division signal is lowered. That is, the Johnson counter code signal JC, which is a long-distance transmission signal, <0> One period of the above indicates the period of a 16 LSB signal, but the frequency of the two-phase phase-divided signal is reduced to half that of the phase-divided signal in the first embodiment, thereby improving the stability of circuit transmission and reducing power consumption.

[0097] The lower part of FIG. 15 shows an example of an output bit pattern of an A / D converter including a phase splitter circuit 100d according to the third embodiment. The phase split signal according to the third embodiment is two-phase and includes a phase split signal 1 whose phase changes at an intermediate position between the phase changes of adjacent Johnson counter code signals. The phase split signal according to the third embodiment is two-phase and includes a phase split signal 0 whose phase changes at a 1 / 4 phase position and a 3 / 4 phase position between the phase changes of adjacent Johnson counter code signals. Therefore, when the phase split signals 0 and 1 are arranged in parallel, a bit pattern appears in which the phase changes every 1 / 4 phase between the phase changes of adjacent Johnson counter code signals. That is, the two-phase phase split signal of the phase splitter circuit 100d according to the third embodiment divides the interval between the phase change points of adjacent Johnson counter code signals into four, thereby increasing the conversion speed of a conventional A / D converter by four times. Therefore, the Johnson counter code signal JC, which is a long-distance transmission signal, <0> One period of this represents the period of a 32 LSB signal.

[0098] According to the common feature of the output patterns described above, a phase splitter circuit that generates a signal faster than a global counter code signal that determines the operating frequency of the semiconductor device can be arranged in a column. As a result, the semiconductor device can operate at a speed faster than the global counter code signal. In addition, since a plurality of relatively slow Johnson counter code signals can be used as the input of the phase splitter circuit, it is possible to endure long-distance transmission and high-load transmission. In addition, since the phase split signal of the phase splitter circuit outputs a high-speed signal that changes at an intermediate phase of the Johnson counter code signal, which is a multi-phase clock, it is possible to reduce the probability of miscounting. In addition, since the phase splitter circuit can be designed to be arranged adjacent to a circuit that requires high-speed operation as necessary, it is possible to supply the phase split signal over a short distance and with a low load.

[0099] (Variation 1) In the above first to third embodiments, a method for applying a phase division signal of a phase division circuit to the LSB of an A / D converter has been described. However, the output signal of the A / D converter may be subjected to image processing by an image processing circuit. In this case, the image processing circuit may be realized by a semiconductor circuit, and an image processing device as a semiconductor device may be realized by the A / D converter and the image processing circuit. That is, the first modification is applied to a case where a semiconductor device such as an image processing device is provided that includes an integral type A / D converter according to any one of the first to third embodiments and a semiconductor circuit such as an image processing circuit.

[0100] According to the semiconductor device having the above-described configuration, it is possible to increase the number of pixels of the imaging device, increase the number of gradations, thereby improving image quality, prevent uneven image quality, and prevent the generation of images with streaks.

[0101] (Variation 2) In the above-mentioned first to third embodiments and the first modification, the configuration in which the phase division signal of the phase division circuit is applied to the imaging device has been described. However, in a semiconductor device having a plurality of column circuits in parallel, in which the column circuits are operated by a counter code signal from a global counter, there are cases where a column circuit that requires a high-frequency signal is arranged locally. In such a case, a configuration in which a phase division circuit is arranged in or near the column circuit and a phase division signal operating at a high frequency is supplied to the column circuit is effective when the high-frequency signal is not required for all column circuits. For example, an example of such a semiconductor device is a memory semiconductor device such as a DRAM or an SRAM.

[0102] That is, the semiconductor device includes a column circuit driven by a counter code signal generated by a global counter being transmitted across a preceding column circuit, and a plurality of such column circuits are connected in parallel. The semiconductor device also includes a phase splitting circuit that generates a phase split signal that changes the phase at any position between phase change points of the counter code signal when the counter code signal is a multi-phase counter code signal. The phase splitting circuit is preferably disposed in a column circuit using a frequency higher than that of the counter code signal, or within one to several hundred column circuits from the column circuit. With this configuration, the phase splitting circuit is disposed in or near a column circuit that locally requires a high-frequency signal, making it possible to supply a low-load, high-speed phase splitting signal in a short transmission distance range.

[0103] The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. For example, the above embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those having all of the configurations described. In addition, it is possible to add, delete, or replace part of the configuration of the above embodiments with other configurations.

[0104] In addition, the above-mentioned configurations, functions, processing units, processing means, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. In addition, the above-mentioned configurations, functions, etc. may be realized in software by a processor interpreting and executing a program that realizes each function. Information such as the program, table, file, etc. that realizes each function can be stored in a recording device such as a memory, a hard disk, or an SSD (Solid State Drive), or in a recording medium such as an IC card, an SD card, or a DVD.

[0105] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0106] 100a, 100b, 100c, 100d phase divider circuit 160a, 160b, 160c, 160d mixers 200 Global Counter 210 Johnson Counter 230 Gray Code Counter 300 Ramp wave generating circuit 400a comparator 501a, 509a, 510a, 520a, 530a, 540a Latch circuits 900a, 900b, 900c, 900x column circuits 1000a Integrating A / D Converter 2000 Semiconductor equipment< / n>

Claims

1. a global counter that outputs a Johnson counter code signal including a polyphase signal; a column circuit including a ramp generating circuit that outputs a ramp voltage whose voltage value changes linearly with time, a comparator that compares the ramp voltage with a pixel voltage generated in a pixel, and a latch circuit that latches the Johnson counter code signal at a timing when the output of the comparator is inverted; an integral type A / D converter for each of the column circuits, the output value of the latch circuit being converted into a digital output value; a phase division circuit that receives the Johnson counter code signal as an input, generates a phase division signal that divides a phase of the Johnson counter code signal, and outputs the phase division signal to the latch circuit as an LSB of the digital conversion output value of the integral type A / D converter; The global counter is provided for a predetermined number of the column circuits, the phase division circuit is arranged for a number of the column circuits, the number of which is less than the predetermined number, and the LSB is shared by the plurality of phase division circuits; the phase division signal is configured to receive four-phase Johnson counter code signals whose phases differ by two clock signals, and to change the phase of the phase division signal at any position between phase change points of the four-phase Johnson counter code signals; One period of the Johnson counter code signal is the duration of a 16 LSB signal or a 32 LSB signal. Integral A / D converter.

2. The phase division signal is composed of 1 bit, One period of the Johnson counter code signal is the period of the 16 LSB signal.

2. The integral type A / D converter according to claim 1.

3. The phase division signal is a signal whose phase changes at a position between a phase change point of a first-phase Johnson counter code signal and a second-phase Johnson counter code signal, whose phase changes at a position between a phase change point of the second-phase Johnson counter code signal and a third-phase Johnson counter code signal, whose phase changes at a position between a phase change point of the third-phase Johnson counter code signal and a fourth-phase Johnson counter code signal, and whose phase changes at a position between a phase change point of the fourth-phase Johnson counter code signal and the first-phase Johnson counter code signal.

3. The integral type A / D converter according to claim 2.

4. The phase division signal is composed of two bits, One period of the Johnson counter code signal is the period of the 16 LSB signal.

2. The integral type A / D converter according to claim 1.

5. The phase division signal of one bit is a signal whose phase changes at any position between a phase change point of a first-phase Johnson counter code signal and a second-phase Johnson counter code signal, and whose phase changes at any position between a phase change point of a third-phase Johnson counter code signal and a fourth-phase Johnson counter code signal, the phase division signal of the other bit is a signal whose phase changes at an arbitrary position between the phase change points of the second-phase Johnson counter code signal and the third-phase Johnson counter code signal, and whose phase changes at an arbitrary position between the phase change points of the fourth-phase Johnson counter code signal and the first-phase Johnson counter code signal.

5. The integral type A / D converter according to claim 4.

6. The phase division signal is composed of two bits, One period of the Johnson counter code signal is the period of the 32 LSB signal.

2. The integral type A / D converter according to claim 1.

7. The phase division signal of one bit is a signal whose phase changes at any position between the phase change points of the Johnson counter code signals of adjacent phases, The phase division signal of the other bit is a signal whose phase changes at 1 / 4 and 3 / 4 phase points between the phase change points of the Johnson counter code signal of the adjacent phase.

7. The integral A / D converter according to claim 6.

8. the phase division circuit is arranged at every one to every several hundred column circuits from the global counter; 2. The integral type A / D converter according to claim 1.

9. the phase splitting circuit is arranged in a column circuit that operates at a higher frequency than the operating frequency of the adjacent column circuit, or within one to several hundred column circuits from the adjacent column circuit; 2. The integral type A / D converter according to claim 1.

10. An integral A / D converter according to any one of claims 1 to 9; A semiconductor circuit; A semiconductor device comprising:

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