Layout correction method for active region photomask and manufacturing method of semiconductor device

Abstract

The present invention relates to a layout correction method for an active region photomask and a manufacturing method for semiconductor components. The correction method includes: the active region photomask is used to manufacture semiconductor components adopting a local oxidation of silicon (LOCOS) isolation process. By adding OPC correction patterns to three sides of the active region pattern end that are in contact with the LOCOS region, the bird's beak deformation of the silicon local oxidation isolation structure in the semiconductor components manufactured using the active region photomask becomes negligible at the active region end position; wherein the active region end is used to set through holes or contact holes. The present invention improves the topography at the junction of the active region end and the LOCOS region through special OPC, avoids the active region being eroded by the bird's beak, enables the active region end to achieve good electrical contact with the through hole / contact hole with a smaller area, and finally achieves the purpose of effectively applying the LOCOS process to products with smaller line widths.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a method for correcting the layout of an active area photomask, a method for manufacturing a semiconductor component, and a readable storage medium. Background Art

[0002] The LOCOS (local oxidation of silicon) process is a typical isolation process in semiconductor manufacturing and is often applied to products with relatively large line widths. For CMOS devices isolated by the LOCOS process, the size of the devices is difficult to reduce due to the presence of the LOCOS bird's beak. Summary of the Invention

[0003] Based on this, it is necessary to provide a method for correcting the layout of an active area photomask that can reduce the area of semiconductor components using the LOCOS process.

[0004] A method for correcting the layout of an active area photomask, the active area photomask being used to manufacture semiconductor components using the local oxidation of silicon isolation process, by adding OPC correction patterns to three sides of the active area pattern end that are in contact with the LOCOS area, so that the bird's beak deformation of the local oxidation of silicon isolation structure in the semiconductor components manufactured using the active area photomask tends to be zero at the active area end; wherein the active area end is used to set through holes or contact holes.

[0005] The above method for correcting the layout of an active area photomask improves the topography at the junction of the active area end and the LOCOS area through special OPC, avoids the active area being eroded by the bird's beak, enables the active area end to achieve good electrical contact with the through hole / contact hole with a smaller area, and ultimately achieves the purpose of effectively applying the LOCOS process to products with smaller line widths. And since the OPC method is a mature layout correction technology, the correction of the active area pattern can be completed efficiently.

[0006] In one embodiment, the semiconductor component is a CMOS device.

[0007] In one embodiment, the method further includes the steps of: collecting OPC data for different active area topographies; establishing an OPC model for the active area pattern end according to the collected data; and performing OPC correction on the active area pattern, including adding OPC correction patterns to three sides of the active area pattern end that are in contact with the LOCOS area according to the OPC model.

[0008] In one embodiment, the OPC correction pattern includes two L-shaped structures, and each of the two L-shaped structures fits with a corner of the active area pattern end.

[0009] In one embodiment, the OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end.

[0010] In one embodiment, the OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end; the OPC correction pattern further includes two L-shaped structures, one of the L-shaped structures is disposed in a fitting manner outside the connection of the first and second strip structures among the three strip structures, and the other L-shaped structure is disposed in a fitting manner outside the connection of the second and third strip structures among the three strip structures.

[0011] In one embodiment, the OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end; the OPC correction pattern further includes a plurality of protrusions on the three strip structures.

[0012] In one embodiment, the three sides are composed of a short side, a first long side, and a second long side. The OPC correction pattern includes: a plurality of rectangles on the first long side, adjacent rectangles among the plurality of rectangles are connected to each other, and the rectangle closer to the short side has a longer side length in a first direction perpendicular to the first long side; a plurality of rectangles on the second long side, adjacent rectangles among the rectangles on the second long side are connected to each other, and the rectangle closer to the short side has a longer side length in a second direction perpendicular to the second long side; a plurality of rectangles on the short side, adjacent rectangles among the plurality of rectangles on the short side are connected to each other, and the rectangle closer to both ends of the short side has a longer side length in a third direction perpendicular to the short side, and the rectangle closer to the middle of the short side has a shorter side length in the third direction.

[0013] It is also necessary to provide a method for manufacturing a semiconductor device, including: providing a layout of a photomask; the photomask includes an active region photomask, and the layout of the active region photomask is the layout corrected by the layout correction method of the active region photomask described in any of the foregoing embodiments; preparing a photomask according to the layout; manufacturing a semiconductor device using the photomask; including using the active region photomask for lithography and etching to obtain a LOCOS region and an active region covered by an etched barrier layer, and then oxidizing and growing a silicon local oxidation isolation structure on the LOCOS region.

[0014] It is also necessary to provide a photomask, which is a photomask made from a layout obtained by the layout correction method of the active region photomask described in any of the foregoing embodiments.

[0015] It is also necessary to provide a readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the layout correction method of the active area photomask described in any one of the above embodiments are implemented.

[0016] It is also necessary to provide a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the layout correction method of the active area photomask described in any one of the above embodiments are implemented.

[0017] It is also necessary to provide a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the layout correction method of the active area photomask described in any one of the foregoing embodiments are implemented. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram in which the active area end in an exemplary layout is enlarged;

[0020] Figure 2 It is a schematic diagram of the mask pattern of the active area pattern end in Embodiment 1 of the present application;

[0021] Figure 3 It is a schematic diagram of the mask pattern of the active area pattern end in Embodiment 2 of the present application;

[0022] Figure 4 It is a schematic diagram of the mask pattern of the active area pattern end in Embodiment 3 of the present application;

[0023] Figure 5 It is a schematic diagram of the mask pattern of the active area pattern end in Embodiment 4 of the present application;

[0024] Figure 6 It is a schematic diagram of the mask pattern of the active area pattern end in Embodiment 5 of the present application;

[0025] Figure 7 It is a flowchart of the manufacturing method of semiconductor components in an embodiment. Detailed Embodiments

[0026] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0028] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0029] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device may also have additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0030] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0031] One of the reasons why it is difficult to reduce the size of a LOCOS device due to the presence of the LOCOS bird's beak is that the LOCOS process will erode the active region during silicon oxidation growth and form a bird's beak. The presence of the bird's beak will limit the size of the active region end at the bottom of the via, and at the same time affect the junction morphology between the active region and the field region, resulting in difficulty in reducing the line width and area of products using the LOCOS process. The above problems are particularly obvious in the narrow transistors of CMOS. Due to the small area of the active region, the LOCOS in three directions will erode the area of the active region, resulting in the need to particularly enlarge the area of the active region. Therefore, when designing the lithography mask of the active region of the LOCOS process, the active region end will be drawn large enough to ensure that the LOCOS bird's beak will not erode the via connection. Although this solution can ensure the normal operation of the device, it increases the area of each device end, resulting in an increase in the size of the entire chip.

[0032] For the process using LOCOS (local oxidation of silicon) for isolation, the minimum active region width is limited. For some 0.5-micron front-end processes, the minimum active region width can be set to 0.6 microns. However, for the source and drain leads of CMOS (complementary metal oxide semiconductor) devices, the size of the active region extending out of the gate needs to be specially enlarged to ensure good contact between the contact hole and the active region. See Figure 1, the active region pattern 10 is magnified at the position of the active region end 12 to ensure effective contact between the active region end 12 and the contact hole 22 (or via). This situation is particularly serious when it is necessary to integrate the cobalt silicide process (such as the self-aligned silicide process), because the presence of the bird's beak will cause cobalt not to grow, resulting in an open circuit or poor contact in the contact hole.

[0033] Exemplary solutions can change the isolation process from LOCOS to STI (shallow trench isolation) structure, or increase implantation after contact hole etching to form ohmic contact, but both methods have irreconcilable contradictions - it is relatively difficult to integrate thick gate oxide in the STI process, while increasing contact hole implantation is not applicable to shallow junction processes.

[0034] Lithography technology is the driving force for the development of integrated circuit manufacturing processes and is also one of the most complex technologies. Compared with other individual manufacturing technologies, the improvement of lithography technology is of great significance for the development of integrated circuits. Before the lithography process begins, the pattern needs to be copied onto the photomask through a specific device first, and then the pattern structure on the photomask is copied onto the wafer used to form the chip through the lithography machine. During the exposure process in lithography, due to the interference and diffraction phenomena of light, there are certain deformations and deviations between the lithography pattern obtained on the actual product wafer and the photomask pattern. This error in lithography will directly affect the circuit performance and production yield. The main reasons for the occurrence of light interference and diffraction phenomena are that the line width of the layout pattern (and the spacing between patterns) is close to or even less than the wavelength of the light used for exposure.

[0035] To solve the above problems, optical proximity correction (OPC) can be performed on the photomask layout. OPC can be carried out through computer-aided software tools (OPC software). By using mature OPC software, OPC engineers can efficiently obtain the corrected photomask layout. The wavelength of the light wave used in the exemplary lithography exposure is 248 nm, so OPC is usually applied to products with small line widths, such as products below 0.3 microns.

[0036] Due to the bird's beak effect of LOCOS, the LOCOS process is usually not applicable to products with small line widths. Therefore, for products using the LOCOS process, OPC processing is usually not performed.

[0037] This application uses optical proximity correction to correct the active region pattern, making the deformation caused by the bird's beak of LOCOS tend to be zero at the active region end position, so that the active region end pattern can be made smaller. And because the layout correction method of this application can be carried out using mature OPC software, the correction of the active region pattern can be efficiently completed.

[0038] Specifically, the present application provides a method for correcting the layout of an active area photomask, and the active area photomask is used for manufacturing semiconductor components adopting the local oxidation of silicon (LOCOS) isolation process. The method for correcting the layout of the active area photomask adds OPC correction patterns to three sides of the active area pattern end that are in contact with the LOCOS area, so that the bird's beak deformation of the silicon local oxidation isolation structure in the semiconductor components manufactured using the active area photomask tends to be eliminated at the active area end position; wherein the active area end is used to set through holes or contact holes.

[0039] The above-mentioned method for correcting the layout of the active area photomask improves the topography at the junction of the active area end and the LOCOS area through special OPC, avoids the active area being eroded by the bird's beak, enables the active area end to achieve good electrical contact with the through hole / contact hole with a smaller area, and finally achieves the purpose of effectively applying the LOCOS process to products with smaller line widths. The overlap area between the active area and the contact hole / through hole can be made consistent with the shallow trench isolation (STI) process. At the same time, the manufacturing of the device can be adapted to the thick gate oxide process, and no additional injection for forming ohmic contact is required after the contact hole etching, which can eliminate the junction leakage problem caused by this injection. And since the OPC method is a mature layout correction technology, the correction of the active area pattern can be efficiently completed.

[0040] The above-mentioned method for correcting the layout of the active area photomask is applicable to the preparation of photomasks for CMOS devices and can also be used for the preparation of photomasks for other components.

[0041] In an embodiment of the present application, the above-mentioned method for correcting the layout of the active area photomask is applicable to the preparation of photomasks for components that form cobalt silicide at the position where the active area is in contact with the contact hole (or through hole).

[0042] In an embodiment of the present application, the method for correcting the layout of the active area photomask includes:

[0043] Step A: Collect OPC data for different active area topographies.

[0044] Data can be collected for different active area widths / spaces / areas.

[0045] Step B: Establish an OPC model for the active area pattern end according to the collected data.

[0046] After the OPC model is established, the layout of the active area photomask (mainly the active area pattern end) can be corrected by OPC according to this model.

[0047] Step C: Perform OPC correction on the active area pattern.

[0048] According to the OPC model, an OPC correction pattern is added to the three edges of the active area pattern end that contact the LOCOS area. After OPC correction, the bird's beak deformation of the LOCOS is eliminated at the active area end position, so that when the active area end is made relatively small, the effective contact of the contact hole at the end position can be guaranteed.

[0049] Figure 2 2 is a schematic diagram of a mask pattern of an active region pattern terminal of the first embodiment of the present application. In this embodiment, the added OPC correction pattern includes two L-shaped structures 212 , and each of the two L-shaped structures 212 is aligned with a corner of the active region pattern terminal 210 . Figure 2 Also marked are the LOCOS region 30 and the via 220 .

[0050] Adding an L-shaped structure at the corner of the active area graphic terminal 210 can ensure that the bird's beak deformation of LOCOS is eliminated at the active area terminal position when the area of ​​the active area graphic terminal is slightly increased, thereby ensuring effective contact of the contact hole at the terminal position when the active area terminal is made relatively small. Figure 3 : is a schematic diagram of the mask pattern of the active area pattern terminal of the second embodiment of the present application. In this embodiment, the added OPC correction pattern includes a strip structure 312 located on each of the three sides of the active area pattern terminal 310 that contacts the LOCOS area 30, and the three strip structures 312 are connected end to end to form a "匚" shape. Note that the three sides of the active area pattern terminal 310 that contact the LOCOS area 30 mentioned here are stated from the perspective before the OPC correction pattern is added (after the OPC correction pattern is added, the short side of the active area pattern terminal 310 is no longer in direct contact with the LOCOS area 30).

[0051] Adding a "匚"-shaped structure to the active area graphic terminal 310 can ensure that the bird's beak deformation of LOCOS is eliminated at the active area terminal position when the area of ​​the active area graphic terminal is slightly increased, thereby ensuring effective contact of the contact hole at the terminal position when the active area terminal is made relatively small.

[0052] Figure 4 Schematic diagram of the mask pattern of the active area pattern end of the third embodiment of the present application. In this embodiment, the added OPC correction pattern includes a strip structure located on each of the three sides of the active area pattern end 410 that are in contact with the LOCOS area 30, and these three strip structures are connected end to end to form a "匚" shape. The OPC correction pattern also includes two L-shaped structures 414, one L-shaped structure 414 is bonded to the outside of the connection between the first strip structure 411 and the second strip structure 412, and the other L-shaped structure 414 is bonded to the outside of the connection between the second strip structure 412 and the third strip structure 413. Figure 4In the illustrated embodiment, since the connection between the first strip structure 411 and the second strip structure 412 and the connection between the second strip structure 412 and the third strip structure 413 are both right angles, they can fit closely with the right angle of the L-shaped structure 414 .

[0053] Add 410 at the active area graphic terminal Figure 4 The structure shown can ensure that the bird's beak deformation of LOCOS at the end of the active area is eliminated when the area of ​​the active area graphic end is slightly increased, thereby ensuring effective contact of the contact hole at the end when the active area end is made relatively small.

[0054] Figure 5 Schematic diagram of the mask pattern of the active area pattern terminal of the fourth embodiment of the present application. In this embodiment, the added OPC correction pattern includes a strip structure 512 located on each of the three sides of the active area pattern terminal 510 that contacts the LOCOS area 30, and the three strip structures 512 are connected end to end to form a "匚" shape. The OPC correction pattern also includes a plurality of protrusions 514 located on the three strip structures 512. In one embodiment of the present application, the protrusion 514 is rectangular. In other embodiments, the protrusion 514 may also be other shapes.

[0055] Add the active area graphic terminal 510 Figure 5 The structure shown can ensure that the bird's beak deformation of LOCOS at the end of the active area is eliminated when the area of ​​the active area graphic end is slightly increased, thereby ensuring effective contact of the contact hole at the end when the active area end is made relatively small.

[0056] Figure 6 Schematic diagram of the mask pattern of the active area pattern terminal of the fifth embodiment of the present application. The active area pattern terminal 610 has a short side, a first long side and a second long side in contact with the LOCOS area 30. The added OPC correction pattern includes:

[0057] A plurality of rectangles located on the first long side, wherein adjacent rectangles among the plurality of rectangles are connected to each other, and the closer the rectangle is to the short side, the longer the side length in the first direction is, and the first direction is perpendicular to the first long side.

[0058] The multiple rectangles located on the second long side are connected to each other among the adjacent rectangles located on the second long side, and the closer the rectangle is to the short side, the longer the side length in the second direction is, and the second direction is perpendicular to the second long side.

[0059] A plurality of rectangles located on the short side, adjacent rectangles among the plurality of rectangles located on the short side are connected to each other, and the rectangles closer to both ends of the short side have longer side lengths in the third direction, and the rectangles closer to the middle of the short side have shorter side lengths in the third direction, and the third direction is perpendicular to the short side.

[0060] Add at the end 610 of the active region pattern Figure 6 The structure shown can ensure that when the area increase at the end of the active region pattern is very small, the bird's beak deformation of LOCOS tends to be zero at the end position of the active region, so that even when the end of the active region is made relatively small, the effective contact of the contact hole at the end position can be ensured.

[0061] The present application correspondingly provides a method for manufacturing a semiconductor device. Figure 7 It is a flowchart of a method for manufacturing a semiconductor device in an embodiment, including the following steps:

[0062] S710, provide the layout of the photomask.

[0063] The manufacturing method provided by the present application is used to manufacture a semiconductor device having an active region and forming an isolation structure through the LOCOS process. Multiple photomasks are required during the manufacturing process, including an active region photomask. The layout of the active region photomask is obtained after being corrected by the layout correction method of the active region photomask described in any of the foregoing embodiments.

[0064] S720, prepare a photomask according to the layout.

[0065] A photomask forming a corresponding light-shielding film pattern according to the layout can be prepared on a transparent substrate by using a method well-known in the art. The present application does not limit the specific photomask preparation method, the substrate, the material of the light-shielding film, etc.

[0066] S730, use the photomask to manufacture a semiconductor device.

[0067] Step S730 includes using the active region photomask for lithography and etching to obtain a LOCOS region and an active region covered by an etched barrier layer, and then oxidizing and growing a silicon local oxidation isolation structure on the LOCOS region. In an embodiment of the present application, a silicon nitride layer is deposited on a silicon substrate as an etched barrier layer, and then the silicon nitride layer is lithographed and etched using the active region photomask. The silicon nitride layer in the LOCOS region is etched away, the surface of the silicon substrate in the LOCOS region is exposed, and then an oxide layer is grown on the exposed silicon substrate surface by thermal oxidation to form a LOCOS structure.

[0068] Step S730 further includes the steps of lithographing and etching through a contact hole (or via) photomask to form a contact hole (or via) at the end of the active region, and filling a conductive material in the contact hole.

[0069] Since the photomask of the active region has been corrected as described above, the bird's beak deformation of LOCOS tends to be absent at the end position of the active region. The end of the active region achieves good electrical contact with the vias / contact holes with a smaller area, and finally achieves the purpose of effectively applying the LOCOS process to products with smaller line widths.

[0070] In an embodiment of the present application, step S730 further includes a step of forming a thick gate oxide layer.

[0071] The present application correspondingly provides a photomask made of a layout obtained by the layout correction method of the photomask of the active region according to any of the above embodiments.

[0072] The present application also provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the layout correction method of the photomask of the active region according to any of the above embodiments are implemented.

[0073] The present application also provides a computer device, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps of the layout correction method of the photomask of the active region according to any of the above embodiments are implemented.

[0074] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the layout correction method of the photomask of the active region according to any of the foregoing embodiments are implemented.

[0075] It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps does not have a strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0076] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0077] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0078] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A layout correction method for an active area photomask, the active area photomask being used to manufacture semiconductor components adopting a silicon local oxidation isolation process, characterized in that, By adding OPC correction patterns to three sides of the active region pattern end that are in contact with the LOCOS region, the bird's beak deformation of the local oxidation of silicon isolation structure in the semiconductor device manufactured using the active region photomask becomes negligible at the active region end; wherein the active region end is used to set vias or contact holes. The layout correction method of the active region photomask includes the steps of: Collecting OPC data for different active region topographies; Establishing an OPC model for the active region pattern end based on the collected data; Performing OPC correction on the active region pattern, including adding OPC correction patterns to three sides of the active region pattern end that are in contact with the LOCOS region according to the OPC model.

2. The layout correction method of the active region photomask according to claim 1, wherein The semiconductor device is a CMOS device.

3. The layout correction method for the active region photomask according to claim 1, characterized in that, The OPC correction pattern includes two L-shaped structures, and each of the two L-shaped structures fits with a corner of the active region pattern end.

4. The layout correction method of the active region photomask according to claim 1, wherein The OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end.

5. The layout correction method of the active region photomask according to claim 1, characterized in that The OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end; the OPC correction pattern further includes two L-shaped structures, wherein one L-shaped structure is disposed outside and in contact with the connection of the first and second strip structures among the three strip structures, and the other L-shaped structure is disposed outside and in contact with the connection of the second and third strip structures among the three strip structures.

6. The layout correction method of the active area photomask according to claim 1, characterized in that, The OPC correction pattern includes a strip structure on each of the three sides, and the three strip structures are connected end to end; the OPC correction pattern further includes a plurality of protrusions on the three strip structures.

7. The layout correction method of the active region photomask according to claim 1, wherein The three sides are composed of a short side, a first long side, and a second long side, and the OPC correction pattern includes: A plurality of rectangles on the first long side, adjacent rectangles among the plurality of rectangles are connected to each other, and the rectangle closer to the short side has a longer side length in a first direction perpendicular to the first long side; A plurality of rectangles on the second long side, adjacent rectangles among the rectangles on the second long side are connected to each other, and the rectangle closer to the short side has a longer side length in a second direction perpendicular to the second long side; A plurality of rectangles on the short side, adjacent rectangles among the plurality of rectangles on the short side are connected to each other, and the rectangle closer to both ends of the short side has a longer side length in a third direction perpendicular to the short side, and the rectangle closer to the middle of the short side has a shorter side length in the third direction.

8. A manufacturing method of a semiconductor device, including: Providing a layout of a photomask; the photomask includes an active region photomask, and the layout of the active region photomask is the layout corrected by the layout correction method of the active region photomask according to any one of claims 1-7; Preparing a photomask according to the layout; Manufacturing a semiconductor device using the photomask; including lithographing and etching using the active region photomask to obtain a LOCOS region and an active region covered by an etched barrier layer, and then oxidizing and growing a local oxidation of silicon isolation structure on the LOCOS region.

9. A readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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