Method for dsoi wafer preparation for pseudo-mos characterization

Abstract

The application discloses a DSOI wafer preparation method for pseudo-MOS characterization, and the method comprises the following steps: providing a plurality of original wafers, respectively preparing corresponding bottom wafers and top wafers by using the original wafers, preparing a double buried oxygen silicon-on-insulator (DSOI) wafer with a pseudo-MOS characterization structure by using the bottom wafers and the top wafers, and performing layer-by-layer etching and metal electrode etching on a step structure of the DSOI wafer with the pseudo-MOS characterization structure, so as to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization. By using the application, the problem that the interface characteristics are less in the prior art based on an SOI process for supporting characterization of a pseudo-MOS characterization structure is solved, and the interface characteristic parameter characterization of multiple interfaces is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating DSOI wafers for pseudo-MOS characterization. Background Technology

[0002] Pseudo-MOS is a characterization technique used to characterize parameters such as threshold voltage, mobility, and interface state traps of the underlying silicon film (SOI1) before complementary metal-oxide-semiconductor (CMOS) processing on a silicon-on-insulator (SOI) wafer. It is called pseudo-MOS because it has an electrode contact structure similar to that of a MOS device.

[0003] Currently, the proposed structures for characterizing wafer interface properties are SOI-based structures for pseudo-MOS characterization. In practice, two electrodes can be arbitrarily connected on the top silicon film of the SOI wafer as the source and drain, respectively, with the SOI substrate as the gate, to characterize the interface properties between SOI and BOX. However, in practice, it has been found that SOI-based pseudo-MOS characterization structures support characterizing limited interface properties, and no DSOI-based structure for pseudo-MOS characterization has yet been proposed. Summary of the Invention

[0004] This application provides a DSOI wafer fabrication method for pseudo-MOS characterization, which can propose a structure for pseudo-MOS characterization based on the DSOI process to support the method of characterizing the electrical properties of the four interfaces of DSOI.

[0005] On the one hand, this application provides a method for fabricating a DSOI wafer for pseudo-MOS characterization through an embodiment of this application, the method comprising:

[0006] Provides multiple original wafers;

[0007] The corresponding bottom layer wafer and top layer wafer are respectively prepared using the original wafer;

[0008] Using the bottom wafer and the top wafer, a double buried oxide insulator-on-silicon (DSOI) wafer with a pseudo-MOS characterization structure was fabricated.

[0009] The DSOI wafer with the pseudo-MOS characterization structure is subjected to step-by-step etching and metal electrode etching to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization.

[0010] Optionally, the step of fabricating the corresponding underlying wafer using the original wafer includes:

[0011] The original wafer is used to prepare the corresponding first intermediate wafer and second intermediate wafer respectively;

[0012] A third intermediate wafer is prepared using the first intermediate wafer and the second intermediate wafer;

[0013] The third intermediate wafer is etched and metal is deposited to obtain a bottom wafer with a substrate electrode.

[0014] Optionally, the step of fabricating a corresponding first intermediate wafer using the original wafer includes:

[0015] Electrode etching and metal deposition are performed on the two original wafers respectively to obtain a first etched wafer and a second etched wafer with substrate electrodes;

[0016] The first etched wafer is flipped over and bonded to the second etched wafer to obtain the first bonded wafer;

[0017] The first bonding wafer is etched to expose the substrate electrode on the first bonding wafer;

[0018] Silicon material is grown on the substrate electrode that is exposed on the first bonding wafer to prepare the first intermediate wafer.

[0019] Optionally, the step of fabricating a corresponding second intermediate wafer using the original wafer includes:

[0020] The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a first processed wafer;

[0021] The first processed wafer is subjected to electrode etching and metal deposition to obtain a second intermediate wafer with metal electrodes.

[0022] Optionally, the step of preparing a third intermediate wafer using the first intermediate wafer and the second intermediate wafer includes:

[0023] The second intermediate wafer is flipped over and bonded to the first intermediate wafer to obtain a second bonded wafer;

[0024] The excess upper layer wafer on the second bonding wafer is cut off using a layer transfer process to obtain the remaining first cut wafer;

[0025] Silicon material is grown on the first diced wafer to obtain the third intermediate wafer.

[0026] Optionally, the step of fabricating the corresponding top-layer wafer using the original wafer includes:

[0027] The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a second processed wafer;

[0028] The excess upper layer wafer on the second processed wafer is cut off using a layer transfer process to obtain the top layer wafer.

[0029] Optionally, the fabrication of a double buried oxide-on-insulator (DSOI) wafer with a pseudo-MOS characterization structure using the bottom wafer and the top wafer includes:

[0030] The top wafer is flipped over and bonded to the bottom wafer to obtain a third bonded wafer;

[0031] The excess upper layer wafer on the third bonding wafer is cut off by a layer transfer process to obtain the double buried oxide insulator-on-silicon (DSOI) wafer with pseudo-MOS characterization structure.

[0032] Optionally, the DSOI wafer used for pseudo-MOS characterization is stacked sequentially from bottom to top, comprising: a substrate Sub, a second buried oxide layer BOX2, a second silicon film SOI2, a first buried oxide layer BOX1, and a first silicon film SOI1, wherein the substrate Sub, the second buried oxide layer BOX2, and the second silicon film SOI2 are provided by fabricating the bottom wafer, and the first buried oxide layer BOX1 and the first silicon film SOI1 are provided by fabricating the top wafer.

[0033] Optionally, different metal electrodes on the DSOI wafer used for pseudo-MOS characterization can be combined to characterize the interface characteristic parameters of the corresponding interfaces.

[0034] Optionally, the method further includes: fabricating a DSOI device with a pseudo-MOS characterization structure on the DSOI wafer used for pseudo-MOS characterization.

[0035] On the other hand, this application provides a DSOI device with a pseudo-MOS characterization structure through one embodiment of the application. The device is fabricated on the DSOI wafer used for pseudo-MOS characterization, and the DSOI wafer used for pseudo-MOS characterization is fabricated using the DSOI wafer fabrication method for pseudo-MOS characterization described above.

[0036] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application provides multiple raw wafers, and respectively uses the raw wafers to prepare corresponding bottom wafers and top wafers. The bottom wafers and top wafers are then used to prepare a double buried oxide insulator-on-silicon (DSOI) wafer with a pseudo-MOS characterization structure. Finally, the DSOI wafer with the pseudo-MOS characterization structure is subjected to step-by-step etching and metal electrode etching to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization. The pseudo-MOS characterization structure can be used to analyze the interface characteristic parameters between different interfaces in the wafer, such as the interface characteristics of the four interfaces: SOI1 and BOX1, SOI2 and BOX1, SOI2 and BOX2, and SUB and BOX2. Furthermore, the step structure (similar to a multi-layered cake) used in this application effectively prevents leakage current at the silicon film edges, ensuring wafer safety and reliability. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a traditional pseudo-MOS device provided by existing technology.

[0039] Figure 2 This is a schematic diagram of the current transfer characteristic curve of a pseudo-MOS provided by existing technology.

[0040] Figure 3 This is a simulation interface current distribution diagram of a pseudo-MOS provided by existing technology.

[0041] Figure 4 This is a schematic flowchart of a DSOI wafer fabrication method for pseudo-MOS characterization provided in an embodiment of this application.

[0042] Figure 5 This is a schematic diagram of the fabrication process of a DSOI wafer for pseudo-MOS characterization provided in an embodiment of this application.

[0043] Figure 6 This is a schematic diagram of a DSOI device with a pseudo-MOS structure provided in an embodiment of this application.

[0044] Figure 7 This is a simulation diagram based on a DSOI wafer used for pseudo-MOS characterization, provided in an embodiment of this application.

[0045] Figure 8 This is a schematic diagram of the simulated internal structure and metal electrodes of a DSOI wafer used for pseudo-MOS characterization, provided in an embodiment of this application.

[0046] Figure 9 This is a schematic diagram of a simulated PN junction contact electrode provided in an embodiment of this application.

[0047] Figure 10 This is a schematic diagram of charge movement based on a DSOI wafer used for pseudo-MOS characterization, provided in an embodiment of this application.

[0048] Figure 11 This is a schematic diagram of the current transfer characteristic curve corresponding to the BOX1 and SOI1 interface provided in an embodiment of this application.

[0049] Figure 12 This is a schematic diagram of the current transfer characteristic curve corresponding to the BOX1 and SOI2 interface provided in an embodiment of this application.

[0050] Figure 13 This is a schematic diagram of the current transfer characteristic curve corresponding to the BOX2 and SOI2 interface provided in an embodiment of this application.

[0051] Figure 14 This is a schematic diagram of the current transfer characteristic curve corresponding to the BOX2 and SUB interface provided in an embodiment of this application. Detailed Implementation

[0052] During the process of filing this application, the applicant discovered that: Please see Figure 1 A schematic diagram of a traditional pseudo-MOS device is shown. Figure 1 The pseudo-MOS device shown includes: a substrate 101, a buried oxide layer (BOX) 102, and a silicon-on-insulator (SOI) layer (also known as the top silicon film) 103. During pseudo-MOS characterization, two electrodes can be arbitrarily connected to the top silicon film as the source and drain, respectively, with the substrate serving as the gate, to characterize the interface parameters between the SOI and the BOX. Its corresponding current characteristic curve (I...) d -V g )like Figure 2 As shown, it can be seen that current can be detected in the structure (or pseudo-MOS device) used for pseudo-MOS characterization when both positive and negative gate voltages are applied to the gate. This is a typical characteristic for pseudo-MOS characterization. When a positive voltage is applied, the drain current is the electron current; when a negative voltage is applied, the drain current is the hole current. Please refer to [further details omitted]. Figure 3 This illustrates a pseudo-MOS I d -V g Simulation interface current distribution diagram. (Example) Figure 3In silicon (Si), the electron mobility is about three times that of the hole, so the corresponding saturation currents of the two differ by approximately three times.

[0053] This application provides a DSOI wafer fabrication method for pseudo-MOS characterization, which solves the technical problem in the prior art that the interface characteristics supported for characterization of pseudo-MOS structures based on SOI process are limited.

[0054] The technical solution of this application embodiment is to solve the above-mentioned technical problems. The overall idea is as follows: providing multiple raw wafers; preparing corresponding bottom wafers and top wafers using the raw wafers respectively; preparing a double buried oxide insulator-on-silicon (DSOI) wafer with a pseudo-MOS characterization structure using the bottom wafers and the top wafers; performing step-by-step etching and metal electrode etching on the DSOI wafer with the pseudo-MOS characterization structure to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization.

[0055] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0056] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0057] Please see Figure 4 This is a schematic flowchart of a DSOI wafer fabrication method for pseudo-MOS characterization provided in an embodiment of this application. Figure 4 The method shown includes the following implementation steps:

[0058] S401 provides multiple original wafers 401.

[0059] S402, respectively, using the original wafer 401 to prepare the corresponding bottom wafer 411 and top wafer 413.

[0060] In one embodiment, the present application may use the original wafer 401 to prepare a first intermediate wafer 405 and a second intermediate wafer 407, and then use the first intermediate wafer 405 and the second intermediate wafer 407 to prepare a third intermediate wafer 410. Finally, the third intermediate wafer 410 is etched and metal is deposited to obtain a bottom wafer 411 with a substrate electrode.

[0061] In one specific embodiment, please refer to Figure 5This is a schematic flowchart of a DSOI wafer fabrication process for pseudo-MOS characterization provided in an embodiment of this application. Figure 5 In this application, a raw wafer 401 (also referred to as a Si wafer) can be etched and metal deposited. Specifically, the substrate (Sub) electrode positions can be etched out and metal can be deposited on the electrode paths to obtain a first etched wafer 402 with substrate electrodes. Similarly, another raw wafer 401 can be etched and metal deposited in the same way to obtain a second etched wafer 403 with substrate electrodes. The first etched wafer 402 is then flipped over and bonded to the second etched wafer 403 to obtain a first bonded wafer 404. The first bonded wafer 404 is further etched down to the metal layer to remove the upper silicon layer and expose the substrate electrodes. A layer of the raw wafer 401 is then bonded on it or a layer of silicon material (such as SiO2) is grown to obtain a first intermediate wafer 405.

[0062] Optionally, this application may further perform thermal oxidation and hydrogen implantation on another original wafer 401 to obtain a first processed wafer 406. Then, the first processed wafer 406 is subjected to electrode etching and metal deposition, for example, removing a portion of SiO2 and Si to expose two metal electrodes (specifically, two SOI2 down), thereby obtaining a second intermediate wafer 407 having two metal electrodes.

[0063] Furthermore, this application flips the second intermediate wafer 407 and bonds the flipped second intermediate wafer 407 to the first intermediate wafer 405. Specifically, after flipping, SiO2 is bonded to the top layer Si and SiO2 to obtain a second bonded wafer 408. Then, a layer transfer process is used to cut off the excess upper layer wafer on the second bonded wafer 408 to obtain the remaining first cut wafer 409. Finally, a layer of silicon material (SiO2) is grown on the surface of the first cut wafer 409 to obtain a third intermediate wafer 410.

[0064] Optionally, this application may further perform thermal oxidation and hydrogen implantation on another original wafer 401 to obtain a second processed wafer 412. Then, a layer transfer process is used to cut off the excess upper layer wafer on the second processed wafer 412 to obtain a top layer wafer 413.

[0065] S403. Using the bottom wafer 411 and the top wafer 413, a double buried oxide insulator-on-silicon (DSOI) wafer 415 with a pseudo-MOS characterization structure is prepared.

[0066] In a specific implementation as shown in the figure, the top layer wafer 413 can be flipped over, and the flipped top layer wafer 413 can be bonded to the bottom layer wafer 411 to obtain a third bonded wafer 414. Then, a layer transfer process is used to cut off the excess upper layer wafer on the third bonded wafer 414 to obtain a DSOI wafer 415 with a pseudo-MOS characterization structure.

[0067] S404. Perform step-by-step etching of the DSOI wafer 415 with the pseudo-MOS characterization structure and etching of the metal electrodes to obtain a DSOI wafer 416 with multiple metal electrodes for pseudo-MOS characterization.

[0068] Finally, this application can etch stage structures and metal electrodes layer by layer on the DSOI wafer 415 to obtain a DSOI wafer 416 with multiple metal electrodes for pseudo-MOS characterization.

[0069] In an optional embodiment, this application may also employ existing DSOI processes to fabricate DSOI devices for pseudo-MOS characterization on the DSOI wafer 416 used for pseudo-MOS characterization. Please also refer to... Figure 6 This is a schematic diagram of a DSOI device for pseudo-MOS characterization provided in an embodiment of this application. Figure 6 The device shown includes, from bottom to top, a substrate Sub 601, a second buried oxide layer BOX2 602, a second silicon insulator SOI2 603, a first buried oxide layer BOX1 604, and a first silicon insulator SOI1 605, wherein the substrate Sub 601, the second buried oxide layer BOX2 602, and the second silicon insulator SOI2 603 are provided by fabricating the bottom wafer, and the first buried oxide layer BOX1 604 and the first silicon insulator SOI1 605 are provided by fabricating the top wafer.

[0070] It should be noted that this application utilizes the pseudo-characterization approach for SOI wafer interface parameters, employing similar structures and methods to characterize the electrical parameters at each interface on a DSOI wafer, such as the interface state density between the top silicon layer and the BOX1 layer. Furthermore, considering the DSOI wafer structure, SOI2 leads can be used as gate contacts (i.e., gate metal electrodes). Alternatively, this application can create two leads at different locations on the SOI2 layer, serving as the source and drain, with the substrate Sub acting as the gate. This allows for the characterization of the SOI2 layer's interface state density with BOX2 and other interface electrical parameters.

[0071] To achieve the above objectives, this application proposes a device structure based on a DSOI wafer that can be used for pseudo-MOS characterization (i.e., a DSOI wafer or device for pseudo-MOS characterization) based on existing DSOI technology and a computer numerical simulation platform (TCAD). Due to the difference between simulation and experiment, in order to achieve numerical simulation of this pseudo-MOS characterization DSOI structure, this application proposes a DSOI simulation structure for pseudo-MOS characterization, which can characterize the four interfaces of DSOI, such as the interface characteristics of the four interfaces: SOI1 and BOX1, SOI2 and BOX1, SOI2 and BOX2, and SUB and BOX2.

[0072] Please see Figures 7-8 These are schematic diagrams illustrating the simulation structures of two DSOI wafers used for pseudo-MOS characterization provided in embodiments of this application. Figure 7 and Figure 8 As shown, this application deploys 10 metal electrodes on a DSOI wafer (or device) used for pseudo-MOS characterization, as shown in the figure: SOI11, SOI12, SOI13, SOI14 (specifically, four metal electrodes led out from SOI1), SOI21UP, SOI22UP (two metal electrodes on the upper surface of SOI2), SOI21DOWN, SOI22DOWN (two metal electrodes on the lower surface of SOI2). These metal electrodes can be combined to form four DSOI wafer structures for pseudo-MOS characterization, which can be used to characterize the interface characteristics of four interfaces: SOI1 and BOX1, SOI2 and BOX1, SOI2 and BOX2, and SUB and BOX2. Furthermore, the interface characteristics can be used to study the coupling effect between interfaces.

[0073] Please see also Figure 6 The figure shown is a simulated outline of the DSOI structure used for pseudo-MOS characterization in the simulation example of this application. The metal electrodes in this structure adopt a PNPN or NPNP electrode structure, for example... Figure 9 An exemplary schematic diagram of a simulated PN junction contact electrode is provided. The advantage of this structure is that it enables simultaneous measurement of electron and hole currents, while both connection methods exhibit the same subthreshold characteristics for electron and hole currents, eliminating the influence of asymmetric doping structures on the simulated current characteristics. Specifically, this application employs... Figure 6 The electrode deployment shown in the simulation is because the pseudo-MOS structure has current-carrying capacity. Figure 3The distribution characteristics shown are as follows: the bottom surface of the figure represents the gate electrode, and the left and right sides above represent the drain and source PN electrodes. The BOX and SOI interface is in an accumulation state. Hole current flows through the interface and then crosses the depletion region of the N-doped Poly on the right side of the P-doped SOI region. Electron current exhibits similar characteristics. Therefore, this application sets SOI2UP and SOI2DOWN to be perpendicular to each other. This is because during simulation, the heavily doped regions in the PN junction electrodes of SOI2UP and SOI2DOWN will intersect at 1e15cm. -3 Nitrogen doping forms a space charge region. If the two are in a parallel state, the following will occur: Figure 10 In the diagram, the alternation of positive and negative space charge regions means that the current flowing through the SOI2 / BOX2 and SOI2 / BOX1 interfaces is hindered by the depletion region beneath the electrodes. By staggering the upper and lower surface electrodes, the space charge regions can be misaligned, thus preventing the depletion region from obstructing current flow. Furthermore, it should be noted that... Figure 6 When SOI1 is used as the gate and SOI2 as the source and drain, the source and drain cannot be located outside the BOX1 layer. This is because the current needs to flow through the inversion or accumulation layer and then across the space charge region to flow into the electrode. This requires the space charge region that the current crosses to have sufficient charge carriers. In other words... Figure 3 As shown, in P-doped SOI, inversion (electron current flowing) or accumulation (hole current flowing) is also required below the space charge region. Sufficient holes must be present below the P-doped electrode during interface accumulation, while sufficient electrons must be present below the N-doped electrode during interface inversion. Therefore, the electrodes must be positioned within the corresponding gate oxide coverage area. Thus, in Figure 6 In the structure shown, the SOI2 DOWN electrode is led out from the area covered by BOX1 on the lower surface of SOI2, and the SUB electrode is led out from the area covered by BOX2 on the lower surface of SUB. Since the inversion and accumulation regions through which the current flows are very thin, and ultimately must cross the entire silicon film thickness to flow into the electrode, the silicon film thickness must not be too thick. In the DSOI process, the SOI1 and SOI2 thicknesses are sufficiently thin, while the SUB is too thick. To measure the interface current between SUB and BOX2, this application slightly adjusts the DSOI process to obtain... Figure 5 The fabrication process shown is used to prepare a DSOI wafer for pseudo-MOS characterization, and then to fabricate the corresponding DSOI device on the wafer.

[0074] In the specific simulation process, this application sets up 10 electrodes: SOI11, SOI12, SOI13, SOI14, SOI21UP, SOI22UP, SOI21DOWN, SOI22DOWN, SUB1, and SUB2, and uses different simulation parameters as shown in Table 1 below, such as the simulated device size, doping parameters, and applied electrode voltage. Through simulation, by changing the different electrode connections, current characteristic curves (IF) at each interface with the same characteristics as those of pseudo-MOS characterization structures obtained by using SOI technology are obtained. d -V g This was used to verify that the structure could be used for pseudo-MOS characterization, and the I corresponding to each interface was... d -V g For details of the curve, please refer to [link / reference]. Figures 11-14 As shown.

[0075] Table 1

[0076]

[0077] Please see Figure 11 This illustrates an I-type interface for characterizing the properties of the BOX1 and SOI1 interfaces. d -V g Schematic diagram of curves. Curve 1 represents the I corresponding to the hole current. d -V g Curve 2 represents the I corresponding to the electron current. d -V g Curve 3 represents the I corresponding to the total current. d -V g Curve. For example... Figure 11 In the simulation, SOI11 and SOI12 are used as the corresponding source and drain, respectively, and SOI21DOWN and SOI22DOWN are used as the gate. Based on the simulation parameters shown in Table 1, it can be seen that: in this application, SOI11 can be used as the drain with a positive voltage of 0.1V; SOI12 can be used as the source with a voltage of 0.0V; and SOI21DOWN and SOI22DOWN can be used as the gate with a scan voltage ranging from -10V to +10V. The corresponding Ig is then measured. d -V g Curves Figure 11 As shown, through this I d -V g The curve can be used to characterize the interface properties of the BOX1 and SOI1 interface, such as the interface state density or other electrical parameters.

[0078] Please see Figure 12 This illustrates an I-type interface for characterizing the properties of the BOX1 and SOI2 interfaces. d -V gSchematic diagram of curves. Curve 1 represents the I corresponding to the hole current. d -V g Curve 2 represents the I corresponding to the electron current. d -V g Curve 3 represents the I corresponding to the total current. d -V g Curve. For example... Figure 12 In the simulation, SOI21DOWN and SOI22DOWN were used as the source and drain, respectively, and SOI11 and SOI12 were used as the gate. Based on the simulation parameters shown in Table 1, it can be seen that: in this application, SOI21DOWN is used as the drain with a voltage of 0.1V; SOI22DOWN is used as the source with a voltage of 0.0V; and SOI11 and SOI12 are used as the gates with a scan voltage ranging from -10V to +10V. The corresponding Ig values ​​were measured. d -V g Curves Figure 12 As shown, through this I d -V g The curve can be used to characterize the interface properties between BOX1 and SOI2.

[0079] Please see Figure 13 This illustrates an I-type interface for characterizing the properties of the BOX2 and SOI2 interfaces. d -V g Schematic diagram of curves. Curve 1 represents the I corresponding to the hole current. d -V g Curve 2 represents the I corresponding to the electron current. d -V g Curve 3 represents the I corresponding to the total current. d -V g Curve. For example... Figure 13 In the simulation, SOI21UP and SOI22UP were used as the source and drain, and SUB1 and SUB2 as the gate. Based on the simulation parameters shown in Table 1, it can be seen that: in this application, SOI21UP is used as the drain with a voltage of 0.1V; SOI22UP is used as the source with a voltage of 0.0V; and SUB1 and SUB2 are used as the gates with a scan voltage ranging from -10V to +10V. The corresponding Ig values ​​were measured. d -V g Curves Figure 13 As shown, through this I d -V g The curve can be used to characterize the interface properties between the BOX2 and SOI2 interfaces.

[0080] Please see Figure 14 This illustrates an I-type interface for characterizing the properties of the BOX2 and SUB interfaces. d -Vg Schematic diagram of curves. Curve 1 represents the I corresponding to the hole current. d -V g Curve 2 represents the I corresponding to the electron current. d -V g Curve 3 represents the Id-Vg curve corresponding to the total current. For example... Figure 14 In the simulation, SOI21UP and SOI22UP were used as gates, and SUB1 and SUB2 were used as source and drain, respectively. Based on the simulation parameters shown in Table 1, it can be seen that: in this application, SUB1 is used as the drain with a voltage of 0.1V; SUB2 is used as the source with a voltage of 0.0V; and SOI21UP and SOI22UP are used as gates with a scan voltage ranging from -10V to +10V. The corresponding Ig values ​​were measured. d -V g Curves Figure 14 As shown, through this I d -V g The curve can be used to characterize the interface properties between the BOX2 and SUB interfaces.

[0081] This application proposes a structure for pseudo-MOS characterization based on DSOI technology, and proposes a pseudo-MOS simulation method based on DSOI based on previous research. This method can be used to analyze the interface characteristics between the four interfaces in DSOI: SOI1 and BOX1, SOI2 and BOX1, SOI2 and BOX2, and SUB and BOX2. Furthermore, to prevent leakage current at the silicon film edges during experiments, this application employs a stepped structure (similar to a multi-layered cake). In addition, to establish a reasonable process for characterizing all interface characteristics using pseudo-MOS, a process flow for fabricating DSOI wafers for pseudo-MOS characterization is proposed.

[0082] By implementing this application, multiple raw wafers are provided, and corresponding bottom and top wafers are fabricated using these raw wafers. The bottom and top wafers are then used to fabricate a silicon-on-insulator (DSOI) wafer with a pseudo-MOS characterization structure. Finally, the DSOI wafer with the pseudo-MOS characterization structure undergoes step-by-step etching and metal electrode etching to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization. The pseudo-MOS characterization structure can be used to analyze interface characteristics between different interfaces in the wafer, such as the interface characteristics of the four interfaces: SOI1 and BOX1, SOI2 and BOX1, SOI2 and BOX2, and SUB and BOX2. Furthermore, the step-by-step structure (similar to a multi-layered cake) used in this application effectively prevents leakage current at the silicon film edges, ensuring wafer safety and reliability.

[0083] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0084] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating DSOI wafers for pseudo-MOS characterization, characterized in that, The method includes: Provides multiple original wafers; The corresponding bottom layer wafer and top layer wafer are respectively prepared using the original wafer; Using the bottom wafer and the top wafer, a double buried oxide insulator-on-silicon (DSOI) wafer with a pseudo-MOS characterization structure was fabricated. The process of preparing the corresponding bottom wafer using the original wafer includes: The original wafer is used to prepare the corresponding first intermediate wafer and second intermediate wafer respectively; A third intermediate wafer is prepared using the first intermediate wafer and the second intermediate wafer; The third intermediate wafer is etched and metal is deposited to obtain a bottom wafer with a substrate electrode. The process of fabricating the corresponding top-layer wafer using the original wafer includes: The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a second processed wafer; The excess upper layer wafer on the second processed wafer is cut off using a layer transfer process to obtain the top layer wafer; The DSOI wafer with the pseudo-MOS characterization structure is subjected to step-by-step etching and metal electrode etching to obtain a DSOI wafer with multiple metal electrodes for pseudo-MOS characterization. The process of fabricating a double buried oxide insulator-on-insulator (DSOI) wafer with a pseudo-MOS characterization structure using the bottom wafer and the top wafer includes: The top wafer is flipped over and bonded to the bottom wafer to obtain a third bonded wafer; The excess upper layer wafer on the third bonding wafer is cut off by a layer transfer process to obtain the double buried oxide insulator silicon-on-insulator wafer with pseudo-MOS characterization structure. The step of preparing the corresponding first intermediate wafer using the original wafer includes: Electrode etching and metal deposition are performed on the two original wafers respectively to obtain a first etched wafer and a second etched wafer with substrate electrodes; The first etched wafer is flipped over and bonded to the second etched wafer to obtain the first bonded wafer; The first bonding wafer is etched to expose the substrate electrode on the first bonding wafer; Silicon dioxide is grown on the substrate electrode exposed on the first bonding wafer to prepare the first intermediate wafer; The step of preparing a corresponding second intermediate wafer using the original wafer includes: The original wafer is subjected to thermal oxidation and hydrogen implantation to obtain a first processed wafer; The first processed wafer is subjected to electrode etching and metal deposition to obtain a second intermediate wafer with metal electrodes; The step of preparing a third intermediate wafer using the first intermediate wafer and the second intermediate wafer includes: The second intermediate wafer is flipped over and bonded to the first intermediate wafer to obtain a second bonded wafer; The excess upper layer wafer on the second bonding wafer is cut off using a layer transfer process to obtain the remaining first cut wafer; Silicon dioxide is grown on the first diced wafer to obtain the third intermediate wafer.

2. The method according to claim 1, characterized in that, The DSOI wafer used for pseudo-MOS characterization comprises, from bottom to top, a substrate Sub, a second buried oxide layer BOX2, a second silicon film SOI2, a first buried oxide layer BOX1, and a first silicon film SOI1, wherein the substrate Sub, the second buried oxide layer BOX2, the second silicon film SOI2, and the first buried oxide layer BOX1 are provided by fabricating the bottom wafer, and the first silicon film SOI1 is provided by fabricating the top wafer.

3. The method according to claim 2, characterized in that, By combining different metal electrodes on the DSOI wafer used for pseudo-MOS characterization, interface characteristic parameters of the corresponding interfaces are characterized.

4. The method according to claim 1, characterized in that, The method further includes: fabricating a DSOI device with a pseudo-MOS characterization structure on the DSOI wafer used for pseudo-MOS characterization.

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