Semiconductor structure and preparation method thereof

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same, comprising providing a stacked structure comprising a first chip and a second chip; forming a through-silicon via (TSV) within the stacked structure, comprising a first portion and a second portion connected to the first portion, wherein the sidewalls of the first portion are vertical sidewalls and the sidewalls of the second portion are inclined sidewalls; forming an insulating layer on the sidewalls of the first portion; and forming a conductive layer within the TSV. The semiconductor structure and method for manufacturing the same provided herein form a TSV that penetrates the second chip and a portion of the first chip, and forms a conductive layer within the TSV. This allows electrical connection between the metal layers within the first and second chips without requiring additional conductive structures, thereby simplifying the semiconductor structure and process steps. Furthermore, because the sidewalls of the second portion are inclined, it is convenient to form an insulating layer only on the sidewalls of the first portion, simplifying the process steps and reducing costs.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] The TSV (Through Silicon Via) process is a high-density packaging technology that is gradually replacing the more mature wire bonding technology and is considered a fourth-generation packaging technology. Through-silicon via technology achieves vertical electrical interconnection through silicon vias by filling them with conductive materials such as copper, tungsten, and polysilicon. This allows signals to be transmitted from one side of a chip to the other, and by combining it with chip stacking technology, it enables three-dimensional integration of multi-layer chips. Through vertical interconnection, TSV technology can effectively shorten the length of interconnect lines between chips and reduce signal latency, thereby improving the signal transmission performance and operating frequency of electronic systems, increasing bandwidth, and achieving miniaturization of device integration. It is an important direction for the future development of semiconductor technology.

[0003] The TSV process primarily involves deep silicon etching to form micropores, deposition of insulating / barrier / seed layers, deep hole filling, chemical mechanical polishing, thinning, pad (bonding pad) fabrication, and redistribution line preparation. Traditionally, the TSV process involves fabricating TSVs on the front side of the chip, establishing electrical connections with metal interconnects on the front side, and then thinning the semiconductor chip to allow TSV electrodes to be routed to the backside of the chip.

[0004] However, using the traditional TSV process, the TSV is only located in one chip. When two or more chips are bonded together, additional conductive structures (such as solder balls, conductive bumps, etc.) are required to electrically connect adjacent chips, which makes the structure and manufacturing process relatively complex. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof that can realize metal interconnection without additional solder balls to address the problems in the above background technology.

[0006] To achieve the above objectives, the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0007] A stacked structure is provided; the stacked structure includes a first chip and a second chip, the second chip is bonded face-to-face on the first chip, and the first chip and the second chip each include a substrate, a dielectric layer located on the substrate, and a metal layer located within the dielectric layer;

[0008] A through-silicon via (TSV) is formed in the stacked structure; the TSV includes a first portion and a second portion connected to the first portion, the first portion penetrating the substrate of the second chip and having vertical sidewalls; the second portion penetrating the metal layer of the second chip and at least a portion of the metal layer in the first chip, the second portion having inclined sidewalls, and a width of the second portion at the bottom being smaller than a width of the second portion at the top;

[0009] forming an insulating layer on sidewalls of the first portion;

[0010] A conductive layer is formed in the through silicon via, and the conductive layer is electrically connected to the metal layer penetrating the first chip and the second chip.

[0011] In one embodiment, the first chip and the second chip further include a pad, and the pad is located on a side of the metal layer away from the substrate; the through silicon via also penetrates the pad in the first chip and the pad in the second chip.

[0012] In one embodiment, forming an insulating layer on the sidewall of the first portion includes:

[0013] forming an insulating material layer on the sidewall and bottom of the through silicon via;

[0014] The insulating material layer located on the sidewall and bottom of the second portion is removed by a dry etching process, and the insulating material layer remaining on the sidewall of the first portion is the insulating layer.

[0015] In one embodiment, the sidewall of the second portion is inclined at an angle of 60° to 80° relative to the substrate surface.

[0016] In one embodiment, the depth of the through silicon via is 50 μm to 100 μm, and the width of the through silicon via is 2 μm to 10 μm.

[0017] In one embodiment,

[0018] Providing a laminated structure includes:

[0019] providing the first chip;

[0020] Providing the second chip, and bonding the second chip face-to-face to the first chip;

[0021] The forming of a through silicon via in the stacked structure includes:

[0022] The first chip and the second chip are etched by an etching process to form the through silicon via.

[0023] In one embodiment, the second chip is bonded to the first chip via a bonding layer; and the through-silicon via also penetrates the bonding layer.

[0024] In one embodiment, forming a conductive layer in the through silicon via includes:

[0025] forming a metal barrier layer on the surface of the insulating layer, the sidewalls and the bottom of the second portion;

[0026] A filling conductive layer is formed on the surface of the metal barrier layer, and the filling conductive layer fills the through silicon via.

[0027] The present application also provides a semiconductor structure, comprising:

[0028] A stacked structure comprising a first chip and a second chip, wherein the second chip is bonded face-to-face to the first chip, and each of the first chip and the second chip comprises a substrate, a dielectric layer on the substrate, and a metal layer within the dielectric layer;

[0029] A through-silicon via (TSV), the TSV comprising a first portion and a second portion communicating with the first portion, the first portion penetrating the substrate of the second chip and having vertical sidewalls; the second portion penetrating the metal layer of the second chip and at least a portion of the metal layer in the first chip, the second portion having inclined sidewalls, and a width at a bottom of the second portion being smaller than a width at a top of the second portion;

[0030] an insulating layer located on a side wall of the first portion;

[0031] A conductive layer is located in the through silicon via and fills the through silicon via. The conductive layer is electrically connected to the metal layer penetrating the first chip and the second chip.

[0032] In one embodiment, the first chip and the second chip further include a pad, and the pad is located on a side of the metal layer away from the substrate; the through silicon via also penetrates the pad in the first chip and the pad in the second chip.

[0033] In one embodiment, the sidewall of the second portion is inclined at an angle of 60° to 80° relative to the substrate surface.

[0034] In one embodiment, the through silicon via has a depth of 50 μm to 100 μm and a width of 2 μm to 10 μm.

[0035] In one embodiment, it is characterized by further comprising a bonding layer, wherein the bonding layer is located between the first chip and the second chip and contacts the dielectric layer of the first chip and the dielectric layer of the second chip.

[0036] In one embodiment, the conductive layer comprises:

[0037] a metal barrier layer located on the surface of the insulating layer and the sidewalls and bottom of the second portion;

[0038] The filling conductive layer is located on the surface of the metal barrier layer and fills the through silicon via.

[0039] In one embodiment, the metal barrier layer includes a tantalum layer; and the insulating layer includes a pad oxide layer.

[0040] The preparation method of the semiconductor structure in the present application forms a silicon via that penetrates the second chip and part of the first chip, and forms a conductive layer in the silicon via. Without the need for an additional conductive structure, electrical connection between the metal layers in the first chip and the second chip can be achieved, which can simplify the semiconductor structure and process steps. At the same time, since the side wall of the second part is an inclined side wall, it is convenient to form an insulating layer only on the side wall of the first part, simplifying the process steps and reducing costs.

[0041] The semiconductor structure in the present application can achieve electrical connection between the metal layers in the first chip and the second chip through silicon vias that penetrate the second chip and part of the first chip, as well as the conductive layer located in the silicon vias, without the need for additional conductive structures, thereby simplifying the semiconductor structure and process steps; at the same time, since the side walls of the second part are inclined side walls, it is convenient to form an insulating layer only on the side walls of the first part, simplifying the process steps and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic cross-sectional view of a semiconductor structure;

[0044] Figure 2 This is a flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0045] Figure 3This is a schematic cross-sectional view of the structure obtained in step S1 of the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0046] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S2 of the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0047] Figure 5 This is a flow chart of step S3 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0048] Figure 6 Schematic cross-sectional view of the structure obtained in step S301 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0049] Figure 7 1 is a schematic cross-sectional view of the structure obtained in step S302 in the method for preparing a semiconductor structure provided in one embodiment of the present application, and is also a schematic cross-sectional view of the structure obtained in step S3;

[0050] Figure 8 1 is a schematic cross-sectional view of a structure obtained in step S4 of a method for preparing a semiconductor structure provided in one embodiment of the present application, and is also a schematic structural view of a semiconductor structure provided in another embodiment of the present application;

[0051] Figure 9 This is a flow chart of step S4 in the method for preparing a semiconductor structure provided in an embodiment of the present application.

[0052] Description of reference numerals:

[0053] 11. First chip; 111. Substrate; 112. Dielectric layer; 113. Metal layer; 114. Pad; 12. Second chip; 13. Through-silicon via; 131. First portion; 132. Second portion; 14. Insulation layer; 15. Conductive layer; 16. Bonding layer; 17. Solder ball; 401. Insulation material layer; DETAILED DESCRIPTION

[0054] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first or second may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first chip may be referred to as the second chip, and similarly, the second chip may be referred to as the first chip; the first chip and the second chip are different chips.

[0057] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the invention.

[0060] A conventional semiconductor structure such as Figure 1 As shown, a conventional semiconductor structure includes a stacked structure, a through-silicon via (TSV) 13', an insulating layer 14', and a conductive layer 15'. The stacked structure includes a first chip 11' and a second chip 12'. The second chip 12' is bonded face-to-face to the first chip 11' via a bonding layer 16'. Both the first chip 11' and the second chip 12' include a substrate 111', a dielectric layer 112' located on the substrate 111', and a metal layer 113' located within the dielectric layer 112'. The TSV 13' penetrates the substrate 111' and the dielectric layer 112' of the second chip 12'. The insulating layer 14' is located on the sidewalls of the first portion 131'. The conductive layer 15' is located in the through silicon via 13' and fills the through silicon via 13'. The conductive layer 15' is electrically connected to the metal layer 113' that penetrates the first chip 11' and the second chip 12'. Figure 1 As shown, in a conventional semiconductor structure, the through silicon via 13 ′ is only located in the second chip 12 ′, and therefore additional solder balls 17 ′ are required to establish metal interconnections, which complicates the manufacturing process.

[0061] See also Figure 2 , the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0062] S1: Providing a stacked structure; the stacked structure includes a first chip and a second chip, the second chip is bonded face-to-face on the first chip, and the first chip and the second chip each include a substrate, a dielectric layer located on the substrate, and a metal layer located within the dielectric layer;

[0063] S2: forming a through-silicon via (TSV) in the stacked structure; the TSV includes a first portion and a second portion communicating with the first portion, the first portion penetrating the substrate of the second chip, and having vertical sidewalls; the second portion penetrating the metal layer of the second chip and at least a portion of the metal layer in the first chip, the second portion having inclined sidewalls, and a width of a bottom portion of the second portion being smaller than a width of a top portion of the second portion;

[0064] S3: forming an insulating layer on the sidewall of the first portion;

[0065] S4: forming a conductive layer in the through silicon via, the conductive layer being electrically connected to the metal layer penetrating the first chip and the second chip.

[0066] The preparation method of the semiconductor structure provided in the present application forms a silicon-through via (TSV) penetrating the second chip and part of the first chip, and forms a conductive layer in the TSV. This allows electrical connection between the metal layers in the first chip and the second chip to be achieved without the need for an additional conductive structure, thereby simplifying the semiconductor structure and reducing the number of process steps. At the same time, since the sidewalls of the second portion are inclined sidewalls, it is convenient to form an insulating layer only on the sidewalls of the first portion, simplifying the process steps and reducing costs. In addition, by bonding the second chip face-to-face to the first chip, the resulting structure also has the advantages of high precision, a small volume occupied by the formed stacked structure, a high I / O (Input / Output) density, short interconnects, and small lead parasitic parameters.

[0067] Optionally, the first chip and the second chip may be bonded together using a wafer-level packaging process, such as WOW (wafer on wafer) or COW (chip on wafer), or a chip-scale packaging (CSP) process.

[0068] Optionally, in the preparation methods provided in some embodiments, the inclination angle of the side wall of the second part compared to the substrate surface can be 60° to 80°, such as 60°, 65°, 70°, 75° or 80°, etc.; in the preparation methods provided in some embodiments, the depth of the silicon via can be 50μm to 100μm, such as 50μm, 65μm, 80μm or 100μm, etc.; in the preparation methods provided in some embodiments, the width of the silicon via can be 2μm to 10μm, such as 2μm, 4μm, 6μm, 8μm or 10μm, etc.; the preparation method of the semiconductor structure provided in the present application does not limit the specific size of the inclination angle of the side wall of the second part compared to the substrate surface, the depth of the silicon via and the width of the silicon via.

[0069] In step S1, see Figure 2 S1 and Figure 3 , providing a stacked structure; the stacked structure includes a first chip 11 and a second chip 12, the second chip 12 is bonded face to face on the first chip 11, and the first chip 11 and the second chip 12 both include a substrate 111, a dielectric layer 112 located on the substrate 111, and a metal layer 113 located in the dielectric layer 112.

[0070] Please continue reading Figure 3 In one embodiment, step S1 may include the following steps:

[0071] Providing the first chip 11;

[0072] A second chip 12 is provided, and the second chip 12 is bonded face-to-face on the first chip 11 .

[0073] In one embodiment, the substrate 111 may include but is not limited to a silicon substrate, a silicon nitride substrate, or a silicon oxynitride substrate, etc.; the dielectric layer 112 may include but is not limited to a silicon dioxide layer or a silicon nitride layer. This application does not limit the materials of the substrate 111 and the dielectric layer 112.

[0074] Specifically, the dielectric layer 112 may be located on the front side of the substrate 111. The so-called "face to face" means that after the second chip 12 is bonded to the first chip 11, the dielectric layer 112 in the second chip 12 is bonded to the dielectric layer 112 in the first chip 11; Figure 3 As shown, the first chip 11 may be bonded to the first chip 11 with its front side facing upward, and the second chip 12 may be bonded to the first chip 11 with its front side facing downward.

[0075] Please continue reading Figure 3 In one embodiment, the first chip 11 and the second chip 12 may also include a pad 114, and the pad 114 is located on the side of the metal layer 113 away from the substrate 111; in the above embodiment, the silicon through via 13 also passes through the pad 114 in the first chip 11 and the pad 114 in the second chip 12.

[0076] In one embodiment, through holes (not shown) may be reserved in the metal layer 113 and the pad 114 . The through holes correspond to the subsequently formed through silicon vias 13 and become part of the through silicon vias 13 after the through silicon vias 13 are formed.

[0077] The method for preparing the semiconductor structure provided in the above embodiment can reserve a through hole in the metal layer 113 and the pad 114. After forming 112 covering the metal layer 113 and the pad 114, the reserved through hole will be filled with the dielectric layer 112. In this way, in the subsequent process of forming the through silicon via 13, the etching steps after etching the substrate 111 are all for etching the dielectric layer 112, and there will be no alternating etching of the dielectric layer 112 and the metal layer 113 or the pad 114, which can simplify the process steps and improve production efficiency.

[0078] Optionally, the pad 114 may include but is not limited to a copper pad, and the present application does not limit the material of the pad 114 .

[0079] In step S2, see Figure 2 S2 and Figure 4, a through silicon via 13 is formed in the stacked structure; the through silicon via 13 includes a first portion 131 and a second portion 132 connected to the first portion 131, the first portion 131 passes through the substrate 111 of the second chip 12, and the sidewall of the first portion 131 is a vertical sidewall; the second portion 132 passes through the metal layer 113 of the second chip 12 and passes through at least a portion of the metal layer 113 in the first chip 11, the sidewall of the second portion 132 is an inclined sidewall, and the width of the bottom of the second portion 132 is less than the width of the top of the second portion 132.

[0080] Please continue reading Figure 4 In one embodiment, step S2 may include the following steps:

[0081] The first chip 11 and the second chip 12 are etched by an etching process to form through silicon vias 13 .

[0082] Please continue reading Figure 4 In one embodiment, the second chip 12 may be bonded to the first chip 11 via the bonding layer 16 ; in the above embodiment, the through silicon via 13 may also penetrate the bonding layer 16 .

[0083] In one embodiment, the bonding layer 16 may include but is not limited to an aluminum / copper composite layer. The present application does not limit the material and structure of the bonding layer 16 .

[0084] Because the operating environment maintains a high temperature, traditional aluminum wire becomes a bottleneck that limits system performance stability. Compared to aluminum, copper has better thermal and electrical conductivity and a lower electrothermal expansion coefficient. However, copper wire bonding is difficult for semiconductors. The semiconductor structure fabrication method provided in the above embodiment uses an aluminum / copper composite layer as the bonding layer 16. Aluminum provides good bonding, while copper offers excellent electrical, mechanical, and thermal properties.

[0085] In one embodiment, the step of etching the first chip 11 and the second chip 12 using an etching process to form the through silicon via 13 may include etching the first chip 11 and the second chip 12 using a dry etching process to form the through silicon via 13 .

[0086] In one embodiment, after using a dry etching process to etch the first chip 11 and the second chip 12 to form the through-silicon via 13, it may also include using a wet etching process to etch the stacked structure to widen the width of the through-silicon via 13 to ensure that the pads 114 in the first chip 11 and the second chip 12 are fully exposed.

[0087] In step S3, see Figure 2 S3 and Figures 5 to 7 , an insulating layer 14 is formed on the sidewall of the first portion 131 .

[0088] like Figure 5 As shown, in one embodiment, step S3 may include the following steps:

[0089] S301: forming an insulating material layer 401 on the sidewall and bottom of the through silicon via 13, such as Figure 6 As shown;

[0090] S302: Remove the insulating material layer 401 on the sidewall and bottom of the second portion 132, and the insulating material layer 401 remaining on the sidewall of the first portion 131 is the insulating layer 14. Figure 7 shown.

[0091] In the method for preparing the semiconductor structure provided by the above embodiment, since the sidewalls of the second part are inclined sidewalls, the insulating material layer located on the sidewalls and bottom of the second part can be directly removed to form an insulating layer only on the sidewalls of the first part, so that the resulting structure can directly form an electrical connection between the metal layers in the first chip and the second chip through the conductive layer located in the silicon through-via, without the need for additional solder balls or wiring, thereby simplifying the process steps and reducing costs.

[0092] In one embodiment, the insulating material layer 401 may include but is not limited to an oxide layer. The present application does not limit the structure and material of the insulating material layer 401 .

[0093] In step S302, refer to Figure 5 S302 and Figure 7 , the insulating material layer 401 located on the sidewall and bottom of the second portion 132 is removed, and the insulating material layer 401 remaining on the sidewall of the first portion 131 is the insulating layer 14 .

[0094] In one embodiment, the insulating material layer 401 located on the sidewall and bottom of the second portion 132 may be removed by, but is not limited to, a dry etching process.

[0095] In one embodiment, after step S302 , a wet etching process may be further used to etch the stacked structure to widen the width of the through silicon via 13 , ensuring that the pads 114 in the first chip 11 and the second chip 12 are fully exposed.

[0096] In step S4, see Figure 2 S4 and Figures 8 and 9 A conductive layer 15 is formed in the through silicon via 13 , and the conductive layer 15 is electrically connected to the metal layer 113 penetrating the first chip 11 and the second chip 12 .

[0097] like Figure 9 As shown, in one embodiment, step S4 may include the following steps:

[0098] S401: forming a metal barrier layer on the surface of the insulating layer 14 and the sidewall and bottom of the second portion 132;

[0099] S402 : forming a filling conductive layer 15 on the surface of the metal barrier layer, wherein the filling conductive layer 15 fills the through silicon via 13 .

[0100] It should be understood that although Figure 2 、 5 The steps in the flowchart of FIG. 9 are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 、 5 At least part of the steps in 9 may include multiple steps or multiple stages. These steps or stages do not necessarily have to be performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0101] Please continue reading Figure 8 The present application also provides a semiconductor structure, including a stacked structure, a through silicon via 13, an insulating layer 14 and a conductive layer 15; wherein the stacked structure includes a first chip 11 and a second chip 12; wherein the second chip 12 is bonded face-to-face on the first chip 11, and the first chip 11 and the second chip 12 both include a substrate 111, a dielectric layer 112 located on the substrate 111 and a metal layer 113 located within the dielectric layer 112; the through silicon via 13 includes a first portion 131 and a second portion 132 connected to the first portion 131; wherein the first portion 131 passes through the second portion 132; The substrate 111 of the chip 12, and the sidewalls of the first part 131 are vertical sidewalls; the second part 132 penetrates the metal layer 113 of the second chip 12 and penetrates at least part of the metal layer 113 in the first chip 11, the sidewalls of the second part 132 are inclined sidewalls, and the width of the bottom of the second part 132 is less than the width of the top of the second part 132; the insulating layer 14 is located on the sidewalls of the first part 131; the conductive layer 15 is located in the silicon through-hole 13 and fills the silicon through-hole 13, and the conductive layer 15 is electrically connected to the metal layer 113 penetrating the first chip 11 and the second chip 12.

[0102] The semiconductor structure in the present application can achieve electrical connection between the metal layers in the first chip and the second chip through silicon vias that penetrate the second chip and part of the first chip, as well as the conductive layer located in the silicon vias, without the need for additional conductive structures, thereby simplifying the semiconductor structure and reducing the process steps. At the same time, since the side walls of the second part are inclined side walls, it is convenient to form an insulating layer only on the side walls of the first part, simplifying the process steps and reducing costs.

[0103] In one embodiment, the substrate 111 may include but is not limited to a silicon substrate, a sapphire substrate, a silicon nitride substrate, or a silicon oxynitride substrate, etc.; the dielectric layer 112 may include but is not limited to a silicon dioxide layer or a silicon nitride layer. This application does not limit the materials of the substrate 111 and the dielectric layer 112.

[0104] Please continue reading Figure 8 In one embodiment, the first chip 11 and the second chip 12 may each further include a pad 114. Specifically, the pad 114 may be located on a side of the metal layer 113 away from the substrate 111. The pad 114 may include, but is not limited to, a copper pad. The present application does not limit the material of the pad 114.

[0105] On the basis of the above embodiment, the through silicon via 13 further passes through the pad 114 in the first chip 11 and the pad 114 in the second chip 12 .

[0106] Optionally, in the semiconductor structures provided in some embodiments, the inclination angle of the sidewall of the second part compared to the substrate surface can be 60° to 80°, such as 60°, 65°, 70°, 75° or 80°, etc.; in the semiconductor structures provided in some embodiments, the depth of the silicon via can be 50μm to 100μm, such as 50μm, 65μm, 80μm or 100μm, etc.; in the semiconductor structures provided in some embodiments, the width of the silicon via can be 2μm to 10μm, such as 2μm, 4μm, 6μm, 8μm or 10μm, etc.; the semiconductor structure provided in the present application does not limit the specific size of the inclination angle of the sidewall of the second part compared to the substrate surface, the depth of the silicon via and the width of the silicon via.

[0107] Please continue reading Figure 8 In one embodiment, the semiconductor structure may further include a bonding layer 16. Specifically, the bonding layer 16 is located between the first chip 11 and the second chip 12 and contacts the dielectric layer 112 of the first chip 11 and the dielectric layer 112 of the second chip 12. The bonding layer 16 may include, but is not limited to, an aluminum / copper composite layer. This application does not limit the material and structure of the bonding layer 16.

[0108] Because the operating environment maintains a high temperature, traditional aluminum wire becomes a bottleneck that limits system performance stability. Compared to aluminum, copper has better thermal and electrical conductivity and a lower electrothermal expansion coefficient. However, copper wire bonding is difficult for semiconductors. The semiconductor structure fabrication method provided in the above embodiment uses an aluminum / copper composite layer as the bonding layer 16. Aluminum provides good bonding, while copper offers excellent electrical, mechanical, and thermal properties.

[0109] In one embodiment, the conductive layer 15 may include a metal barrier layer and a filling conductive layer; wherein the metal barrier layer is located on the surface of the insulating layer, the sidewall and the bottom of the second portion; and the filling conductive layer is located on the surface of the metal barrier layer and fills the through silicon via 13 .

[0110] In one embodiment, the metal barrier layer may include but is not limited to a tantalum layer, a metal barrier layer of other materials, or a stacked structure thereof. The present application does not limit the material and form of the metal barrier layer.

[0111] In one embodiment, the insulating layer 14 may include but is not limited to a pad oxide layer.

[0112] Specifically, in some embodiments, the pad oxide layer may include but is not limited to a silicon dioxide layer or other oxide layers. The present application does not limit the structure and material of the pad oxide layer.

[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: A stacked structure is provided; the stacked structure includes a first chip and a second chip, the second chip is bonded face-to-face on the first chip, and the first chip and the second chip each include a substrate, a dielectric layer located on the substrate, and a metal layer located within the dielectric layer; A through-silicon via (TSV) is formed in the stacked structure; the TSV includes a first portion and a second portion connected to the first portion, the first portion penetrating the substrate of the second chip and having vertical sidewalls; the second portion penetrating the metal layer of the second chip and at least a portion of the metal layer in the first chip, the second portion having inclined sidewalls, and a width of the second portion at the bottom being smaller than a width of the second portion at the top; forming an insulating layer on sidewalls of the first portion; forming a conductive layer in the through silicon via, wherein the conductive layer is electrically connected to the metal layer penetrating the first chip and the second chip; Wherein, forming an insulating layer on the sidewall of the first portion includes: forming an insulating material layer on the sidewall and bottom of the through silicon via; The insulating material layer located on the sidewall and bottom of the second portion is removed by a dry etching process, and the insulating material layer remaining on the sidewall of the first portion is the insulating layer.

2. The preparation method according to claim 1, characterized in that The first chip and the second chip also include a pad, and the pad is located on a side of the metal layer away from the substrate; the through silicon via also passes through the pad in the first chip and the pad in the second chip.

3. The preparation method according to claim 1, characterized in that The sidewall of the second portion is inclined at an angle of 60° to 80° relative to the substrate surface.

4. The preparation method according to claim 1, characterized in that The depth of the through silicon via is 50 μm to 100 μm, and the width of the through silicon via is 2 μm to 10 μm.

5. The preparation method according to claim 1, characterized in that Providing a laminated structure includes: providing the first chip; Providing the second chip, and bonding the second chip face-to-face to the first chip; The forming of a through silicon via in the stacked structure includes: The first chip and the second chip are etched by an etching process to form the through silicon via.

6. The preparation method according to claim 5, characterized in that The second chip is bonded to the first chip via a bonding layer; the through silicon via also passes through the bonding layer.

7. The preparation method according to any one of claims 1 to 6, characterized in that The forming of a conductive layer in the through silicon via comprises: forming a metal barrier layer on the surface of the insulating layer, the sidewalls and the bottom of the second portion; A filling conductive layer is formed on the surface of the metal barrier layer, and the filling conductive layer fills the through silicon via.

8. A semiconductor structure, characterized in that include: A stacked structure comprising a first chip and a second chip, wherein the second chip is bonded face-to-face to the first chip, and each of the first chip and the second chip comprises a substrate, a dielectric layer on the substrate, and a metal layer within the dielectric layer; A through-silicon via (TSV), the TSV comprising a first portion and a second portion communicating with the first portion, the first portion penetrating the substrate of the second chip and having vertical sidewalls; the second portion penetrating the metal layer of the second chip and at least a portion of the metal layer in the first chip, the second portion having inclined sidewalls, the width of the bottom of the second portion being smaller than the width of the top of the second portion, and the width of the bottom of the first portion being smaller than the width of the top of the second portion; an insulating layer located on a side wall of the first portion; A conductive layer is located in the through silicon via and fills the through silicon via. The conductive layer is electrically connected to the metal layer penetrating the first chip and the second chip.

9. The semiconductor structure according to claim 8, wherein: The first chip and the second chip also include a pad, and the pad is located on a side of the metal layer away from the substrate; the through silicon via also passes through the pad in the first chip and the pad in the second chip.

10. The semiconductor structure according to claim 8, wherein: The sidewall of the second portion is inclined at an angle of 60° to 80° relative to the substrate surface.

11. The semiconductor structure according to claim 9, wherein: The depth of the through silicon via is 50 μm to 100 μm, and the width of the through silicon via is 2 μm to 10 μm.

12. The semiconductor structure according to claim 8, wherein: The system further includes a bonding layer, which is located between the first chip and the second chip and contacts the dielectric layer of the first chip and the dielectric layer of the second chip.

13. The semiconductor structure according to any one of claims 8 to 12, characterized in that The conductive layer comprises: a metal barrier layer located on the surface of the insulating layer and the sidewalls and bottom of the second portion; The filling conductive layer is located on the surface of the metal barrier layer and fills the through silicon via.

14. The semiconductor structure according to claim 13, wherein: The metal barrier layer includes a tantalum layer; and the insulating layer includes a pad oxide layer.

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