Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, including: providing a substrate, on which a dielectric stacking layer including at least two dielectric layers of different materials is formed; forming an opening penetrating the dielectric stacking layer; forming a filling film layer, which is formed of the same material and fills the opening; forming an insulating layer and a conductive layer embedded in the insulating layer; etching the substrate to form a through silicon via; etching the filling film layer exposed by the through silicon via to form a dielectric through hole, wherein the conductive layer is exposed by the dielectric through hole. The present invention removes the portion of the dielectric stacking layer corresponding to the through silicon via position in advance to form an opening, and fills the opening with a single-layer filling film layer formed of the same material, that is, the portion of the dielectric stacking layer corresponding to the through silicon via position is converted from a multi-layer film structure to a single structure in advance, so that the film layer structure of the dielectric through hole formed by subsequent etching is single, thereby improving the etching quality of the dielectric through hole and reducing the process defects of forming the dielectric through hole.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the preparation of integrated circuits develops towards ultra-large-scale integrated circuits, the density of the semiconductor device structure, that is, the integration of the devices, is getting larger and larger. As the number of semiconductor components contained in integrated circuit chips continues to increase, the available space for metal connections on the surface of the semiconductor structure is actually greatly reduced. The solution to this problem adopts a multi-layer metal wire design, which uses multiple layers of dielectric layers and conductive layers to overlap each other for multi-layer connections. Among them, it is necessary to etch a dielectric stack layer formed by multiple layers of different dielectric materials to prepare contact holes for interlayer metal interconnection. In addition, with the development of semiconductor technology, the structure of semiconductor devices has gradually diversified and complicated. In the process of preparing semiconductor devices, it also involves etching the interlayer dielectric layer formed by different dielectric materials to form semiconductor structures such as through holes and grooves.

[0003] TSV (Through Silicon Via) can vertically interconnect silicon wafers, greatly reducing the length of interconnection lines in stacked chips, improving chip integration density and bandwidth, and reducing system power consumption. It is widely used in 3D IC stacking processes. In some processes, the interconnection layer along the thickness direction of the chip is filled in the TSV in the silicon substrate and the TDV (Through Dielectric Via) in the multi-layer dielectric layer to achieve electrical connection with the metal layer in the lower film layer. On the basis of TSV, TDV is further formed along the thickness direction. TSV is a deep hole silicon structure. The formation of TDV requires etching of multiple layers of different dielectric materials, which has high requirements for the etching process. The etching rate and etching gas corresponding to different dielectric materials are also different. The formed TDV is prone to bottom side digging, by-products are difficult to remove (such as polymer residues), the bottom is not etched to reveal the metal layer, and the machine sparks and produces arcs and other high-risk problems, which seriously restrict the TDV process. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which improves the TDV etching quality and reduces the process defects of forming a dielectric through hole.

[0005] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, on which a dielectric stack layer including at least two dielectric layers of different materials is formed;

[0007] forming an opening penetrating the dielectric stack;

[0008] forming a filling film layer, wherein the filling film layer is formed of the same material and fills the opening;

[0009] forming an insulating layer and a conductive layer embedded in the insulating layer, wherein the insulating layer covers the filling film layer and the dielectric stack layer, and a projection of the conductive layer on the substrate at least partially overlaps with a projection of the opening on the substrate;

[0010] Etching the substrate at a position corresponding to the opening to form a through silicon via; and

[0011] The filling film layer in the opening exposed by the through silicon via is further etched to form a dielectric through hole, wherein the dielectric through hole exposes the conductive layer.

[0012] Furthermore, in a cross section perpendicular to the substrate, a cross-sectional width of the dielectric through hole is smaller than a cross-sectional width of the opening.

[0013] Furthermore, the material of the filling film layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, phosphosilicate glass and polymer materials.

[0014] Furthermore, the filling film layer is formed by any one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0015] Furthermore, the dielectric stack layer includes any two or more different materials selected from silicon dioxide, silicon nitride, carbon-containing silicon nitride and low dielectric constant materials.

[0016] Furthermore, after forming the insulating layer and the conductive layer and before forming the through silicon via, the method further includes:

[0017] Bonding a side of the insulating layer away from the dielectric stack layer to a substrate;

[0018] The side of the substrate away from the dielectric stack layer is thinned.

[0019] Furthermore, the dielectric through hole is formed by dry etching, and the etching gas includes a fluorine-based gas.

[0020] Furthermore, the dielectric stack layer includes a first dielectric layer, a second dielectric layer to an nth dielectric layer sequentially covering the substrate.

[0021] Furthermore, the material of the nth dielectric layer includes any one of SiNx, SiOx, Al2O3, AlN, HfO2, HfSiO, HfSiON and SiNO; the material of the second dielectric layer includes any one of SiNx, Al2O3, AlN, HfO2, SiOx, HfTiO, HfSiO, HfSiON, Sc2O3, Ga2O3, MgO and SiNO; the material of the first dielectric layer includes any one of SiOx, SiNx, Al2O3, HfO2 and SiNO.

[0022] Furthermore, the production method also includes:

[0023] forming an isolation layer, wherein the isolation layer covers the sidewalls of the through silicon via and the dielectric through hole;

[0024] An interconnection layer is formed, wherein the interconnection layer covers the isolation layer, fills the through silicon via and the dielectric via, and is electrically connected to the conductive layer.

[0025] The present invention also provides a semiconductor device, comprising:

[0026] A substrate having a dielectric stack layer formed thereon, comprising at least two dielectric layers of different materials;

[0027] An opening, wherein the opening penetrates the dielectric stack layer;

[0028] A through silicon via, wherein the through silicon via penetrates the substrate corresponding to the opening;

[0029] A dielectric through hole, wherein the dielectric through hole is formed by etching the through silicon via to expose a filling film layer filled in the opening, and the filling film layer is made of the same material; when forming the dielectric through hole, the filling film layer remaining on the side wall of the opening is etched as a protective layer;

[0030] An insulating layer and a conductive layer embedded in the insulating layer, the insulating layer covers the protective layer and the dielectric stack layer, the projection of the conductive layer on the substrate at least partially overlaps with the projection of the opening on the substrate; the dielectric through hole exposes the conductive layer.

[0031] Furthermore, the semiconductor device further comprises:

[0032] an isolation layer, wherein the isolation layer covers the sidewalls of the through silicon via and the dielectric through hole;

[0033] An interconnection layer covers the isolation layer and fills the through silicon via and the dielectric via and is electrically connected to the conductive layer.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention provides a semiconductor device and a manufacturing method thereof, comprising: providing a substrate, on which a dielectric stacking layer including at least two dielectric layers of different materials is formed; forming an opening penetrating the dielectric stacking layer; forming a filling film layer, wherein the filling film layer is formed of the same material and fills the opening; forming an insulating layer and a conductive layer embedded in the insulating layer, wherein the insulating layer covers the filling film layer and the dielectric stacking layer, and the projection of the conductive layer on the substrate at least partially overlaps with the projection of the opening on the substrate; etching the substrate corresponding to the opening to form a silicon through hole; and further etching the filling film layer exposed by the silicon through hole and located in the opening to form a dielectric through hole, wherein the dielectric through hole exposes the conductive layer. The present invention removes the portion of the dielectric stack layer corresponding to the TSV position in advance to form an opening, and fills the opening with a single-layer filling film layer formed of the same material, that is, the portion of the dielectric stack layer corresponding to the TSV position is converted from a multi-layer film structure (a dielectric stack layer including at least two dielectric layers of different materials) into a single structure (a single-layer filling film layer) in advance, so that the film layer structure of the subsequent etching to form the dielectric through hole (TDV) is single, the etching quality of the dielectric through hole is improved, and process defects such as bottom side digging, difficulty in removing by-products (such as polymer residues), bottom failure to open, and arcing caused by machine sparking are reduced or even avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0037] Figure 2 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention after providing a substrate.

[0038] Figure 3 The schematic diagram is a schematic diagram of a method for manufacturing a semiconductor device after forming an opening according to an embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the method for manufacturing a semiconductor device after forming a filling film layer according to an embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the method for manufacturing a semiconductor device according to an embodiment of the present invention after forming an insulating layer and a conductive layer.

[0041] Figure 6 It is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention after bonding with a substrate.

[0042] Figure 7 The schematic diagram is a semiconductor device manufacturing method according to an embodiment of the present invention after forming a through silicon via and a dielectric through via.

[0043] Figure 8 The schematic diagram is a schematic diagram of a method for manufacturing a semiconductor device after forming an interconnection layer according to an embodiment of the present invention.

[0044] The reference numerals are as follows:

[0045] 10-substrate; 20-dielectric stack layer; 21-first dielectric layer; 22-second dielectric layer; 2n-nth dielectric layer; K-opening; A-silicon via area; 30-filling film layer; 301-protective layer; 40-insulating layer; 41-conductive layer; 50-bonding layer; 60-base; 70-isolation layer; 80-interconnection layer. DETAILED DESCRIPTION

[0046] Based on the above research, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0047] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0048] The embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, including:

[0049] Step S1, providing a substrate, on which a dielectric stack layer including at least two dielectric layers made of different materials is formed;

[0050] Step S2, forming an opening penetrating the dielectric stack layer;

[0051] Step S3, forming a filling film layer, wherein the filling film layer is formed of the same material and fills the opening;

[0052] Step S4, forming an insulating layer and a conductive layer embedded in the insulating layer, wherein the insulating layer covers the filling film layer and the dielectric stack layer, and a projection of the conductive layer on the substrate at least partially overlaps with a projection of the opening on the substrate;

[0053] Step S5, etching the substrate corresponding to the opening to form a through silicon via; and

[0054] Step S6, further etching the filling film layer in the opening exposed by the through silicon via to form a dielectric through hole, wherein the dielectric through hole exposes the conductive layer.

[0055] Combine the following Figures 2 to 8 The steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention are introduced.

[0056] Step S1: Figure 2 As shown, a substrate is provided, on which a dielectric stack layer including at least two dielectric layers of different materials is formed; the substrate 10 may include semiconductor materials, and may be a single-layer structure or a multi-layer structure. The substrate 10 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. It may also include a layered substrate such as, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0057] The dielectric stack layer 20 may be a laminated dielectric layer formed of any two or more different materials including silicon dioxide, silicon nitride, carbon-containing silicon nitride and a low dielectric constant material. The dielectric constant of the low dielectric constant material is less than 2.8. Exemplarily, the low dielectric constant material is porous silicon, carbon-doped silicon oxide or silicon carbide.

[0058] The dielectric stack layer 20 is at least two dielectric layers, which can be two layers, three layers or more layers. The thickness of each material layer of the dielectric stack layer 20 can be the same or different. The dielectric stack layer 20 directly covers the surface of the substrate 10. The dielectric stack layer 20 is an interlayer dielectric layer, and the etched through hole is used to form a contact hole between the multi-layer metal interconnects.

[0059] In one embodiment, the dielectric stack layer 20 includes a stacked structure in which silicon dioxide, silicon nitride, carbon-containing silicon nitride, and a low dielectric constant material are stacked at any number of times and in any quantity, and the dielectric stack layer 20 covers the surface of the substrate 10, and can form a contact hole for metal interconnection on the surface of the substrate 10. The deposition of each material layer in the dielectric stack layer 20 can be achieved by a chemical vapor deposition method.

[0060] In another embodiment, the dielectric stack layer 20 includes a first dielectric layer 21, a second dielectric layer 22, and an nth dielectric layer that sequentially cover the surface of the substrate 10. The dielectric stack layer 20 covers the upper surface of the substrate 10 for preparing a semiconductor device structure. The nth dielectric layer 2n located at the top layer can be any one of SiNx, SiOx, Al2O3, AlN, HfO2, HfSiO, HfSiON, and SiNO. The second dielectric layer 22 can be any one of SiNx, Al2O3, AlN, HfO2, SiOx, HfTiO, HfSiO, HfSiON, Sc2O3, Ga2O3, MgO, and SiNO. The first dielectric layer 21 can be any one of SiOx, SiNx, Al2O3, HfO2, and SiNO.

[0061] Step S2: Figure 3 As shown, an opening K is formed penetrating the dielectric stack layer 20, and the projection of the opening K on the substrate 10 covers the projection of a through silicon via formed by subsequent etching of the substrate on the substrate 10. Specifically, the projection of the opening K on the substrate 10 covers the projection of the through silicon via region A on the substrate 10. The opening is formed by processes such as exposure, development, and etching.

[0062] Specifically, the surface of the dielectric stack layer 20 is covered with a photoresist material (not shown), and the photoresist material has a patterned window exposing the surface of the dielectric stack layer 20, which is used to perform the etching of the opening K of the dielectric stack layer 20. In this step, the photoresist material is a positive or negative photoresist, which is exposed by photolithography or plasma treatment to open a patterned window. Then, the dielectric stack layer 20 exposed by the patterned window is etched by dry and / or wet methods to form an opening K, and the opening K exposes the upper surface of the substrate 10. The dry etching method can be photoevaporation, vapor phase corrosion, sputtering and ion beam milling, plasma etching, high-pressure plasma etching, high-density plasma etching, reactive ion etching, inductively coupled plasma etching, etc. Specifically, the patterned photoresist material layer is used as a mask, and the excited etching gas may be a mixture of fluorocarbon gas, hydrocarbon or fluorinated hydrocarbon gas, and nitrogen and oxygen gas to generate plasma, so as to etch the dielectric stack layer 20 until the upper surface of the substrate 10 is exposed, and the dielectric stack layer 20 formed of different materials is etched by one plasma etching, wherein the nitrogen and oxygen gas flow rate may be 200sccm to 600sccm. Wet etching selects corresponding etching liquid for different materials of the dielectric layer. For example, when the dielectric layer material to be etched is Si3N4:SiO2, the etching liquid includes H3PO4 and H2O, the etching liquid temperature is 160℃ to 180℃, and the etching rate selection ratio is greater than 40. When the etched material is SiO2:AlN or SiO2:Al2O3, the etching liquid is BOE (NH4F:HF=5:1), the temperature is room temperature, and the etching rate selection ratio is greater than 100. By adjusting the composition, proportion and temperature of the etching solution, the corrosion rate can be controlled and the corrosion time can be further determined.

[0063] Step S3: Figure 4 As shown, a single-layer filling film layer 30 is formed. The filling film layer 30 can be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process, etc. The filling film layer 30 fills the opening and also covers the upper surface of the dielectric stack layer 20. The filling film layer 30 located on the upper surface of the dielectric stack layer 20 is planarized by a chemical mechanical polishing (CMP) process. The filling film layer 30 is a single-layer film structure formed of the same material. The material of the filling film layer 30 may include any one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, BPSG (boron phosphosilicate glass), PSG (phosphosilicate glass), and a polymer material.

[0064] Step S4: Figure 5 and Figure 6As shown, an insulating layer 40 and a conductive layer 41 embedded in the insulating layer 40 are formed, and the insulating layer 40 covers the filling film layer 30 and the dielectric stack layer 20. The conductive layer 41 can be made of any one of copper, tungsten or aluminum. The projection of the conductive layer 41 on the substrate 10 overlaps at least partially with the projection of the opening K on the substrate 10. Next, the semiconductor device after the insulating layer 40 and the conductive layer 41 are formed is flipped 180°, and the surface of one side of the insulating layer 40 away from the dielectric stack layer 20 is bonded to another substrate 60, and a bonding layer 50 is formed between the insulating layer 40 and the substrate 60. The substrate 60 can be a carrier wafer or a functional wafer (such as a logic wafer, etc.). The side of the substrate 10 away from the dielectric stack layer 20 is thinned. The insulating layer 40 and the substrate 60 can be stacked (bonded) by melt bonding, hybrid bonding, etc. The insulating layer 40 and the substrate 60 may also be temporarily bonded, for example, by bonding and fixing with an adhesive, and the adhesive may lose its viscosity under high temperature or ultraviolet irradiation to facilitate debonding. Figure 6 and Figure 7As shown, the substrate is etched at the opening K corresponding to the substrate to form the silicon through hole V1; and the filling film layer 30 located in the opening exposed by the silicon through hole V1 is further etched to form a dielectric through hole V2, and the dielectric through hole V2 exposes the conductive layer 41, and the silicon through hole V1 is connected to the dielectric through hole V2. In the cross section perpendicular to the substrate 10, the cross-sectional width of the dielectric through hole V2 is smaller than the cross-sectional width of the opening K, so as to ensure that only a single-layer filling film layer 30 structure is etched in the process of forming the dielectric through hole V2, and a partial thickness of the filling film layer 30 is retained on the side wall of the opening K as a protective layer 301. In this way, the side wall of the dielectric through hole V2 is composed of the protective layer 301 of the same material, and the dielectric stack layer 20 around the dielectric through hole V2 is covered or isolated by the protective layer 301, so as to avoid the problem of bubbles and uneven side walls when the dielectric stack layer 20 of different materials is exposed by etching the dielectric through hole V2. When the material of the filling film layer 30 is silicon dioxide, the reaction gas for etching the filling film layer 30 is mainly fluorine-based gas, such as CF4, SF6 and NF3. When reactive ions etch silicon dioxide, the fluorine atoms or chlorine atoms decomposed in the glow discharge react with the atoms on the surface of silicon dioxide to generate gaseous products, thereby achieving the purpose of etching. The mechanism of active ion etching is that carbon fluoride compounds form CF polymers on the surface of silicon dioxide materials. Under the action of energy provided by ion physical bombardment, CF polymers react with silicon dioxide materials to form volatile SiFx, which is extracted from the reaction chamber by the vacuum system. In order to achieve a higher etching rate, in addition to carbon fluoride gases with a high C / F ratio, some auxiliary gases, such as O2 and Ar, are also required. Under low pressure and high power conditions, energy is provided by high-energy Ar+ bombardment, and carbon fluoride gases and silicon dioxide materials to be etched react chemically. The oxygen ions generated by the decomposition of silicon dioxide react with groups such as CF3*, and the generated volatile gases such as CO, CO2, SiF4 are extracted from the reaction chamber by the vacuum system, completing the etching of silicon dioxide.

[0065] Then, if Figure 7 and Figure 8 As shown, an isolation layer 70 is formed, and the isolation layer 70 at least covers the side walls of the silicon through hole V1 and the dielectric through hole V2. Specifically, the isolation layer 70 covers the side walls, the bottom of the silicon through hole V1 and the dielectric through hole V2, and the side surface of the substrate 10 away from the dielectric stack layer 20. The isolation layer at the bottom of the dielectric through hole V2 is etched and removed to expose the conductive layer 41; the isolation layer located on the side surface of the substrate 10 away from the dielectric stack layer 20 can be etched and removed together, or can be retained as needed. The isolation layer 70 can be a single-layer film structure, a two-layer or multi-layer film structure. The material of the isolation layer 70 can be any one of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or a combination of two or more, and other suitable insulating materials. The isolation layer 70 prevents the subsequently formed interconnect layer 80 from diffusing into the substrate 10.

[0066] Next, an interconnection layer 80 is formed, the interconnection layer 80 covers the isolation layer 70 and fills the through silicon via V1 and the dielectric via V2, and the interconnection layer 80 is electrically connected to the conductive layer 41. The interconnection layer 80 can be made of any one of copper, tungsten or aluminum. When the interconnection layer 80 is made of copper, it can be formed by an electroplating process.

[0067] This embodiment also provides a semiconductor device, such as Figure 7 and Figure 8 As shown, including:

[0068] A substrate 10, on which a dielectric stack layer 20 including at least two dielectric layers of different materials is formed;

[0069] An opening K, wherein the opening K penetrates the dielectric stack layer 20;

[0070] A through silicon via V1, wherein the through silicon via V1 penetrates the substrate 10 at a position corresponding to the opening;

[0071] The dielectric through hole V2 is formed by etching the through silicon via V1 to expose the filling film layer filled in the opening K, and the filling film layer is made of the same material; when forming the dielectric through hole V2, the filling film layer remaining on the side wall of the opening K is etched as a protective layer 301;

[0072] An insulating layer 40 and a conductive layer 41 embedded in the insulating layer 40, wherein the insulating layer 40 covers the protective layer 301 and the dielectric stack layer 20, and the projection of the conductive layer 41 on the substrate 10 at least partially overlaps with the projection of the opening K on the substrate 10; the dielectric through hole V2 exposes the conductive layer 41.

[0073] The semiconductor device further comprises:

[0074] An isolation layer 70, wherein the isolation layer 70 covers the sidewalls of the through silicon via V1 and the dielectric via V2;

[0075] An interconnection layer 80 , wherein the interconnection layer 80 covers the isolation layer 70 and fills the through silicon via V1 and the dielectric via V2 and is electrically connected to the conductive layer 41 .

[0076] In the semiconductor device of the present embodiment, the filling film layer remaining on the side wall of the opening K after etching when forming the dielectric through hole V2 serves as a protective layer 301; that is, the side wall of the dielectric through hole V2 is composed of the protective layer 301 of the same material, and the dielectric stack layer 20 around the dielectric through hole V2 is covered or isolated by the protective layer 301, so as to avoid problems such as bubbles and rough side walls that are easily formed when etching the dielectric through hole V2 to expose the dielectric stack layer 20 of different materials.

[0077] In summary, the present invention provides a semiconductor device and a method for manufacturing the same, comprising: providing a substrate, on which a dielectric stack layer including at least two dielectric layers of different materials is formed; forming an opening penetrating the dielectric stack layer; forming a filling film layer, the filling film layer being formed of the same material and filling the opening; forming an insulating layer and a conductive layer embedded in the insulating layer, the insulating layer covering the filling film layer and the dielectric stack layer, the projection of the conductive layer on the substrate at least partially overlapping with the projection of the opening on the substrate; etching the substrate corresponding to the opening to form a through silicon via; and further etching the filling film layer exposed by the through silicon via and located in the opening to form a dielectric through hole, the dielectric through hole exposing the conductive layer.

[0078] The present invention removes the portion of the dielectric stack layer corresponding to the TSV position in advance to form an opening, and fills the opening with a single-layer filling film layer formed of the same material, that is, the portion of the dielectric stack layer corresponding to the TSV position is converted from a multi-layer film structure (a dielectric stack layer including at least two dielectric layers of different materials) into a single structure (a single-layer filling film layer) in advance, so that the film layer structure of the subsequent etching to form the dielectric through hole (TDV) is single, the etching quality of the dielectric through hole is improved, and process defects such as bottom side digging, difficulty in removing by-products (such as polymer residues), bottom failure to open, and arcing caused by machine sparking are reduced or even avoided.

[0079] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0080] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a dielectric stack layer including at least two dielectric layers of different materials is formed; forming an opening penetrating the dielectric stack; forming a filling film layer, wherein the filling film layer is formed of the same material and fills the opening; forming an insulating layer and a conductive layer embedded in the insulating layer, wherein the insulating layer covers the filling film layer and the dielectric stack layer, and a projection of the conductive layer on the substrate at least partially overlaps with a projection of the opening on the substrate; Etching the substrate at a position corresponding to the opening to form a through silicon via; as well as The filling film layer in the opening exposed by the silicon through hole is further etched to form a dielectric through hole, wherein the dielectric through hole exposes the conductive layer, and in a cross section perpendicular to the substrate, the cross-sectional width of the dielectric through hole is smaller than the cross-sectional width of the opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the filling film layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, borophosphosilicate glass, phosphosilicate glass and polymer materials.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The filling film layer is formed by any one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric stack layer includes any two or more different materials selected from silicon dioxide, silicon nitride, carbon-containing silicon nitride and low dielectric constant materials.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the insulating layer and the conductive layer and before forming the through silicon via, the method further includes: Bonding a side of the insulating layer away from the dielectric stack layer to a substrate; The side of the substrate away from the dielectric stack layer is thinned.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric through hole is formed by dry etching, and the etching gas includes fluorine-based gas.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric stack layer comprises a first dielectric layer, a second dielectric layer to an nth dielectric layer which sequentially cover the substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The material of the nth dielectric layer includes any one of SiNx, SiOx, Al2O3, AlN, HfO2, HfSiO, HfSiON and SiNO; the material of the second dielectric layer includes any one of SiNx, Al2O3, AlN, HfO2, SiOx, HfTiO, HfSiO, HfSiON, Sc2O3, Ga2O3, MgO and SiNO; the material of the first dielectric layer includes any one of SiOx, SiNx, Al2O3, HfO2 and SiNO.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that: The production method further comprises: forming an isolation layer, wherein the isolation layer covers the sidewalls of the through silicon via and the dielectric through hole; An interconnection layer is formed, wherein the interconnection layer covers the isolation layer, fills the through silicon via and the dielectric via, and is electrically connected to the conductive layer.

10. A semiconductor device, characterized in that: include: A substrate having a dielectric stack layer formed thereon, comprising at least two dielectric layers of different materials; An opening, wherein the opening penetrates the dielectric stack layer; A through silicon via, wherein the through silicon via penetrates the substrate corresponding to the opening; A dielectric through hole, wherein the dielectric through hole is formed by etching the through silicon via to expose a filling film layer filled in the opening, and the filling film layer is made of the same material; when forming the dielectric through hole, the filling film layer remaining on the side wall of the opening is etched as a protective layer; An insulating layer and a conductive layer embedded in the insulating layer, the insulating layer covers the protective layer and the dielectric stack layer, the projection of the conductive layer on the substrate at least partially overlaps with the projection of the opening on the substrate; the dielectric through hole exposes the conductive layer.

11. The semiconductor device according to claim 10, wherein: Also includes: an isolation layer, wherein the isolation layer covers the sidewalls of the through silicon via and the dielectric through hole; An interconnection layer covers the isolation layer and fills the through silicon via and the dielectric via and is electrically connected to the conductive layer.

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