A method for manufacturing a non-shading passivated contact MWT cell

Abstract

The application provides a preparation method of a non-shading passivation contact MWT battery, and belongs to the technical field of solar cells, and comprises the following steps: double-side texturing of an N-type silicon wafer, and polishing of a back light surface; preparation of a first tunneling oxide layer and a phosphorus-doped polysilicon layer on the back light surface, preparation of a phosphorus-silicon layer on the outer surface of the phosphorus-doped polysilicon layer; setting a plurality of preset areas on the back light surface, and removing the phosphorus-silicon glass layer, the phosphorus-doped polysilicon layer and the first tunneling oxide layer on the preset areas, and preparing through holes penetrating through the silicon wafer on the preset areas; preparing a second tunneling oxide layer and an intrinsic polysilicon layer on the back light surface and the inner wall of the through holes; performing boron diffusion process treatment on the silicon wafer; performing chemical cleaning on the silicon wafer; depositing a passivation anti-reflection layer on the double sides of the silicon wafer; screen printing metal grid lines on the back light surface and the through holes; and drying and sintering. The preparation method of the non-shading passivation contact MWT battery simplifies the production process steps and reduces the production cost.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, and more specifically, relates to a method for preparing a light-shielding passivated contact MWT cell. Background Technology

[0002] Solar power generation technology is an important area of ​​new energy development. Improving the conversion efficiency of solar panels, increasing output power per unit area, simplifying the solar cell manufacturing process, and reducing manufacturing costs are the ultimate goals of solar cell technology advancement. MWT cells introduce front-side current into the back surface of the cell through through-holes penetrating the silicon wafer, which can eliminate some of the shading from the grid lines on the light-receiving side. However, current MWT cells cannot completely eliminate front-side grid line shading. Furthermore, N-type MWT cells require additional insulation and cleaning processes for the back surface and the emitter area introduced to the back surface, increasing the cell manufacturing process. At the same time, the recombination between the inner wall of the through-holes and the metal paste is significant; increasing the number of through-holes greatly increases recombination at the metallized contacts, leading to a decrease in cell conversion efficiency. Therefore, the development of MWT cell conversion efficiency, especially for N-type MWT cells, has been relatively slow, hindering large-scale industrial production and slowing down the rate of cost reduction and efficiency improvement. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a non-shielded passivated contact MWT battery. This method solves the problem of shading by the metal grid lines on the front of the battery, and also eliminates a series of steps such as laser etching required in the traditional N-type MWT battery fabrication process to achieve back field and insulation between the back emitter. This greatly simplifies the fabrication process of the back field and through-hole guided back emitter of the N-type MWT battery, and reduces the battery cost.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is: to provide a method for preparing a light-shielding passivated contact MWT cell, comprising the following steps:

[0005] Step 1: Double-sided texturing of N-type silicon wafers and polishing of the backlight side;

[0006] Step 2: Prepare a first tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the backlight surface, and prepare a phosphorus-silicon glass layer on the outer surface of the phosphorus-doped polycrystalline silicon layer;

[0007] Step 3: Set multiple preset areas on the backlight surface, remove the phosphorus silicate glass layer, the phosphorus-doped polycrystalline silicon layer and the first tunneling oxide layer on the preset areas, and prepare through holes penetrating the silicon wafer in the specific areas;

[0008] Step 4: Prepare a second tunneling oxide layer and an intrinsic polycrystalline silicon layer on the backlight surface and the inner wall of the through hole;

[0009] Step 5: Perform a boron diffusion process on the silicon wafer;

[0010] Step Six: Chemically clean the silicon wafer;

[0011] Step 7: Deposit passivation and antireflection layers on both sides of the silicon wafer;

[0012] Step 8: Screen print metal grid lines on the backlight surface and inside the through holes;

[0013] Step 9: Drying and sintering.

[0014] In one possible implementation, the predetermined area in step three is a circular area with a diameter between 0.05 mm and 5 mm.

[0015] In one possible implementation, the through hole is a circular hole with a cross-sectional diameter between 0.01 mm and 0.2 mm.

[0016] In one possible implementation, the circular region is concentric with the circular hole.

[0017] In one possible implementation, the lines connecting three adjacent through holes form an equilateral triangle.

[0018] In one possible implementation, the thickness of the second tunneling oxide layer in step four is between 1 nm and 2 nm, and the thickness of the intrinsic polycrystalline silicon layer is between 10 nm and 200 nm.

[0019] In one possible implementation, the boron diffusion process in step five is carried out at a temperature of 950°C, a diffusion time of 20 minutes, and a doping concentration of 2E19 atm / cm3, thereby forming a boron-phosphorus co-doped polycrystalline silicon layer on the backlight surface.

[0020] In one possible implementation, in step six, chemical etching is performed simultaneously with chemical cleaning. Specifically, an alkaline solution is used to etch the backlight surface to remove the boron-phosphorus co-doped polycrystalline silicon layer and form an insulating region on the backlight surface.

[0021] In one possible implementation, the width of the insulating region is between 100 nm and 100 μm.

[0022] In one possible implementation, the diameter of the area of ​​the printed metal grid lines on the backlight surface in step eight is between 0.04 mm and 0.5 mm.

[0023] The beneficial effects of the method for fabricating a non-shielded passivated contact MWT cell provided by this invention are as follows: Compared with the prior art, a first tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, and a phosphorosilicate glass layer are prepared on the back surface of an N-type silicon wafer. The first tunneling oxide layer, phosphorus-doped polycrystalline silicon layer, and phosphorosilicate glass layer in a predetermined region are removed, and a circular through-hole penetrating the silicon wafer is prepared at the center of this predetermined region. Subsequently, a second tunneling oxide layer and an intrinsic polycrystalline silicon layer are prepared on the back surface of the silicon wafer and the inner wall of the through-hole. Boron doping is then performed on both sides of the silicon wafer through boron diffusion to form a boron-doped polycrystalline silicon layer. Simultaneously, a boron-diffused emitter is formed on the light-receiving surface of the silicon wafer. A boron-phosphorus co-doped polycrystalline silicon layer is formed in the overlapping region of the phosphorus and boron doping. During the subsequent chemical cleaning process, the corrosion rate of the phosphorus-boron co-doped polycrystalline silicon layer is significantly higher. By using a single phosphorus-doped or boron-doped layer, excess boron-phosphorus co-doped polycrystalline silicon layers are removed, forming an insulating region. This achieves self-aligned etching insulation between the back field of the N-type MWT cell and the emitter introduced to the back of the silicon wafer. This eliminates the need for additional laser etching and chemical cleaning processes required in traditional N-type back contact cell fabrication to achieve insulation between the back field and the back emitter, greatly simplifying the back field and back emitter fabrication process and reducing cell costs. At the same time, all metal grid lines achieve passivation contact between the metal and the silicon wafer through contact with the silicon wafer. Based on this effect, by optimizing the design of the distance and shape distribution between vias, traditional grid lines can be eliminated on the front of the cell, thereby increasing the cell current and reducing cell costs. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a method for preparing a light-shielding passivated contact MWT cell according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the silicon wafer structure after step two is completed;

[0027] Figure 3 This is a schematic diagram of the silicon wafer structure after step three is completed;

[0028] Figure 4 This is a schematic diagram of the silicon wafer structure after step four is completed;

[0029] Figure 5 This is a schematic diagram of the silicon wafer structure after step five is completed;

[0030] Figure 6This is a schematic diagram of the silicon wafer structure after step six is ​​completed;

[0031] Figure 7 This is a schematic diagram of the silicon wafer structure after step seven is completed;

[0032] Figure 8 This is a schematic diagram of the silicon wafer structure after step eight is completed;

[0033] Figure 9 This is a schematic diagram of the layout structure of vias on a silicon wafer.

[0034] The following are the labeling elements in the figure:

[0035] 1. Silicon wafer; 2. First tunneling oxide layer; 3. Phosphorus-doped polysilicon layer; 4. Phosphosilicate glass layer; 5. Preset area; 6. Through-hole; 7. Second tunneling oxide layer; 8. Intrinsic polysilicon layer; 9. Boron-doped polysilicon layer; 10. Boron-phosphorus co-doped polysilicon layer; 11. Insulating area; 12. Passivation antireflection layer; 13. Metal gate line. Detailed Implementation

[0036] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0037] Please see Figures 1 to 9 The present invention will now describe a method for preparing a light-shielding passivated contact MWT cell. The method for preparing the light-shielding passivated contact MWT cell includes the following steps:

[0038] Step 1: Double-sided texturing and backlight polishing of N-type silicon wafer 1;

[0039] Step 2: Prepare a first tunneling oxide layer 2 and a phosphorus-doped polycrystalline silicon layer 3 on the back surface of the N-type silicon wafer 1, and prepare a phosphorus-silicon glass layer 4 on the outer surface of the phosphorus-doped polycrystalline silicon layer 3. The thickness of the first tunneling oxide layer 2 is 5 nm, the thickness of the phosphorus-doped polycrystalline silicon layer 3 is 120 nm, and the doping concentration is 5E20atm / cm3.

[0040] Step 3: In a predetermined area 5 on the back surface of silicon wafer 1, a laser with a wavelength of 355nm, a pulse width of 100ps, a spot diameter of 50µm, and a mesa power of 30W is used to remove the phosphorosilicate glass layer 4, the phosphorus-doped polycrystalline silicon layer 3, and the first tunneling oxide layer 2. The predetermined area 5 has a width and diameter of 0.8mm. Simultaneously, a through-hole 6 penetrating the silicon wafer 1 is fabricated at the center of the predetermined area 5. The center of the through-hole 6 coincides with the center of the predetermined area 5. The diameter of the through-hole 6 is 0.03mm. The lines connecting three adjacent through-holes 6 form an equilateral triangle with a side length of 2mm. Please refer to [link to relevant documentation]. Figure 9As shown. It then undergoes a chemical cleaning process to remove the damaged layer from the laser ablation area and the walls around the via 6, keeping the silicon wafer 1 and the surface of the via 6 clean.

[0041] Step 4: Prepare a second tunneling oxide layer 7 and an intrinsic polycrystalline silicon layer 8 on the back surface of the N-type silicon wafer 1 and the inner wall of the via 6. The thickness of the second tunneling oxide layer 7 is 1.5 nm and the thickness of the intrinsic polycrystalline silicon layer 8 is 120 nm.

[0042] Step 5: Perform boron diffusion process on silicon wafer 1, with diffusion temperature of 950℃, diffusion time of 20 minutes, and doping concentration of 2E19atm / cm3. At the same time, the overlapping area of ​​phosphorus doping and boron doping forms a boron-phosphorus co-doped polycrystalline silicon layer 9.

[0043] Step 6: Chemical cleaning. Alkaline solution is used for cleaning. Since the corrosion rate of the phosphorus-boron co-doped polycrystalline silicon layer is significantly higher than that of the phosphorus-doped or boron-doped regions alone, selective removal of the boron-phosphorus co-doped polycrystalline silicon layer 10 is achieved. At the same time, self-aligned etching insulation between the battery back field and the emitter introduced on the back side is achieved.

[0044] Step 7: Deposit a passivation antireflection layer 12 on the surface of silicon wafer 1; the passivation antireflection layer 12 includes an aluminum oxide layer and a silicon nitride thin film on the aluminum oxide layer, wherein an aluminum oxide layer is prepared by ALD process with a thickness of 4nm; the silicon nitride thin film is prepared by PECVD (plasma-enhanced chemical deposition) with a thickness of 75nm, which can also play a protective and antireflective role.

[0045] Step 8: Screen print metal grid lines 13 on the back surface of silicon wafer 1 and inside the via 6. The diameter of the area where the metal grid lines 13 are printed on the back surface of silicon wafer 1 is 0.3 mm.

[0046] Step 9: After drying and sintering, a passivated contact MWT battery product with an unshaded front side is formed.

[0047] Furthermore, in step six, the width of the insulating region 11 is between 100 nm and 100 μm.

[0048] This invention provides a method for fabricating a non-shielded passivated contact MWT cell. Compared with existing technologies, this method involves fabricating a first tunneling oxide layer 2, a phosphorus-doped polycrystalline silicon layer 3, and a phosphorosilicate glass layer 4 on the back surface of an N-type silicon wafer 1. The first tunneling oxide layer 2, phosphorus-doped polycrystalline silicon layer 3, and phosphorosilicate glass layer 4 are removed from a predetermined region 5. A circular through-hole 6 penetrating the silicon wafer 1 is then fabricated at the center of this predetermined region 5. Subsequently, a second tunneling oxide layer 7 and an intrinsic polycrystalline silicon layer 8 are fabricated on the back surface of the silicon wafer 1 and the inner wall of the through-hole 6. Boron diffusion is then used to dope the intrinsic polycrystalline silicon layer 8 on the back surface of the silicon wafer 1 and the light-receiving surface of the silicon wafer 1, forming a boron-doped polycrystalline silicon layer 9. Simultaneously, a boron-diffused emitter is formed on the light-receiving surface of the silicon wafer 1. A boron-phosphorus co-doped polycrystalline silicon layer 10 is formed in the overlapping region of the phosphorus-doped and boron-doped layers. During the subsequent chemical cleaning process, due to the phosphorus-boron co-doped polycrystalline silicon… The etching rate of layer 10 is significantly higher than that of a single phosphorus-doped layer or boron-doped layer, thereby removing excess boron-phosphorus co-doped polycrystalline silicon layer 10 and forming an insulating region 11. This achieves self-aligned etching insulation between the back field of the N-type MWT cell and the emitter introduced to the back of the silicon wafer 1, eliminating the need for additional laser etching and chemical cleaning processes required in the traditional N-type back contact cell fabrication process to achieve insulation between the back field and the back emitter. This greatly simplifies the back field and back emitter fabrication process steps of the back contact cell, reducing cell costs. At the same time, all metal grid lines 13 achieve passivation contact between the metal and the silicon wafer 1 through contact with the silicon wafer 1. Based on this effect, by optimizing the design of the distance and shape distribution between the vias 6, it is possible to achieve no traditional grid lines on the front of the cell, thereby increasing the cell current and reducing cell costs.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preparing a light-shielding passivated contact MWT cell, characterized in that, Includes the following steps: Step 1: Double-sided texturing of N-type silicon wafers and polishing of the backlight side; Step 2: Prepare a first tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the backlight surface, and prepare a phosphorus-silicon glass layer on the outer surface of the phosphorus-doped polycrystalline silicon layer; Step 3: Set multiple preset areas on the backlight surface, remove the phosphorus silicate glass layer, the phosphorus-doped polycrystalline silicon layer and the first tunneling oxide layer on the preset areas, and prepare through holes penetrating the silicon wafer in the preset areas; Step 4: Prepare a second tunneling oxide layer and an intrinsic polycrystalline silicon layer on the backlight surface and the inner wall of the through hole; Step 5: Perform a boron diffusion process on the silicon wafer to form a boron-phosphorus co-doped polycrystalline silicon layer on the backlight surface; Step Six: Use an alkaline solution to chemically clean and etch the silicon wafer to remove the boron-phosphorus co-doped polycrystalline silicon layer and form an insulating region on the backlight surface; Step 7: Deposit passivation and antireflection layers on both sides of the silicon wafer; Step 8: Screen print metal grid lines on the backlight surface and inside the through holes; Step 9: Drying and sintering.

2. The method for preparing a light-shielding passivated contact MWT cell as described in claim 1, characterized in that, The preset area in step three is a circular area with a diameter between 0.05mm and 5mm.

3. The method for preparing a light-shielding passivated contact MWT cell as described in claim 2, characterized in that, The through hole is a circular hole, and the diameter of the cross-section of the circular hole is between 0.01mm and 0.2mm.

4. The method for preparing a light-shielding passivated contact MWT cell as described in claim 3, characterized in that, The circular region is concentric with the circular hole.

5. The method for preparing a light-shielding passivated contact MWT battery as described in claim 4, characterized in that, The lines connecting three adjacent through holes form an equilateral triangle.

6. The method for preparing a light-shielding passivated contact MWT cell as described in claim 1, characterized in that, In step four, the thickness of the second tunneling oxide layer is between 1 nm and 2 nm, and the thickness of the intrinsic polycrystalline silicon layer is between 10 nm and 200 nm.

7. The method for preparing a light-shielding passivated contact MWT cell as described in claim 1, characterized in that, In step five, the boron diffusion process is carried out at a temperature of 950°C, a diffusion time of 20 minutes, and a doping concentration of 2E19 atm / cm3.

8. The method for preparing a light-shielding passivated contact MWT battery as described in claim 1, characterized in that, The width of the insulating region is between 100 nm and 100 μm.

9. The method for preparing a light-shielding passivated contact MWT cell as described in claim 1, characterized in that, In step eight, the diameter of the area of ​​the printed metal grid lines on the backlight surface is between 0.04mm and 0.5mm.

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