A hybrid multilevel inverter predictive control method

Abstract

The application provides a hybrid multi-level inverter predictive control method, a discrete model predicted by a single vector model is used to establish a value function without a weight factor, and a voltage predicted when the value function minimum is used to replace a reference voltage to perform space vector modulation. A fault-tolerant control method is to establish a seven-level voltage space vector diagram, remove the coordinates lost in the space vector diagram due to bypassing the H-bridge unit due to failure, and continue to perform space vector modulation by using the remaining coordinates. The application uses single vector model prediction to reduce the calculation amount of the value function while ensuring accuracy, uses a common-mode reduction method to reduce the system common-mode voltage, so that the method can be applied in the photovoltaic industry to prevent damage to other devices caused by large common-mode voltage.

Description

Technical Field

[0001] This invention belongs to the field of inverter control technology and relates to a predictive control method for hybrid multilevel inverters. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In photovoltaic power generation, with the gradual adoption of multilevel inverters, the number of switching devices increases, making the system more complex and significantly increasing the difficulty of control technology. Furthermore, when switching devices fail, the consequences can range from minor issues affecting the output waveform and voltage quality to severe power supply system failures, causing irreversible damage to life and property. Therefore, research on fault-tolerant control of multilevel inverters is extremely important.

[0004] The hybrid topology seven-level inverter consists of a T-type three-level inverter and three H-bridge units connected in series. Therefore, this topology combines the advantages of both topologies: the T-type inverter, as the main topology, transmits active power at only three output voltage levels, while the H-bridge units transmit reactive power only. Furthermore, this topology has a peak-to-peak value of 6E, which is 1.5 times that of the T-type three-level inverter. This is equivalent to increasing the DC input voltage, thereby improving DC voltage utilization. Moreover, compared to cascaded H-bridge seven-level inverters, this topology uses fewer switching devices, employs a simpler modulation method, and has a lower probability of switching device failure.

[0005] However, this hybrid topology seven-level inverter has a large number of switching devices, which makes it more prone to failure when modulating the output voltage. Furthermore, since the switching devices in the H-bridge unit are used more frequently, the failure probability of these switching devices is also higher.

[0006] This topology has seven output voltage levels, corresponding to twelve switching modes. Only the output voltage of ±3E corresponds to one switching mode, while the other output voltage states correspond to two switching modes. Therefore, by utilizing the redundancy of the output voltage switching modes in this topology, fault-tolerant control for minor faults can be achieved. However, when there are many faults in the switching devices and the output voltage waveform is severely distorted, other fault-tolerant control methods are required. Summary of the Invention

[0007] To address the aforementioned problems, this invention proposes a predictive control method for hybrid multilevel inverters. This invention utilizes a single-vector model for prediction, which reduces the computational load of the value function while ensuring accuracy. It also employs a common-mode reduction method to decrease the system's common-mode voltage, enabling the method to be applied in the photovoltaic industry and preventing damage to other devices from excessive common-mode voltage.

[0008] According to some embodiments, the present invention adopts the following technical solution:

[0009] A predictive control method for a hybrid multilevel inverter includes the following steps:

[0010] Using the discrete model predicted by the single vector model, a value function without weighting factors is established, and the voltage vector selected when the value function reaches its minimum value is used to replace the reference voltage vector for space vector modulation.

[0011] When a fault occurs in a phase H-bridge unit, fault-tolerant control is implemented to bypass the entire H-bridge unit, so that the hybrid topology seven-level inverter that is working normally is converted into a T-type three-level inverter that is working in faulty condition to maintain the normal operation of the system.

[0012] As an alternative implementation method, the construction process of the discrete model for single-vector model prediction includes: obtaining the output voltage of the hybrid topology inverter according to Kirchhoff's voltage law, converting the voltage into the form of current, and then using Clarke transform to derive the mathematical model of the output voltage in the αβ orthogonal coordinate system. According to the sampling period, the continuous model is represented as a discrete model to predict the reference voltage vector of the control target at the next moment.

[0013] As an alternative implementation, a value function without weighting factors is constructed. By calculating the value function, the basic voltage vector closest to the voltage predicted by the model is selected to replace the reference voltage vector for space vector modulation, thereby controlling the switching state of the switching device to output the voltage.

[0014] As a further step, the fault-tolerant control method involves establishing a seven-level voltage space vector diagram, removing the coordinates lost in the space vector diagram due to the H-bridge unit being bypassed by a fault, and using the remaining coordinates to continue space vector modulation.

[0015] As a further step, when the H-bridge unit is bypassed, the coordinates corresponding to the fault phase in the spatial vector diagram are filtered to remove coordinates that do not meet the fault-tolerant control method, and the remaining coordinates are used for spatial vector modulation.

[0016] As a further step, the coordinates of the minimum common-mode voltage corresponding to each point in the space vector diagram are calculated by using the definition of common-mode voltage, and space vector modulation is performed using the voltage vector corresponding to this coordinate.

[0017] A hybrid topology seven-level inverter includes three-phase bridge arms connected in parallel. Each bridge arm includes one bridge arm of a T-type three-level inverter and an H-bridge unit. One bridge arm of the T-type three-level inverter consists of two reverse-connected series switches connected to a half-bridge unit, and the two ends of the half-bridge unit are connected to the two ends of two series capacitors of the DC link.

[0018] The H-bridge unit consists of two two-level half-bridge units formed by four switching transistors connected in series end to end, and the upper and lower midpoints of the H-bridge unit circuit are connected to the two ends of the flying capacitor; the midpoints of the two half-bridge units are respectively connected to the T-type three-level inverter in the front stage and the power grid in the back stage.

[0019] The above predictive control method is used for control.

[0020] A computer-readable storage medium storing a plurality of instructions adapted for loading by a processor of a terminal device and executing steps in the method.

[0021] A control device includes a processor and a computer-readable storage medium, the processor being configured to implement instructions; the computer-readable storage medium being configured to store a plurality of instructions adapted to be loaded by the processor and executed in accordance with the steps of the method.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] (1) Before the fault, the output voltage of this method is seven levels. Compared with the three-level inverter with only T type, it is equivalent to increasing the DC input voltage, thereby increasing the utilization rate of DC voltage, and the waveform of the output voltage is a more accurate sine wave.

[0024] (2) This method uses a single vector model for prediction, which reduces the computational cost of the value function while ensuring accuracy.

[0025] (3) This method reduces the output voltage of the faulty phase from seven levels to three levels after a faulty switch in the H-bridge unit without voltage distortion, and can still maintain the normal operation of the inverter.

[0026] (4) This method uses the common-mode reduction method to reduce the common-mode voltage of the system, so that the method can be applied in the photovoltaic industry to prevent the generation of large common-mode voltage from damaging other devices.

[0027] (5) This invention is applied to the photovoltaic industry. By calculating the common mode voltage, the coordinates of each point in the spatial vector diagram with the smallest absolute value of the common mode voltage are selected for spatial vector modulation. This invention uses this common mode reduction method to reduce the common mode voltage of the system. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0029] Figure 1 This is a schematic diagram of a hybrid topology seven-level inverter according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of a model prediction using voltage vectors according to an embodiment of the present invention.

[0031] Figure 3 This is a spatial vector diagram of the A-phase subtraction common mode during normal operation according to an embodiment of the present invention.

[0032] Figure 4 This is a spatial vector diagram of a common-mode H-bridge unit in phase A subtraction according to an embodiment of the present invention.

[0033] Figure 5(a) is a simulation diagram of the output voltage of phase A when it is working normally after common mode reduction treatment according to an embodiment of the present invention.

[0034] Figure 5(b) is a simulation diagram of the output voltage after fault-tolerant control when the A-phase H-bridge unit fails after common-mode reduction processing according to an embodiment of the present invention.

[0035] Figure 5(c) is a simulation diagram of the output line voltage when the two phases AB are operating normally after common-mode reduction treatment according to an embodiment of the present invention.

[0036] Figure 5(d) is a simulation diagram of the output line voltage after fault-tolerant control when phase B is working normally after a fault in phase A H-bridge unit following common-mode reduction treatment according to an embodiment of the present invention.

[0037] Figure 5(e) is a simulation diagram of the three-phase output current during normal operation after common-mode reduction treatment according to an embodiment of the present invention.

[0038] Figure 5(f) is a simulation diagram of the three-phase output current after fault-tolerant control when the A-phase H-bridge unit fails after common-mode reduction treatment according to an embodiment of the present invention.

[0039] Figure 5(g) is a simulation diagram of the common-mode voltage during normal operation after common-mode reduction treatment according to an embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0042] This invention provides a hybrid topology, including parallel three-phase bridge arms. Each bridge arm includes an H-bridge unit and a bridge arm of a T-type inverter. The T-type inverter's bridge arm consists of two units: the first unit comprises two IGBT switches connected in reverse series, and the second unit comprises two IGBT switches connected in forward series, forming a two-level half-bridge unit. A 2E capacitor is connected to each end of the second unit, and these two capacitors are connected in series. One end of the first unit is then connected to the connection point of the two capacitors, and the other end is connected to the midpoint of the second unit, thus forming one bridge arm of the T-type three-level inverter. The H-bridge unit comprises two parallel two-level half-bridge units formed by four IGBT switches connected in series, and a capacitor with a capacitance of E is connected in parallel with the two half-bridge units to form the H-bridge unit. This topology is formed by connecting the connection point of the first and second units in one bridge arm of the T-type three-level inverter to the midpoint of one of the two half-bridge units in the H-bridge unit. Each unit is grounded via a star connection through capacitors.

[0043] In some embodiments, different switching transistors can withstand different maximum voltages, so different voltage levels or types of power devices can be used for switching transistors in different locations to save hardware costs.

[0044] The control method for the hybrid topology seven-level inverter described above uses a discrete model predicted by a single vector model to establish a value function without weighting factors, and uses the voltage predicted when the value function reaches its minimum value to perform space vector modulation.

[0045] In some embodiments, fault-tolerant control is implemented after a failure of a certain IGBT switch in the H-bridge unit by bypassing the H-bridge unit. The original hybrid topology seven-level inverter is converted into a T-type three-level inverter, and the output voltage of the faulty phase is reduced from seven-level to three-level to maintain the normal operation of the inverter.

[0046] In some embodiments, the fault-tolerant method is to establish a seven-level voltage space vector diagram, remove the coordinates lost in the space vector diagram due to the H-bridge unit being bypassed by a fault, and continue to perform space vector modulation using the remaining coordinates.

[0047] Since this topology is applied in the photovoltaic industry, the coordinates of the point with the smallest absolute value of common-mode voltage in the space vector diagram are selected by calculating the common-mode voltage to perform space vector modulation. This invention uses this common-mode reduction method to reduce the common-mode voltage of the system.

[0048] In some embodiments, after removing the coordinates lost in the spatial vector diagram due to the fault bypassing of the H-bridge unit, the coordinates lost in the spatial vector diagram to reduce the common-mode voltage are further removed, and the remaining coordinates are used to continue spatial vector modulation.

[0049] As a typical embodiment of the present invention, a hybrid seven-level inverter topology is provided. For example... Figure 1 As shown, this hybrid topology consists of one arm of a T-type three-level inverter and an H-bridge unit connected in series. x1 -S x8 For 8 fully controlled switching devices, V cd1 and V cd2 These are the upper and lower capacitor voltages of the DC link, U fx Let x be the voltage across the flying capacitor (x = a, b, c). The voltage across Cd1 and Cd2 is 2E, the DC link voltage is constant at 4E, and the voltage across the flying capacitor is E. x1 and S x2 Withstands the voltage of the entire DC power supply (4E), S x3 and S x4 The voltage it withstands is half of the DC power supply (2E), S x5 -S x8 It withstands the voltage (E) across the flying capacitor. Cx It is the current flowing into the leap capacitor Cx, i mx This is the current flowing out from the midpoint of the DC link. For a T-type three-level inverter, S x1 With S x2 S x3 With S x4 The drive signals are complementary. By controlling the on / off state of the four switching devices, the T-type topology can generate three voltage levels: -2E, 0, and 2E. Therefore, the T-type inverter is a three-level topology. For the H-bridge unit, the upper and lower switching devices on each side of the bridge arm are complementary in conduction, i.e., S... x5 With S x6 S x7 With S x8 The drive signals are complementary. By controlling the on / off state of the four switching devices, the H-bridge unit can generate three voltage levels: -E, 0, and E. Therefore, the H-bridge unit is also a three-level topology. (The last sentence appears to be incomplete and possibly refers to a different topic.) x1 and S x2 The midpoint of S x5 and S x6 By connecting the midpoints, the resulting hybrid topology can output seven levels from -3E to +3E, thus constituting a seven-level inverter. The seven levels from -3E to 3E correspond to 12 different conduction paths. When the output voltage is ±3E, there is only one conduction path; when the output voltage is -2E to +2E, each output voltage corresponds to two conduction paths. Table I shows the switching states and output voltage states corresponding to different conduction paths.

[0050] Table I Output Voltage Status and Switching Status

[0051]

[0052] According to the present invention, a control method using the above-described topology is also provided.

[0053] According to a specific embodiment of the present invention, in Figure 2 The reference voltage V for space vector modulation is obtained by predicting MPC through a model. ab This voltage is then used to control the switching state of the switching devices using PWM modulation.

[0054] The specific method for model prediction is as follows: Based on Kirchhoff's voltage law, the output voltage of the hybrid topology inverter is obtained, converted into current form, and then the Clarke transform is used to derive the mathematical model of the output voltage in the αβ orthogonal coordinate system. Let the sampling period be Ts, the resistance be R, the inductance to ground be L, and the voltage be V. α (k)V β (k) represents the voltage of the discrete model transformed into the αβ two-phase voltage at time k, i α (k)i β (k) represents the current in the discrete model at time k transformed into the αβ two-phase current, i α (k-1)i β (k-1) represents the current in the discrete model transformed into the αβ two-phase current at time k-1, e α (k)e β (k) represents the grid voltage of the two phases α and β transformed from the discrete model at time k. The continuous model is expressed as a discrete model, which is:

[0055]

[0056] After the three phases ABC are transformed into two phases α and β by Clarke transformation, the current i(k) at time k and the rate of change of i(k) at this time are used to predict the current i(k+1) at the next time. Then the current is converted into voltage to obtain the predicted reference voltage.

[0057] To achieve optimal current tracking performance, a current tracking value function g based on the voltage model of MPC is proposed as follows:

[0058]

[0059] in, V is the voltage obtained by transforming the discrete model at time k+1 into the two-phase αβ voltage predicted by the model. α V β The voltage vectors after the discrete model is transformed into two phases α and β.

[0060] The coordinates of the voltage vector in the spatial vector diagram and the voltage obtained from the discrete mathematical model are substituted into the calculation of the value function. The voltage vector corresponding to the minimum value of the obtained value function is used to replace the reference voltage for spatial vector modulation.

[0061] According to a specific embodiment of the present invention, when phase A is operating normally, since it is a seven-level inverter, there are a total of 7x7x7 = 343 vectors. Each voltage vector can be represented by (x, y, z), where x, y, and z represent the numerical values ​​corresponding to the output voltage values ​​of phases A, B, and C, respectively. For example, the voltage vector corresponding to the origin coordinates (3, 3, 3) is the voltage vector where the output voltages of phases A, B, and C are all 0. Considering only the case of H-bridge unit failure, when a switch in the H-bridge unit fails, the entire H-bridge unit is bypassed. That is, the original T-type cascaded H-bridge hybrid topology inverter is converted into a single T-type three-level inverter for output. Since the DC link voltage V cd1 and V cd2 Since the common-mode voltage is 2E, the output voltage after bypassing the H-bridge unit only has three levels: -2E, 0, and 2E, corresponding to coordinates 1, 3, and 5. Other voltage levels cannot be output, and the inverter is reduced from seven levels to three levels to maintain normal operation. If a switch in the A-phase H-bridge unit fails, after fault tolerance processing, only the vector coordinates (x, y, z) (x = 1, 3, 5) are retained. At this point, there are 147 remaining space vectors and 97 remaining coordinates. Because this equipment is used in photovoltaic grid connection, reducing its common-mode voltage reduces common-mode leakage current to ensure equipment safety. The common-mode voltage of each of the 343 vectors is calculated, and the coordinate with the smallest absolute value of the common-mode voltage for each calculated vector is marked on the space vector diagram.

[0062] The common-mode voltage of the inverter can be expressed as

[0063] V CMV =(V an +V bn +V cn ) / 3

[0064] V an V bn V cn The voltages of phases A, B, and C are respectively, V CMV This is the common-mode voltage.

[0065] Based on the above description, this topology has seven output levels, namely "-3V". dc / 4”, -V dc / 2”, -V dc / 4”, 0”, V dc / 4”V dc / 2”, 3Vdc / 4". Substituting the seven output voltage levels of the three-phase output into the above formula, we obtain 19 possible values ​​for the common-mode voltage, namely: "-3V". dc / 4”, -2V dc / 3”, -7V dc / 12”, -V dc / 2"-5V dc / 12”, -V dc / 3”, -V dc / 4”, -V dc / 6”, -V dc / 12”, “0”, “V” dc / 12”, V dc / 6”V dc / 4”V dc / 3"5V" dc / 12”, V dc / 2”, 7V dc / 12”, “2V” dc / 3”, “3V” dc / 4”, where V dc The voltage of the entire DC power supply is 4E. The common-mode reduction method used in this invention is to perform space vector modulation only using the coordinate with the minimum common-mode voltage. The minimum common-mode voltage is 0 or ±1 / 12V. dc This method can reduce the common-mode voltage of the system, thereby reducing the common-mode leakage current caused by the common-mode voltage and reducing unnecessary losses.

[0066] According to a specific embodiment of the present invention, when the H-bridge unit is bypassed due to a fault, the coordinates of the remaining voltage vector are (x, y, z) (x = 1, 3, 5). The vector and coordinates after common-mode reduction screening are as follows: Figure 4 As shown, at this point, the number of remaining vectors and coordinates is 53, the number of output voltage levels decreases from seven levels to three levels, and the common-mode voltage is also reduced to ±1 / 12V. dc between.

[0067] According to a specific embodiment of the present invention, a fault-tolerant method for a hybrid topology seven-level inverter was simulated. Figure 5(a) shows the method when the DC bus voltage is 580V, i.e., V dc =580V, the output voltage of phase A during normal operation after common-mode reduction. There are seven output voltage levels, with amplitudes ranging from ±3 / 4V. dc Within the range. Figure 5(b) shows the output voltage of the A-phase H-bridge unit after fault tolerance control following common-mode reduction processing. The output voltage is reduced from seven levels to three levels, and the amplitude of the output voltage is reduced to ±1 / 2V. dcFigure 5(c) shows the output line voltage of phases A and B under normal operation after common-mode reduction treatment. Compared with the output line voltage of phase B under fault-tolerant control after common-mode reduction treatment (Figure 5(d) when phase A H-bridge unit fails), the output line voltage of this figure changes from a significant nine-level to slightly distorted. Figures 5(e) and 5(f) show the three-phase output current under normal operation after common-mode reduction treatment and the three-phase output current under fault-tolerant control after phase A H-bridge unit fails, respectively. The former shows a relatively stable current with a good waveform, while the latter shows fluctuations in output current due to phase A H-bridge unit failure, with the fluctuations being most pronounced when reaching the peak value. Figure 5(g) shows the common-mode voltage under normal operation after common-mode reduction treatment. The common-mode voltage is suppressed to ±1 / 12V by applying the common-mode reduction method. dc Within the range. Therefore, it can be concluded that this common-mode reduction fault-tolerant control method has a suppressive effect on common-mode voltage, reducing it from the original maximum common-mode voltage absolute value of 3 / 4V. dc Reduce to 1 / 12V dc This significantly reduces the common-mode voltage within the system.

[0068] The present invention also provides the following product examples:

[0069] A control device is characterized by including a processor and a computer-readable storage medium, the processor for implementing instructions; the computer-readable storage medium for storing a plurality of instructions adapted to be loaded by the processor and executed in accordance with the steps of the method.

[0070] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A predictive control method for a hybrid topology seven-level inverter, characterized in that, Includes the following steps: A discrete model predicted by a single vector model is used to establish a value function without weighting factors. The voltage predicted when the value function is at its minimum value is used to replace the reference voltage for space vector modulation. When a certain phase H When a bridge unit fails, fault-tolerant control is implemented to... H The entire bridge unit is bypassed, transforming the hybrid topology seven-level inverter from normal operation to fault operation. T A three-level inverter is used to maintain the normal operation of the system; when H When the bridge unit is bypassed, the coordinates corresponding to the fault phase in the spatial vector diagram are filtered out, and the coordinates that do not meet the fault-tolerant control method are removed. The remaining coordinates are then used for spatial vector modulation. The coordinates of the minimum common-mode voltage corresponding to each point in the space vector diagram are calculated by defining common-mode voltage, and space vector modulation is performed using the voltage vector corresponding to this coordinate.

2. The predictive control method for a hybrid topology seven-level inverter as described in claim 1, characterized in that, The fault-tolerant control method involves establishing a seven-level voltage space vector diagram and removing fault-bypassed values ​​from the space vector diagram. H The coordinates lost by the bridge unit are used to continue spatial vector modulation using the remaining coordinates.

3. The predictive control method for a hybrid topology seven-level inverter as described in claim 1, characterized in that, The process of constructing a discrete model for single-vector model prediction includes: obtaining the output voltage of the hybrid topology inverter according to Kirchhoff's voltage law, converting the voltage into current, and then using... Clarke Transformation, derive the output voltage at αβ The mathematical model in the orthogonal coordinate system, based on the sampling period, represents the continuous model as a discrete model in order to predict the reference voltage vector of the control target at the next moment.

4. The predictive control method for a hybrid topology seven-level inverter as described in claim 3, characterized in that, A value function without weighting factors is constructed. By calculating the value function, the basic voltage vector closest to the voltage predicted by the model is selected as the reference voltage vector for space vector modulation, and then the switching state of the switching device is controlled to output the voltage.

5. A computer-readable storage medium storing a plurality of instructions adapted for loading by a processor of a terminal device and executing the steps of the method according to any one of claims 1-4.

6. A control device, characterized in that, It includes a processor and a computer-readable storage medium, the processor being used to implement various instructions; the computer-readable storage medium being used to store a plurality of instructions adapted to be loaded by the processor and executed as steps in the method of any one of claims 1-4.

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