Mapping descriptor for read operations

Abstract

The present application relates to mapping descriptors for read operations. A memory device may include a memory array having a set of memory cells, a first cache may include a mapping table between logical addresses and physical addresses, and a second cache may include one or more descriptors of one or more physical addresses of the memory array. The descriptor may include a starting logical address, a starting physical address, and the number of addresses in the descriptor, and may be configured to identify frequently accessed addresses or groups of addresses. When an access command (e.g., a read command) is received, the first cache may be queried, and then the second cache may be queried (if there is a cache miss at the first cache). The physical address of the data of the memory array may be determined (and accessed) based on the descriptors stored in the second cache.

Description

[0001] Cross Reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / CN2020 / 086039, entitled “MAPPING DESCRIPTORS FOR READ OPERATIONS” filed by DUAN on April 22, 2020, which is assigned to its assignee and the entire contents of the application are expressly incorporated herein by reference.

[0003] The technical field relates to mapping descriptors for read operations. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one storage state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (such as FeRAM) can maintain its stored logic state for a long time even in the absence of external power. Volatile memory devices (such as DRAM) may lose their stored state when disconnected from external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include a memory array; and a controller coupled to the memory array and configured to cause the apparatus to: receive a read command including a logical address of the memory array of data requested by the read command; determine whether the logical address is missing from a first cache, the first cache including mappings between a first set of logical addresses and a first set of physical addresses of the memory array; identify a descriptor associated with the logical address and stored in a second cache based at least in part on determining that the logical address is missing from the first cache, the second cache including one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array; and retrieve the data from the memory array based at least in part on the descriptor stored in the second cache.

[0007] An apparatus is described. The apparatus may include a memory system including a memory array having a plurality of memory cells; a first cache configured to store a mapping between a first set of logical addresses and a first set of physical addresses of the memory array; and a second cache configured to store a descriptor between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptor identifies a starting physical address of the memory array and a length of data to be read for a read operation for an associated logical address.

[0008] An apparatus is described. The apparatus may include a memory array; and a controller coupled to the memory array and configured to cause the apparatus to: determine whether a number of read operations performed on a portion of the memory array satisfies a first threshold; determine whether a number of physical addresses of the portion of the memory array satisfies a second threshold based at least in part on determining that the number of read operations satisfies the first threshold; generate a descriptor for the portion of the memory array based at least in part on determining that the number of physical addresses of the portion of the memory array satisfies the second threshold; and store the descriptor in a cache associated with the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a computing environment that supports mapping descriptors for read operations according to examples as disclosed herein is described.

[0010] Figure 2 and 3 An example of a process flow diagram is illustrated to support mapping descriptors for read operations according to examples as disclosed herein.

[0011] Figure 4 A block diagram of a memory device supporting mapping descriptors for read operations is shown according to examples as disclosed herein.

[0012] Figure 5 and 6 A flowchart is shown of a method of supporting mapping descriptors for read operations according to examples as disclosed herein. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to mapping descriptors for read operations of a memory device. The memory device may be a nonvolatile memory device including nonvolatile memory cells, such as flash memory cells, such as NAND memory cells. The memory device may consist of one or more physical blocks containing valid data, invalid data, or no data. Each memory cell in a physical block may be associated with a physical address.

[0014] When a memory device receives an access command (e.g., a read command), the command may include a logical address, such as a logical address referenced by a host system in a physical to logical (P2L) mapping table. The memory device may store a mapping table for translating received logical addresses into physical addresses for accessing associated memory cells. The mapping table may be stored in a designated volatile memory (e.g., a cache) of the memory device. Because the memory device typically includes a large number of memory cells, the mapping table for mapping each physical address to a corresponding logical address may be large. This in turn may use a relatively large cache memory. In addition, some embodiments (e.g., a mobile memory device) may include a relatively small volatile memory, and may not be able to load the entire P2L mapping table into a volatile cache. Therefore, it may be necessary to reduce the size of the cache required to map physical addresses to logical addresses, which in turn may reduce the overall power consumption of the memory device.

[0015] According to the techniques described herein, power consumption and cache size (e.g., for storing mapping tables) of a memory device can be reduced. The memory device can include: a first cache (e.g., a mapping page cache (MPC)) configured to store a mapping table of a portion of a physical address of the memory device; and a second cache (e.g., a mapping descriptor cache (MDC)) for storing entries (e.g., compressed mapping data) associated with logical addresses and physical addresses of the memory device. The entry can be referred to as a descriptor and can include a starting logical address, a starting physical address, and the number of addresses of entries in the second cache.

[0016] When the memory device receives an access command (e.g., a read command) for data stored at a memory array of the memory device, the memory controller may determine whether the associated logical address is stored in the MPC. If the logical address is not stored in the MPC, the memory controller may determine whether the associated logical address is stored in the MDC. The memory controller may use the starting logical address and the number of addresses in the entry to determine whether the logical address is stored in the MDC. Based on the logical address stored in the MDC, the memory controller may determine the associated physical address and read the data from the memory array.

[0017] In other examples, the memory controller may be configured to generate and store descriptors to the MDC. The descriptors may be generated based on various criteria, such as the frequency with which data is accessed and the number of physical addresses to be included in the descriptors. The starting logical address, starting physical address, and length fields in the descriptors may represent a relatively small amount of data, which may allow the size of the MPC and MDC to be smaller. Smaller cache sizes may reduce the overall power consumption of the memory device.

[0018] First, in reference Figure 1 Features of the present disclosure are described in the context of a memory system described in reference to Figure 2 and 3 Features of the present disclosure are described in the context of the flowcharts described. Figures 4 to 6 These and other features of the present disclosure are further illustrated and referenced by the device diagram and flow chart associated with the mapping descriptor described for read operations.

[0019] Figure 1 1 is an example of a computing environment 100 that supports mapping descriptors for read operations according to an example of the present disclosure. The computing environment 100 may include a memory system 110, which may include media such as one or more non-volatile memory devices (e.g., memory device 140). The memory system 110 may include a first cache 135 and a second cache 137 coupled to the memory device 140. The first cache 135 and the second cache 137 may be configured to store entries for mapping logical addresses to physical addresses of the memory device 140.

[0020] The memory system 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing environment 100 may include a host system 105 coupled to one or more memory systems 110. In some examples, the host system 105 may be coupled to different types of memory systems 110. For example, the host system 105 may use the memory system 110 to write data to and read data from the memory device 140. As used herein, "coupled to" or "coupled with" generally refers to a connection between components or devices, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components or devices), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 105 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS) interface, etc. The physical host interface may be used to transfer data between the host system 105 and the memory system 110. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory system 110 and the host system 105.

[0023] The memory device may include any combination of different types of non-volatile memory devices and / or volatile memory devices. A volatile memory device (e.g., memory device 140) may be, but is not limited to, a random access memory (RAM) such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM). Figure 1In the illustrated example, memory device 140 may be a non-volatile memory device, such as a NAND memory device. In this example, memory device 140 may not include any volatile memory (such as DRAM). However, it should be recognized that in other examples, memory device 140 may include volatile and / or non-volatile memory.

[0024] Some examples of non-volatile memory devices (e.g., memory device 140) include "NAND" type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells.

[0025] The memory system controller 115 (or, for simplicity, controller 115) may communicate with the memory device 140 and / or the local memory 125 to perform operations such as reading data, writing data, or erasing data. The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory system controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0026] The memory system controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and controlling the operation of the memory system 110, including handling communications between the memory system 110 and the host system 105.

[0027] In some examples, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory system 110 in has been described as including a memory system controller 115, but in another example of the present disclosure, the memory system 110 may not include a memory system controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory system).

[0028] The memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 140. The memory system controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 140. The memory system controller 115 may further include host interface circuitry to communicate with the host system 105 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 140 and convert responses associated with the memory device 140 into information for the host system 105.

[0029] In some examples, memory device 140 may include one or more local media controllers (not shown) that operate in conjunction with memory system controller 115 to perform operations on one or more memory cells of memory device 140. An external controller (e.g., memory system controller 115) may externally manage memory device 140 (e.g., perform media management operations on memory device 140). In some examples, memory device 140 may be a locally managed memory device, which is a memory device combined with a local media controller that performs memory management operations on memory device 140 within the same memory device package.

[0030] In some examples, the memory system 110 may include a command manager 130, such as a flash translation layer (FTL), which may be configured as an interface between the host system 105 and the memory device 140. The command manager 130 may be included in the memory system controller 115 (e.g., the memory system controller 115 may perform the functions performed by the command manager 130, as described herein). In some implementations, the commands and signaling scheme used by the host system 105 may be different from the commands and signaling scheme used by the memory device 140. To facilitate communication between the host system 105 and the memory device 140 storing data on behalf of the host system, the command manager 130 may translate or otherwise convert host system 105 information to memory device 140 information, and vice versa. One or more cores may be used to perform the functions of the command manager 130. For example, one or more cores may be used to implement the functions of the command manager 130. In some examples, these cores may be dedicated to performing the functions of the command manager 130.

[0031] In some examples, the memory system 110 may include a first cache 135 (e.g., a mapping page cache). The first cache 135 may communicate with the command manager 130 during access operations to the memory device 140. For example, the memory device 140 may include one or more NAND memory cells. Since NAND memory cells cannot be updated in place, the command manager 130 may write data to a new page and mark the previous page as invalid. Therefore, an address mapping table may be used to translate a logical address (provided by the host system 105) into a physical flash address. In some cases, the first cache 135 may store a portion of the address mapping table. Additionally or alternatively, the remainder of the address mapping table (e.g., the entire address mapping table) may be stored to the memory device 140.

[0032] In some examples, an address mapping table (e.g., an address mapping table of the first cache 135) may be classified as a page level, a block level, or a hybrid scheme. The page level scheme translates a logical page number (LPN) in the flash memory into a physical page number (PPN). The block level scheme may reduce overall memory requirements by translating a logical block number (LBN) into a physical block number (PBN). The hybrid scheme may include one or more portions of both the page level and block level mapping schemes.

[0033] When using a page level scheme, the size of the first cache 135 may be relatively large to store the mapping table. However, as described herein, reducing the overall size of the memory system 110 and associated power usage may be beneficial, and thus reducing the overall size of the first cache 135 may be beneficial.

[0034] In some examples, the size of first cache 135 may be reduced by caching entries stored to first cache 135. When caching entries, entries utilized by a mapping table may be stored in flash memory (e.g., memory device 140 or another memory device), and mapping pages (e.g., units stored in first cache 135) may be loaded into first cache 135 when needed.

[0035] For a read operation, when the memory system 110 receives a read command from the host system 105 (e.g., at the command manager 130), the memory system 110 may be used to determine the physical page address of the logical page. To determine the physical page, the memory system 110 may look in the first cache 135. If the associated physical address is stored in the MPC, the physical address may be retrieved, and data may be read from the memory device 140 according to the physical address. If the physical page is not stored to the first cache 135, the memory system 110 may read the corresponding mapping page from a mapping table (e.g., an L2P table) stored in flash memory (e.g., stored in a dedicated portion of the memory device 140 or another memory device) to the mapping cache before reading the data from the memory device 140 according to the physical address. As described herein, the memory system 110 may include a second cache 137 (e.g., a mapping descriptor cache) to reduce the size of the first cache 135 and reduce the frequency of cache misses, where the memory system controller 115 would need to access the mapping table to find the corresponding physical location associated with the access command.

[0036] In some examples, the second cache 137 can communicate with the first cache 135 and / or the command manager 130 during access operations to the memory device 140. Figure 1 , the first cache 135 and the second cache 137 may be two different (e.g., separate) caches. However, in other examples (not shown), the first cache 135 and the second cache 137 may reside in the same cache and / or may be implemented using the local memory 125. For example, the first cache 135 and the second cache 137 may be different partitions of the same cache of memory units.

[0037] The second cache 137 may be configured to store descriptors associated with groups of frequently accessed addresses of the memory device 140. In some cases, groups or blocks of addresses of the memory device 140 may be frequently accessed together. Such groups of consecutive addresses may be simplified into descriptors, and the descriptors may be stored in the cache. For example, each entry stored to the second cache 137 may consist of a starting logical address, a starting physical address, and / or a length field (e.g., indicating the number of addresses in the descriptor). When a read command is received by the memory system 110, the associated logical address may be compared with a range of logical addresses stored to the second cache 137 (e.g., the logical address will be compared with the range of logical addresses based on the stored starting logical address and the length field). If the logical address is within the range stored to the second cache 137, the associated physical address may be determined, and data may be read from the memory device 140 according to the physical address. Therefore, when a read command is received, the memory system controller 115 may check the associated logical addresses of the first cache 135 and the second cache 137.

[0038] In some examples, the second cache 137 may be configured to store entries associated with frequently accessed (e.g., hot) data of the memory device 140. Although the memory device 140 may store multiple pages of data, most pages are relatively infrequently accessed (e.g., cold). The purpose of this patent is to increase the access speed of hot data, because the latency and performance of hot data access contribute greatly to the user experience. To track the temperature of the data, the memory device 140 may be divided (e.g., logically divided) into sub-LBA ranges. For example, a 128GB storage device may be divided into 128 1GB sub-LBA ranges.

[0039] When the memory system 110 receives a read command, the controller 115 may identify the corresponding LBA range to be read and increase the read count of the LBA range. One LBA read may correspond to an increase in the read count. As the read count increases, the data may become hotter. A mapping of a certain threshold of frequently accessed data (e.g., the number of most frequently accessed data) may be stored in the second cache 137 at any one time. As time goes by, different data is accessed more (or less) frequently, and the entries stored in the second cache 137 may be updated (e.g., removed and replaced by different entries). By using the second cache 137 in the memory system, the size of the first cache 135 may be reduced, and the overall power consumption and size of the memory system 110 may be reduced.

[0040] The memory system 110 may also include additional circuitry or components not illustrated. In some examples, the memory system 110 may include additional caches, memory devices (e.g., DRAM), and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory system controller 115 and decode the addresses to access the memory devices 140.

[0041] In other examples, the memory system 110 may include a non-transitory computer-readable medium (CRM) (e.g., local memory 125 and / or memory device 140) storing instructions (e.g., firmware) for performing the methods described herein for mapping descriptors (e.g., methods 200, 300, 500, and 600). For example, the instructions, when executed by the memory system controller 115 (or the processor 120 of the memory system controller 112), may cause the memory system controller 115 to perform the methods described herein for mapping descriptors.

[0042] Figure 2 An example of a flowchart 200 is shown for supporting a mapping descriptor for a read operation according to an example disclosed herein. Flowchart 200 may illustrate a host system (eg, as described in reference Figure 1 host system 105) and a memory system (e.g., as described in reference Figure 1 The memory system may include a controller, a first cache (e.g., a mapped page cache or MPC), a second cache (e.g., a mapped descriptor cache or MDC), and a memory array. The components of the memory system may be as described in reference Figure 1 2. Flowchart 200 may illustrate a memory system receiving a read command (e.g., from a host system) and accessing one or more memory cells of a memory array using an MDC. As described herein, an MDC may include one or more map entries (e.g., compressed map entries), which may reduce overall power consumption and size of the memory array.

[0043] At 205, an access command may be received. In some examples, the memory device may receive an access command from a host system. For example, the access command may be a read command that includes a logical address (e.g., a logical block address) of one or more memory cells of a memory array. The read command may be received and processed by a controller, such as described in reference to Figure 1 The memory system controller 115 described herein. The controller may determine the physical address of the memory array to be accessed based on receiving the read command. The controller may utilize one or more entries (eg, descriptors) stored in the MDC to determine the physical address of the memory array and access the associated data.

[0044] At 210, a determination may be made as to whether the logical address associated with the access command is stored at the MPC. In some examples, the controller may determine whether the logical address associated with the access command is stored at the MPC. As discussed herein, the MPC may include a mapping table (e.g., a portion of a mapping table) between logical addresses and physical addresses of the memory array. The controller may ultimately utilize the MDC based on the logical address not being included (e.g., stored) in the MPC.

[0045] At 215, if the logical address associated with the access command is stored at the MPC, then the physical address of the memory array associated with the logical address of the access command may be determined. In some examples, the controller may determine the physical address of the memory array associated with the logical address of the access command. For example, a mapping table (e.g., a portion of a mapping table) of the MPC may include entries (e.g., rows) that map logical addresses to physical addresses. Thus, if the logical address is stored to the MPC, then the controller may determine the associated physical address based on the table entry. After determining the physical address of the memory array, the controller may retrieve (e.g., access) data stored to the corresponding physical address of the memory array. In some examples, the controller may provide (e.g., transmit) the retrieved data to the host system.

[0046] At 220, if the logical address associated with the access command is not stored at the MPC, it may be determined whether the logical address associated with the access command is stored at the MDC. In some examples, the controller may determine whether the logical address associated with the access command is stored at the MDC. As discussed herein, the MDC may include entries (e.g., compressed entries) referred to as descriptors. Each descriptor may include a starting logical address, a starting physical address, and / or a length field indicating the length of the respective entry. Table 1, shown below, illustrates example descriptors saved to the MDC.

[0047] Starting LPN Starting PPN length 100 20 128 500 200 2

[0048] Table 1

[0049] For example, the first entry describes a starting logical address (logical page number (LPN)) of "100" and a length of 128. Similarly, the second entry describes a starting logical address of "500" and a length of 2. Thus, the first entry may represent logical addresses 100 to 228, and the second entry may represent logical addresses 500 to 502. Thus, in this example, at 220, the controller may determine whether the logical address of the received access command falls within any range of logical addresses by using at least the starting logical address and the length field.

[0050] At 225, if the logical address associated with the access command is not stored at the MDC, a descriptor including at least the logical address and the corresponding physical address may be generated. In some examples, the controller may optionally generate a descriptor including at least the logical address and the corresponding physical address. The memory address may determine the physical address associated with the logical address based on one or more previous access operations. In some examples, the descriptor may be generated based on a memory system (e.g., a controller) receiving multiple write commands with sequential logical addresses. In this example, the starting logical address may be based on the first logical address in the sequence, and the length field may be based on the number of logical addresses included in the sequence.

[0051] In some examples, the MPC may be used to generate descriptors. In some examples, the controller may use the MPC to generate descriptors. For example, the controller may load a page of physical addresses of the memory array into the MPC. The controller may generate one or more descriptors based on the page of physical addresses to store in the MDC. Additional details on the generation of descriptors are provided in Figure 4 .

[0052] At 230, the generated descriptor may optionally be stored in the MDC. In some examples, the controller may optionally store the generated descriptor in the MDC. As discussed herein (e.g., with reference to Figure 4 ), descriptors may be stored to the MDC based on one or more criteria. For example, descriptors may be stored to the MDC based on a threshold number of accesses to associated data (e.g., the data's associated physical address). For example, the controller may track the number of access operations performed on a subset (e.g., a range) of logical addresses. When a subset of logical addresses experiences a threshold number of access operations, an associated descriptor may be generated and stored to the MDC.

[0053] In other examples, descriptors may be stored to the MDC based on the length (e.g., the number of logical addresses and / or corresponding physical addresses in an entry) meeting a threshold. For example, the controller may determine the length of the generated descriptor based on the length field. Descriptors whose lengths meet the threshold number may be stored to the MDC. For additional details on storing descriptors to the MDC, refer to Figure 4 .

[0054] At 235, the memory array may be accessed. In some examples, the controller may access the memory array. In some cases, if the MDC does not include a logical address, the controller may skip features 225 and 230 and go directly to 235. The controller may retrieve (e.g., access) data stored to the physical address associated with the logical address of the generated (and stored) descriptor. In some examples, the controller may provide (e.g., transmit) the retrieved data to the host system.

[0055] At 240, if the logical address associated with the access command is stored at the MDC, then the physical address of the memory array associated with the logical address of the access command may be determined. In some examples, the controller may determine the physical address of the memory array associated with the logical address of the access command. For example, as described with reference to Table 1, the MDC may include entries including a starting logical address, a starting physical address, and / or a length field indicating the length of the corresponding entry. To determine whether the logical address is stored to the MDC, the controller may determine whether the logical address of the received access command falls within a range of logical addresses by using at least the starting logical address and the length field.

[0056] When it is determined that the logical address is included in the range of the stored descriptors, the corresponding physical address can be calculated. To calculate the physical address, the position of the logical address in the sequence can be determined. For example, the logical address can be "103", which can be the fourth (4) in the order of logical addresses. Because the starting physical address can be "20", the controller can determine (e.g., calculate) that the corresponding physical address is "23". The corresponding physical address can be determined for any logical address included in the descriptors stored to the MDC.

[0057] At 245, after determining the physical address of the memory array corresponding to the received logical address, the data stored at the corresponding physical address of the memory array can be retrieved. In some examples, the controller can retrieve (e.g., access) the data stored at the corresponding physical address of the memory array. In some examples, the controller can provide (e.g., transmit) the retrieved data to the host system.

[0058] Figure 3 An example of a flowchart 300 is shown for supporting a mapping descriptor for a read operation according to an example disclosed herein. Flowchart 300 may illustrate a host system (eg, as described in reference Figure 1 host system 105) and a memory system (e.g., as described in reference Figure 1 The memory system may include a controller, a first cache (e.g., a mapping page cache), a second cache (e.g., a mapping descriptor cache), and a memory array. The components of the memory system may be as described in reference Figure 1 and 2 300 may illustrate a memory system receiving a plurality of read commands (e.g., from a host system) and determining whether to generate entries (e.g., descriptors) and / or store entries to an MDC. As described herein, entries stored to an MDC may reduce overall power consumption and size of a memory array.

[0059] At 305, a plurality of access commands may be received. In some examples, the memory device may receive a plurality of access commands from a host system. For example, the access commands may be read commands, each of which includes a logical address (e.g., a logical block address) of one or more memory cells of a memory array. The read commands may be received and processed by a controller, such as described in reference to Figure 1 1. The memory system controller 115 described herein. In some examples, the memory array may be divided (e.g., logically subdivided) into one or more sub-blocks, each of which is associated with a range of logical addresses. The controller may track the number of access operations performed on each sub-block. For example, when a single read command is received for a logical address within a sub-block, the controller may increment a value of access operations performed on the sub-block (e.g., using a counter).

[0060] At 310, it may be determined whether a number of read operations performed on a sub-block of a memory array satisfies a threshold. In some examples, the controller may determine whether a number of read operations performed on a sub-block of a memory array satisfies a threshold (e.g., a first threshold). The number of read operations performed on a sub-block may indicate whether the sub-block is frequently accessed (e.g., whether it contains "hot" data). It may be desirable to generate descriptors associated with hot data to reduce latency associated with future access operations to the data and to avoid using an MPC to determine a physical address associated with the data. In some examples, the threshold number may be a configurable (e.g., adjustable) number based on desired design parameters of the memory system. If the number of read operations satisfies the threshold, descriptors for one or more logical addresses contained within the sub-block may be generated.

[0061] At 315, if the number of read operations performed on the sub-block of the memory array does not satisfy the threshold (e.g., the number is below the threshold), then descriptors for any logical addresses included in the sub-block may be avoided from being generated. In some examples, the controller may avoid generating descriptors for any logical addresses included in the sub-block. The controller may determine (e.g., re-determine) whether the number of read operations satisfies the threshold at another time.

[0062] At 320, based on the number of read operations performed on the sub-block satisfying the threshold, it may be determined whether the number of physical addresses of the sub-block satisfies a threshold (e.g., a second threshold). In some examples, the controller may determine whether the number of physical addresses of the sub-block satisfies a threshold (e.g., a second threshold). When the number of read operations satisfies the first threshold, the controller may read data from the associated sub-block of the memory array. For example, the controller may read the physical address associated with each logical address included in the sub-block. As the controller reads the data, it may identify (e.g., track) groups of consecutive physical addresses. The consecutive physical addresses of each group may be compared to a second threshold, which may be a configurable (e.g., adjustable) value based on desired design parameters of the memory system. If the number of consecutive physical addresses satisfies the second threshold, a descriptor of one or more logical addresses included in the sub-block may be generated.

[0063] At 325, if the number of consecutive physical addresses read from the memory array does not satisfy the second threshold (e.g., the number is below the second threshold), then descriptors for corresponding logical addresses included in the sub-block may be avoided. In some examples, the controller may avoid generating descriptors for corresponding logical addresses included in the sub-block. The controller may determine (e.g., re-determine) whether the number of consecutive physical addresses satisfies the second threshold at another time.

[0064] At 330, based on the number of consecutive physical addresses satisfying the second threshold, a descriptor may be generated for storage at the MDC. In some examples, the controller may generate a descriptor for storage at the MDC. The descriptor may include a starting logical address, a starting physical address, and / or a length of the descriptor. The generated descriptor may be stored to the MDC.

[0065] At 335, an attempt may be made to store the generated descriptor to the MDC. In some examples, the controller may attempt to store the generated descriptor to the MDC. In some cases, the MDC may be full (e.g., full of one or more stored descriptors), and the generated descriptor may or may not be stored. Whether to store the generated descriptor may depend on whether the MDC is full and whether the length of the descriptor is greater than (or less than) the length of any of the descriptors stored to the MDC. In some examples, the stored MDC may be overwritten (e.g., deleted and replaced by the generated descriptor).

[0066] At 340, it may be determined whether the MDC is full. In some examples, the controller may determine whether the MDC is full. In some examples, the MDC may be configured to store a limited number of descriptors. In this example, the controller may determine whether the MDC contains a limited number of descriptors, or whether additional descriptors may be stored. In other examples, the MDC may be configured to store a limited amount of data (e.g., a limited number of bytes). In this example, the controller may determine whether the MDC contains enough space to store the size of the generated descriptor.

[0067] At 345, it may be determined that the MDC is not full. In some examples, the controller may determine that the MDC is not full. Based on the MDC having available space to store one or more descriptors, the controller may store the generated descriptors to the MDC. The stored MDC may be used to determine a physical address of the memory array based on the memory system receiving an access command including a logical address.

[0068] At 350, it may be determined that the MDC is full and whether the length of the generated descriptor exceeds the length of any stored descriptor. In some examples, the controller may determine that the MDC is full and may determine whether the length of the generated descriptor exceeds the length of any stored descriptor. Entries may be stored to the MDC based on their lengths. For example, the entries may be stored in the MDC in descending order, and the controller may be configured to compare the size of the generated descriptor to the smallest entry. If the generated descriptor is larger than the smallest entry, the smallest entry will be removed from the MDC and the generated descriptor will be stored.

[0069] At 355, the size of the generated descriptor is not greater than any of the descriptors stored to the MDC. In this example, the generated descriptor may not be stored to the MDC. In this example, the previously stored entries in the MDC will still be stored in the MDC.

[0070] At 360, the size of the generated descriptor may be larger than the smallest descriptor stored to the MDC. In this example, the smallest descriptor stored to the MDC may be removed (e.g., deleted) and the generated descriptor may be stored to the MDC. The controller may store the generated descriptor to the MDC according to the size of the generated descriptor, so that the MDC is organized according to the size of the stored descriptors. The stored descriptor may be used to determine the physical address of the memory array based on the memory system receiving an access command including the logical address. Utilizing the MDC may reduce the overall power consumption and size of the memory device that would otherwise be caused by using only the MPC to determine the physical address of the memory array.

[0071] Figure 4 A block diagram 400 is shown of a memory device 405 supporting mapping descriptors for read operations according to examples as disclosed herein. The memory device 405 may be a memory device as described in reference to Figures 1 to 3 Memory device 405 may include a receiving component 410, a determining component 415, an identifying component 420, a retrieving component 425, a generating component 430, a storing component 435, a reading component 440, and a removing component 445. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0072] The receiving component 410 can receive, at a memory device, a read command including a logical address of a memory array of data requested by the read command.

[0073] The determining component 415 can determine whether a logical address is missing from a first cache of the memory device, the first cache comprising a mapping between a first set of logical addresses and a first set of physical addresses of the memory array. In some examples, the determining component 415 can determine whether a number of read operations performed on a portion of the memory array satisfies a first threshold. In some examples, the determining component 415 can determine whether a number of physical addresses of the portion of the memory array satisfies a second threshold based on determining that the number of read operations satisfies the first threshold.

[0074] In some examples, the determination component 415 can determine the number of logical addresses of the subset of the second set of logical addresses. In some examples, the determination component 415 can determine that the logical address is included in the subset of the second set of logical addresses based on identifying a starting logical address of the subset of the second set of logical addresses and determining the number of logical addresses in the subset of the second set of logical addresses. In some examples, the determination component 415 can determine the number of addresses in the subset of the second set of logical addresses between the starting logical address and the logical address requested by the read command.

[0075] In some examples, the determination component 415 may determine that a descriptor associated with the logical address of the read command is not stored in the second cache. In some examples, the determination component 415 may determine whether the cache is full based on attempting to store the second descriptor. In some examples, the determination component 415 may determine whether the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array. In some examples, the determination component 415 may determine whether the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array.

[0076] In some examples, the determination component 415 can determine whether the number of consecutive physical addresses satisfies a second threshold, wherein generating the descriptor is based on the number satisfying the second threshold. In some examples, the determination component 415 can determine consecutive physical addresses of a portion of the memory array that satisfy the first threshold and the second threshold.

[0077] The identification component 420 can identify a descriptor associated with the logical address and stored in a second cache based on determining that the logical address is missing from the first cache, the second cache including one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array. In some examples, the identification component 420 can identify a starting logical address of a subset of the second set of logical addresses.

[0078] In some examples, the identification component 420 may identify a physical address associated with the logical address based on a descriptor stored in the second cache, wherein retrieving data is based on identifying the physical address. In some examples, the identification component 420 may identify a starting logical address of a subset of the second set of logical addresses based on the identification descriptor. In some examples, the identification component 420 may identify a starting physical address of a subset of the second set of physical addresses associated with the subset of the second set of logical addresses, wherein the physical address associated with the logical address requested by the read command is based on the identified starting physical address of the subset of the second set of physical addresses and a number of addresses between the starting logical address and the logical address requested by the read command.

[0079] In some examples, identification component 420 may identify a portion of data that has undergone a number of read operations that satisfies a first threshold. In some examples, identification component 420 may identify a physical address of the portion of data that satisfies the first threshold. In some examples, identification component 420 may identify a portion of the physical address having consecutive physical addresses based on identifying the physical address of the portion of data that satisfies the first threshold, wherein generating the descriptor is based on identifying the portion of the physical address having consecutive physical addresses.

[0080] The retrieval component 425 can retrieve data from the memory array based on the descriptors stored in the second cache.

[0081] The generation component 430 may generate a descriptor for the portion of the memory array based on determining that the number of physical addresses of the portion of the memory array satisfies a second threshold. In some examples, the generation component 430 may generate a descriptor associated with the logical address of the memory array and the corresponding physical address based on determining that the descriptor associated with the logical address of the read command is not stored in the second cache. In some examples, the generation component 430 may generate a second descriptor for the second portion of the memory array based on the number of physical addresses of the second portion of the memory array satisfying the second threshold.

[0082] The storage component 435 may store the descriptor in a cache associated with the memory array. In some examples, the storage component 435 may store the descriptor to a second cache. In some examples, the storage component 435 may attempt to store the second descriptor in a cache associated with the memory array based on generating the second descriptor. In some examples, the storage component 435 may store the second descriptor in the cache based on removing the descriptor. In some examples, the storage component 435 may avoid storing the second descriptor in the cache based on determining that the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array.

[0083] The read component 440 can read memory cells of the memory array associated with the identified physical address. In some examples, the read component 440 can access data associated with the number of read operations that meet the first threshold more frequently than data associated with the number of read operations that do not meet the first threshold over a duration of time.

[0084] The removal component 445 can remove the descriptor from the cache based on determining that the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array.

[0085] Figure 5 A flowchart illustrating a method 500 for supporting a mapping descriptor for a read operation according to an example as disclosed herein is shown. The operations of the method 500 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 500 may be implemented by reference to Figure 4 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0086] At 505, the memory device may receive at the memory device a read command including a logical address of a memory array of data requested by the read command. Operation 505 may be performed according to the methods described herein. In some examples, aspects of operation 505 may be performed as described in reference to Figure 4 The receiving component described here is executed.

[0087] At 510, the memory device may determine whether the logical address is missing from a first cache of the memory device, the first cache comprising a mapping between a first set of logical addresses of the memory array and a first set of physical addresses. Operation 510 may be performed according to the methods described herein. In some examples, aspects of operation 510 may be performed as described in reference to Figure 4 Determine the components to perform the description.

[0088] At 515, the memory device may identify a descriptor associated with the logical address and stored in a second cache of the memory device based on determining that the logical address is missing from the first cache, the second cache including one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array. Operation 515 may be performed according to the methods described herein. In some examples, aspects of operation 515 may be performed as described in reference to Figure 4 The identification components described are performed.

[0089] At 520, the memory device may retrieve data from the memory array based on the descriptor stored in the second cache. Operation 520 may be performed according to the methods described herein. In some examples, aspects of operation 520 may be performed as described in reference to Figure 4 Describes the retrieval component to perform.

[0090] In some examples, an apparatus as described herein may perform a method such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device, a read command of a logical address of a memory array of data requested by the read command; determining whether the logical address is missing from a first cache of the memory device, the first cache including mappings between a first set of logical addresses and a first set of physical addresses of the memory array; identifying a descriptor associated with the logical address and stored in a second cache of the memory device based on determining that the logical address is missing from the first cache, the second cache including one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array; and retrieving the data from the memory array based on the descriptor stored in the second cache.

[0091] In some examples of the method 500 and apparatus described herein, identifying a descriptor may include operations, features, means, or instructions for: identifying a starting logical address of a subset of the second set of logical addresses; and determining a number of logical addresses of the subset of the second set of logical addresses.

[0092] Some instances of the method 500 and apparatus described herein may further include operations, features, components, or instructions for determining that the logical address may be included in the subset of the second set of logical addresses based on identifying the starting logical address of the subset of the second set of logical addresses and determining the number of logical addresses in the subset of the second set of logical addresses.

[0093] Some examples of method 500 and apparatus described herein may further include operations, features, means, or instructions for identifying a physical address associated with the logical address based on the descriptor stored in the second cache, wherein retrieving the data may be based on identifying the physical address.

[0094] In some instances of the method 500 and apparatus described herein, identifying the physical address may include operations, features, components, or instructions for: identifying a starting logical address of a subset of the second set of logical addresses based on identifying the descriptor; and determining a number of addresses in the subset of the second set of logical addresses that may be between the starting logical address and the logical address requested by the read command.

[0095] Some instances of the method 500 and apparatus described herein may further include operations, features, components, or instructions for identifying a starting physical address of a subset of the second set of physical addresses that may be associated with the subset of the second set of logical addresses, wherein the physical address associated with the logical address requested by the read command may be based on the identified starting physical address of the subset of the second set of physical addresses and the number of addresses between the starting logical address and the logical address requested by the read command.

[0096] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for determining that the descriptor associated with the logical address of the read command may not be stored in the second cache; generating the descriptor associated with the logical address and the corresponding physical address of the memory array based on determining that the descriptor associated with the logical address of the read command may not be stored in the second cache; and storing the descriptor to the second cache.

[0097] In some examples of the method 500 and apparatus described herein, retrieving the data from the memory array may include an operation, feature, means, or instruction for reading a memory cell of the memory array associated with the identified physical address.

[0098] Figure 6 A flowchart illustrating a method 600 for supporting a mapping descriptor for a read operation according to an example as disclosed herein is shown. The operations of the method 600 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 600 may be implemented by reference to Figure 4The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0099] At 605, the memory device may determine whether the number of read operations performed on a portion of the memory array satisfies a first threshold. Operation 605 may be performed according to the methods described herein. In some examples, aspects of operation 605 may be as described in reference to Figure 4 Determine the components to perform the description.

[0100] At 610, the memory device may determine whether the number of physical addresses of the portion of the memory array satisfies a second threshold based on determining that the number of read operations satisfies the first threshold. Operation 610 may be performed according to the methods described herein. In some examples, aspects of operation 610 may be described by reference to Figure 4 Determine the components to perform the description.

[0101] At 615, the memory device may generate a descriptor for the portion of the memory array based on determining that the number of physical addresses of the portion of the memory array satisfies the second threshold. Operation 615 may be performed according to the methods described herein. In some examples, aspects of operation 615 may be described by reference to Figure 4 Described generation components to execute.

[0102] At 620, the memory device may store the descriptor in a cache associated with the memory array. Operation 620 may be performed according to the methods described herein. In some examples, aspects of operation 620 may be performed as described in reference to Figure 4 The storage components described are executed.

[0103] In some examples, an apparatus as described herein may perform a method such as method 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining whether a number of read operations performed on a portion of a memory array satisfies a first threshold; determining whether a number of physical addresses of the portion of the memory array satisfies a second threshold based on determining that the number of read operations satisfies the first threshold; generating a descriptor for the portion of the memory array based on determining that the number of physical addresses of the portion of the memory array satisfies the second threshold; and storing the descriptor in a cache associated with the memory array.

[0104] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: generating a second descriptor for a second portion of the memory array based on the number of physical addresses of the second portion of the memory array satisfying the second threshold; attempting to store the second descriptor in the cache associated with the memory array based on generating the second descriptor; and determining whether the cache is full based on attempting to store the second descriptor.

[0105] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for determining whether the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array; removing the descriptor from the cache based on determining that the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array; and storing the second descriptor in the cache based on removing the descriptor.

[0106] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for determining whether the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array; and avoiding storing the second descriptor in the cache based on determining that the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array.

[0107] Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: identifying a portion of data that has undergone the number of read operations that satisfies the first threshold; identifying a physical address of the portion of data that satisfies the first threshold; and identifying a portion of the physical address having a contiguous physical address based on identifying the physical address of the portion of data that satisfies the first threshold, wherein generating the descriptor may be based on identifying the portion of the physical address having the contiguous physical address.

[0108] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for determining whether the number of the consecutive physical addresses satisfies the second threshold, wherein generating the descriptor may be based on the number satisfying the second threshold.

[0109] In some examples of the method 600 and apparatus described herein, generating the descriptor may include operations, features, means, or instructions for determining consecutive physical addresses of the portion of the memory array that satisfy the first threshold and the second threshold.

[0110] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for enabling data associated with the number of read operations that satisfy the first threshold to be accessed more frequently within a duration than data associated with the number of read operations that do not satisfy the first threshold.

[0111] In some examples of the method 600 and apparatus described herein, the descriptor includes a starting physical address of the portion of the memory array and the number of physical addresses of the portion of the memory array.

[0112] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0113] An apparatus is described. The apparatus may include: a memory device including a memory array having a set of memory cells; a first cache configured to store a mapping between a first set of logical addresses and a first set of physical addresses of the memory array; and a second cache configured to store a descriptor between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptor identifies a starting physical address of the memory array and a length of data to be read for a read operation for an associated logical address.

[0114] In some examples, the second cache may be configured to store the descriptors between the second set of logical addresses and the second set of physical addresses based on a number of read operations performed on a portion of the memory array associated with the second set of physical addresses. In some examples, the memory device may be configured to update the descriptors stored at the second cache based on the number of read operations performed on a portion of the memory array associated with the second set of physical addresses.

[0115] In some examples, the memory device may be configured to receive a read command including a logical address of data of the memory array and read the associated data based on the descriptor stored at the second cache.

[0116] In some examples, the memory system may be configured to determine a physical address of the second set of physical addresses that may be associated with the logical address of the read command, wherein the memory device may be configured to read the associated data based on determining the physical address of the data.

[0117] In some examples, the second set of logical addresses comprises a set of sequential logical addresses, and wherein the second set of physical addresses comprises a set of sequential physical addresses. In some examples, the first cache may be coupled to the memory array, and the second cache may be coupled to the first cache. In some examples, the first cache and the second cache may be located in a volatile memory coupled to the memory array.

[0118] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have various bit widths.

[0119] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0120] The term "coupled" refers to a condition that transitions from an open-circuit relationship between components (where signals are currently unable to be transmitted between components through conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components through conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through conductive paths that previously did not allow signals to flow.

[0121] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between components, they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0122] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0123] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices, including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated".

[0124] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "example" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples." However, these techniques may be practiced without these specific details. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the examples described.

[0125] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label without regard to the second reference label.

[0126] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0127] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0128] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features implementing the functions may also be physically located at various locations, including portions distributed so that the functions are implemented at different physical locations. In addition, as used herein, the "or" used in the claims, such as in the list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of"), indicates that the list includes a list such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as a reference to a set of closed conditions. For example, the example steps described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "based at least in part on."

[0129] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special purpose computer. By way of example but not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired process code device in the form of instructions or data structures and can be accessed by a general or special purpose computer or a general or special purpose processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then the coaxial cable, optical cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0130] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory array; and a controller coupled to the memory array and configured to cause the apparatus to: receiving a read command, the read command including a logical address of the memory array of data requested by the read command; determining whether the logical address is missing from a first cache, the first cache comprising a mapping between a first set of logical addresses and a first set of physical addresses of the memory array; identifying, based at least in part on determining that the logical address is missing from the first cache, a descriptor associated with the logical address and stored in a second cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptor includes a starting logical address of the second set of logical addresses, a starting physical address of the second set of physical addresses, and a length indicating a number of logical addresses associated with the descriptor; and The data is retrieved from the memory array based at least in part on the descriptor stored in the second cache.

2. The apparatus of claim 1 , wherein identifying the descriptor comprises: A starting logical address of a subset of the second set of logical addresses is identified based at least in part on the starting logical address, wherein the second set of logical addresses includes the number of logical addresses.

3. The apparatus of claim 2, wherein the controller is configured to cause the apparatus to: The logical address is determined to be included in the subset of the second set of logical addresses based at least in part on identifying the starting logical address of the subset of the second set of logical addresses and determining the number of logical addresses in the subset of the second set of logical addresses.

4. The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: A physical address associated with the logical address is identified based at least in part on the descriptor stored in the second cache, wherein retrieving the data is based at least in part on identifying the physical address.

5. The apparatus of claim 4, wherein identifying the physical address comprises: identifying a subset of the second set of logical addresses based at least in part on the starting logical address; and A second number of addresses in the subset of the second set of logical addresses between the starting logical address and the logical address requested by the read command is determined.

6. The apparatus of claim 5, wherein the controller is configured to cause the apparatus to: A subset of the second set of physical addresses associated with the subset of the second set of logical addresses is identified based at least in part on the starting physical address, wherein the physical address associated with the logical address requested by the read command is based at least in part on the starting physical address of the subset of the second set of physical addresses and the number of addresses between the starting logical address and the logical address requested by the read command.

7. The apparatus of claim 1, wherein the controller is configured to cause the apparatus to: determining that the descriptor associated with the logical address of the read command is not stored in the second cache; generating the descriptor associated with the logical address and a corresponding physical address of the memory array based at least in part on determining that the descriptor associated with the logical address of the read command is not stored in the second cache; and The descriptor is stored in the second cache.

8. The apparatus of claim 1 , wherein retrieving the data from the memory array comprises: Memory cells of the memory array associated with physical addresses corresponding to the logical addresses are read.

9. A device comprising: A memory system comprising a memory array having a plurality of memory cells; a first cache configured to store a mapping between a first set of logical addresses and a first set of physical addresses of the memory array; as well as a second cache configured to store descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptors include a starting logical address of the second set of logical addresses, a starting physical address of the second set of physical addresses, and a length indicating a number of logical addresses associated with the descriptors.

10. The apparatus of claim 9, wherein the second cache is configured to store the descriptors between the second set of logical addresses and the second set of physical addresses based at least in part on a number of read operations performed on a portion of the memory array associated with the second set of physical addresses.

11. The apparatus of claim 10, wherein the memory system is configured to update the descriptor stored at the second cache based at least in part on the number of read operations performed on the portion of the memory array associated with the second set of physical addresses.

12. The apparatus of claim 9, wherein the memory system is configured to receive a read command including a logical address of data of the memory array and read associated data based at least in part on the descriptor stored at the second cache.

13. The apparatus of claim 12, wherein the memory system is configured to determine a physical address of the second set of physical addresses associated with a logical address of the read command, wherein the memory system is configured to read the associated data based at least in part on determining the physical address of the data.

14. The apparatus of claim 9, wherein the second set of logical addresses comprises a plurality of sequential logical addresses, and wherein the second set of physical addresses comprises a plurality of sequential physical addresses.

15. The apparatus of claim 9, wherein the first cache is coupled to the memory array and the second cache is coupled to the first cache.

16. The apparatus of claim 9, wherein the first cache and the second cache are located in a volatile memory coupled to the memory array.

17. An apparatus comprising: Memory array; and a controller coupled to the memory array and configured to cause the apparatus to: determining whether a number of read operations performed on a portion of the memory array satisfies a first threshold; determining whether a number of physical addresses of the portion of the memory array satisfies a second threshold based at least in part on determining that the number of read operations satisfies the first threshold; generating a descriptor for the portion of the memory array based at least in part on determining that the number of physical addresses of the portion of the memory array satisfies the second threshold; as well as The descriptors are stored in a cache associated with the memory array.

18. The apparatus of claim 17, wherein the controller is configured to cause the apparatus to: generating a second descriptor for a second portion of the memory array based at least in part on a number of physical addresses of the second portion of the memory array satisfying the second threshold; attempting to store the second descriptor in the cache associated with the memory array based at least in part on generating the second descriptor; and A determination is made whether the cache is full based at least in part on attempting to store the second descriptor.

19. The apparatus of claim 18, wherein the controller is configured to cause the apparatus to: determining whether the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array; removing the descriptor from the cache based at least in part on determining that the number of physical addresses of the second portion of the memory array satisfies the number of physical locations of the portion of the memory array; and The second descriptor is stored in the cache based at least in part on removing the descriptor.

20. The apparatus of claim 18, wherein the controller is configured to cause the apparatus to: determining whether the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array; and Storing the second descriptor in the cache is avoided based at least in part on determining that the number of physical addresses of the second portion of the memory array does not satisfy the number of physical locations of the portion of the memory array.

21. The apparatus of claim 18, wherein the controller is configured to cause the apparatus to: identifying a portion of data that has undergone said number of read operations satisfying said first threshold; identifying a physical address of the portion of data that satisfies the first threshold; and A portion of the physical address having a contiguous physical address is identified based at least in part on identifying the physical address of the portion of data that satisfies the first threshold, wherein generating the descriptor is based at least in part on identifying the portion of the physical address having the contiguous physical address.

22. The apparatus of claim 21, wherein the controller is configured to cause the apparatus to: A determination is made as to whether the number of the contiguous physical addresses satisfies the second threshold, wherein generating the descriptor is based at least in part on the number satisfying the second threshold.

23. The apparatus of claim 18, wherein generating the descriptor comprises: Contiguous physical addresses of the portion of the memory array that satisfy the first threshold and the second threshold are determined.

24. The apparatus of claim 18, wherein data associated with the number of read operations that satisfy the first threshold is accessed more frequently over a duration than data associated with the number of read operations that do not satisfy the first threshold.

25. The apparatus of claim 18, wherein the descriptor comprises a starting physical address of the portion of the memory array and the number of physical addresses of the portion of the memory array.

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