Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a node connection line, which is in the same layer as a corresponding one of the multiple voltage supply lines, the node connection line is connected to the first capacitor electrode through a first through hole, and is connected to the semiconductor material layer through a second through hole; and an anti-interference block, which is in the same layer as the second capacitor electrode. A corresponding one of the multiple voltage supply lines is connected to the anti-interference block through a third through hole. The anti-interference block includes a first arm and a second arm. Along the first direction, a portion of the node connection line at a position connected to the semiconductor material layer through the second through hole is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising: a plurality of gate lines, which extend in a first direction respectively; a plurality of data lines, which extend in a second direction respectively; a plurality of voltage supply lines, which extend in the second direction respectively; and a pixel driving circuit; wherein the pixel driving circuit comprises a driving transistor; a first transistor; a second transistor; a third transistor and a storage capacitor; and the storage capacitor comprises a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and an insulating layer between the first capacitor electrode and the second capacitor electrode; wherein the array substrate comprises: a semiconductor material layer on a base substrate; a node connection A wiring line, which is in the same layer as a corresponding one of the multiple voltage supply lines, the node connection line is connected to the first capacitor electrode through a first through hole, and is connected to the semiconductor material layer through a second through hole; and an anti-interference block, which is in the same layer as the second capacitor electrode, the corresponding one of the multiple voltage supply lines is connected to the anti-interference block through a third through hole, the anti-interference block includes a first arm and a second arm; wherein, along the first direction, a portion of the node connection line at a position connected to the semiconductor material layer through the second through hole is spaced apart from a first adjacent data line through the first arm, and is spaced apart from a second adjacent data line through the second arm.

[0004] Optionally, the first electrode of the third transistor and the second electrode of the first transistor are part of an integral structure in a corresponding one of a plurality of sub-pixels; the node connection line is connected to the first electrode of the third transistor through the second through hole; and the orthographic projection of the first arm on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate.

[0005] Optionally, an orthographic projection of the second arm on the base substrate at least partially overlaps with an orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate.

[0006] Optionally, an orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate substantially covers at least 30% of an orthographic projection of the second arm on the base substrate.

[0007] Optionally, the anti-interference block also includes a handle; a corresponding one of the multiple voltage supply lines is connected to the handle through the third through hole; the first arm includes an L-shaped portion and a first end portion; the second arm includes a base, a second end portion, and a connecting portion connecting the base and the second end portion; wherein the base connects the L-shaped portion and the handle.

[0008] Optionally, the first electrode and the active layer of the third transistor are part of the overall structure in a corresponding one of the multiple sub-pixels; the node connection line is connected to the first electrode of the third transistor or the second electrode of the first transistor through the second through hole; and the orthographic projection of the first end portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate.

[0009] Optionally, each of the multiple voltage supply lines includes a first parallel portion, a second parallel portion and an inclined portion, the inclined portion connecting the first parallel portion and the second parallel portion along an inclined direction; the first parallel portion and the second parallel portion respectively extend in directions substantially parallel to the second direction; the inclined portion extends along an inclination angle relative to the second direction; the handle and the base are arranged along a direction substantially parallel to the second direction; and the connecting portion extends along a direction substantially parallel to the inclined direction.

[0010] Optionally, the orthographic projection of the inclined portion on the base substrate substantially covers the orthographic projection of the connecting portion on the base substrate; the orthographic projection of the first parallel portion on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate; and the orthographic projection of the second parallel portion on the base substrate substantially covers the orthographic projection of the second end portion on the base substrate.

[0011] Optionally, the second electrode of the first transistor and the first electrode of the third transistor are parts of an integral structure in a corresponding one of a plurality of sub-pixels, the second electrode of the first transistor is directly connected to the first electrode of the third transistor; the node connection line is connected to the first electrode of the third transistor through the second through hole; and the orthographic projection of the second electrode of the first transistor on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate, at least partially overlaps with the orthographic projection of the first parallel portion on the base substrate, and at least partially overlaps with the orthographic projection of the base on the base substrate.

[0012] Optionally, an orthographic projection of the anti-interference block on the base substrate covers at least 30% of an orthographic projection of the second electrode of the first transistor on the base substrate.

[0013] Optionally, the orthographic projection of the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole on the base substrate is substantially surrounded by a combination of the orthographic projection of the anti-interference block on the base substrate and the orthographic projection of a corresponding one of the multiple gate lines on the base substrate.

[0014] Optionally, the array substrate also includes multiple first reset control signal lines; a portion of a corresponding one of the multiple first reset control signal lines is used as the gate of the first transistor; the second electrode of the first transistor and the first electrode of the third transistor are parts of the overall structure in a corresponding one of the multiple sub-pixels, and the second electrode of the first transistor is directly connected to the first electrode of the third transistor; the node connection line is connected to the first electrode of the third transistor through the second through hole; a portion of a corresponding one of the multiple gate lines is used as the gate of the third transistor; and a combination of the orthographic projection of the first adjacent data line on the base substrate, the orthographic projection of the second adjacent data line on the base substrate, the orthographic projection of the corresponding one of the multiple first reset control signal lines on the base substrate, and the orthographic projection of the corresponding one of the multiple gate lines on the base substrate surrounds the orthographic projection of the anti-interference block on the base substrate.

[0015] Optionally, the virtual line passes through the portion of the node connection line at the location connected to the semiconductor material layer through the second through hole and is substantially parallel to the first direction, and the virtual line also passes through the first end portion, the second end portion, the first adjacent data line and the second adjacent data line.

[0016] Optionally, a first shortest distance along the virtual line between the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole and a first center line of the first adjacent data line along the second direction is in the range of 10.0 μm to 20.0 μm.

[0017] Optionally, a second shortest distance along the virtual line between the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole and an edge of the second parallel portion on a side close to the second adjacent data line is in the range of 8.0 μm to 18.0 μm.

[0018] Optionally, a third shortest distance between a second center line of the second adjacent data line along the second direction and a third center line of the handle along the second direction is in a range of 11.0 μm to 22.0 μm.

[0019] Optionally, a ratio among the first shortest distance, the second shortest distance and the third shortest distance is in the range of (14.5 to 16.5):(13.5 to 14.5):(16.0 to 18.0).

[0020] Optionally, the second adjacent data line is configured to provide a data signal to a corresponding sub-pixel; and the first adjacent data line is configured to provide a data signal to an adjacent sub-pixel directly adjacent to the corresponding sub-pixel.

[0021] In another aspect, the present disclosure provides a display device including an array substrate described herein or manufactured by the method described herein, and an integrated circuit connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0023] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0024] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0025] Figure 2B A mechanism for preventing crosstalk in an array substrate according to some embodiments of the present disclosure is shown.

[0026] Figure 2C is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 3A is a diagram showing the structure of multiple sub-pixels of an array substrate in some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A A diagram showing the structure of semiconductor material layers in multiple sub-pixels of an array substrate.

[0029] Figure 3C It is shown Figure 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of an array substrate.

[0030] Figure 3D It is shown Figure 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of an array substrate.

[0031] Figure 3E It is shown Figure 3A A diagram showing the structure of a signal line layer in multiple sub-pixels of an array substrate.

[0032] Figure 3F is a diagram showing the structure of a plurality of voltage supply lines in an array substrate according to some embodiments of the present disclosure.

[0033] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0034] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0035] Figure 4C is along Figure 3A Cross-sectional view along line C-C'.

[0036] Figure 4D is along Figure 3A Cross-sectional view along line D-D'.

[0037] Figure 5A yes Figure 3A A partial view of a sub-pixel of an array substrate is shown.

[0038] Figure 5B Shows Figure 5A Some selected parts of

[0039] Figure 5C The structure of the anti-interference block in some embodiments according to the present disclosure is shown.

[0040] Figure 5D is an enlarged view of a region of an array substrate having a first transistor and a third transistor according to some embodiments of the present disclosure.

[0041] Figure 5E is another enlarged view of a region of an array substrate having a third transistor in some embodiments according to the present disclosure.

[0042] Fig. 5F The detailed structure of the anti-interference block in some embodiments of the present disclosure is shown.

[0043] Figure 5G A partial structure of a corresponding one of a plurality of voltage supply lines according to some embodiments of the present disclosure is shown.

[0044] Figure 5H The structural relationship between the anti-interference block and surrounding components in some embodiments according to the present disclosure is shown.

[0045] Fig.5I is along Figure 5A Cross-sectional view along line E-E'. DETAILED DESCRIPTION

[0046] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0047] The present disclosure particularly provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes: a plurality of gate lines, which extend in a first direction respectively; a plurality of data lines, which extend in a second direction respectively; a plurality of voltage supply lines, which extend in the second direction respectively; and a pixel driving circuit. Optionally, the pixel driving circuit includes a driving transistor; a first transistor; a second transistor; a third transistor and a storage capacitor. Optionally, the storage capacitor includes a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, the array substrate includes: a semiconductor material layer on a base substrate; a node connection line, which is in the same layer as a corresponding one of the plurality of voltage supply lines, the node connection line is connected to the first capacitor electrode through a first through hole, and is connected to the semiconductor material layer through a second through hole; and an anti-interference block, which is in the same layer as the second capacitor electrode, the corresponding one of the plurality of voltage supply lines is connected to the anti-interference block through a third through hole, the anti-interference block including a first arm and a second arm. Optionally, along the first direction, a portion of the node connection line at a position connected to the semiconductor material layer through the second through hole is spaced apart from a first adjacent data line through the first arm, and is spaced apart from a second adjacent data line through the second arm.

[0048] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of voltage supply lines Vdd (e.g., a high voltage supply line) and a plurality of second voltage supply lines (e.g., a low voltage supply line Vss). The light emission of each sub-pixel in the sub-pixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through a corresponding one of the plurality of voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through a corresponding one of the plurality of second voltage supply lines (e.g., a low voltage supply line Vss). The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0049] Various suitable pixel driving circuits can be used in the present array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the present array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0050] Figure 2A2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Referring to FIG. 2 , in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding one of a plurality of first reset control signal lines rst1, a first electrode connected to a corresponding one of a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a gate line GL, a first electrode connected to a data line DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to the gate line GL, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the gate of the third transistor T4. The electrode is connected to the second electrode of the driving transistor Td; the fourth transistor T4, whose gate is connected to a corresponding one of the plurality of light emitting control signal lines em, the first electrode is connected to the voltage supply line Vdd, and the second electrode is connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; the fifth transistor T5, which has a gate connected to a corresponding one of the plurality of light emitting control signal lines em, a first electrode connected to the second electrode of the driving transistor Td and the second electrode of the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and the sixth transistor T6, which has a gate connected to a corresponding one of the plurality of second reset control signal lines rst2, a first electrode connected to a corresponding one of the plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the voltage supply line Vdd and the first electrode of the fourth transistor T4. As used herein, the term "first electrode" refers to one of the source and drain of a transistor, and the term "second electrode" refers to one of the source and drain of a transistor. In one example, the first electrode is a source and the second electrode is a drain. In another example, the first electrode is a drain and the second electrode is a source.

[0051] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2 and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3 and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0052] Figure 2B The mechanism for preventing crosstalk in the array substrate according to some embodiments of the present disclosure is shown. Figure 2B The inventors of the present disclosure have found that the existence of crosstalk between the N1 node and the adjacent data lines affects the display quality. Figure 2B The inventors of the present disclosure have found that, unexpectedly and surprisingly, the anti-interference block (to be described in detail in the present disclosure) can effectively reduce crosstalk, especially vertical crosstalk between the N1 node and the adjacent data line.

[0053] Figure 3A is a diagram showing the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 3A In some embodiments, the array substrate includes a plurality of sub-pixels (e.g., red sub-pixels, green sub-pixels, and blue sub-pixels). In some embodiments, the array substrate includes a plurality of gate lines GL extending along the first direction DR1, a plurality of data lines DL extending along the second direction DR2, and a plurality of voltage supply lines Vdd extending along the second direction DR2. Optionally, the array substrate further includes a plurality of first reset control signal lines rst1 extending along the first direction DR1, a plurality of second reset control signal lines rst2 extending along the first direction DR1, a plurality of first reset signal lines Vint1 extending along the first direction DR1, a plurality of second reset signal lines Vint2 extending along the first direction DR1, and a plurality of light emitting control signal lines em extending along the first direction DR1. Figure 3A The corresponding positions of multiple transistors in the pixel driving circuit are depicted in FIG. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td.

[0054] Figure 3B It is shown Figure 3A A diagram showing the structure of semiconductor material layers in multiple sub-pixels of an array substrate. Figure 3C It is shown Figure 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of an array substrate. Figure 3D It is shown Figure 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of an array substrate. Figure 3E It is shown Figure 3A A diagram showing the structure of a signal line layer in multiple sub-pixels of an array substrate. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. Figure 4B is along Figure 3A Cross-sectional view of line BB' in FIG. FIG. 3A to FIG. 3E as well as FIG. 4A to FIG. 4B In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on a side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on a side of the second conductive layer away from the insulating layer IN, a first signal line layer located on a side of the interlayer dielectric layer ILD away from the second conductive layer, and a first planarization layer PLN1 located on a side of the signal line layer away from the interlayer dielectric layer ILD.

[0055] Reference Figure 2A , Figure 3A and Figure 3B In some embodiments, in each sub-pixel, the semiconductor material layer has an integral structure. Figure 3B In the figure, the first sub-pixel on the left is marked with a mark indicating the area corresponding to multiple transistors in the pixel driving circuit, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td. Figure 3B, the sub-pixels on the right are marked with marks indicating the elements of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of an integral structure in each sub-pixel. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are in the same layer.

[0056] Reference Figure 2A , Figure 3A , Figure 3C , Figure 4A as well as Figure 4B In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of first reset control signal lines rst1, a plurality of light emitting control signal lines em, a plurality of second reset control signal lines rst2, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of gate lines GL, the plurality of first reset control signal lines rst1, the plurality of light emitting control signal lines em, the plurality of second reset control signal lines rst2, and the first capacitor electrode Ce1 are located in the same layer. Optionally, the first conductive layer has a thickness in the range of 200nm to 300nm, for example, 250nm.

[0057] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the plurality of gate lines GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the plurality of gate lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming the plurality of gate lines GL and the steps of forming the first capacitor electrode Ce1, the plurality of gate lines GL and the first capacitor electrode Ce1 may be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0058] Reference Figure 2A , Figure 3A and Figure 3D In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vint1, a second capacitor electrode Ce2 of a storage capacitor Cst, an anti-interference block IPB, and a plurality of second reset signal lines Vint2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, an anti-interference block IPB, and a second capacitor electrode Ce2 are located in the same layer. Optionally, the second conductive layer has a thickness in the range of 200nm to 300nm, for example, 250nm.

[0059] Reference Figure 2A , Figure 3A , Figure 3B and Figure 3EIn some embodiments, the signal line layer includes a plurality of voltage supply lines Vdd, a plurality of data lines DL, a node connection line Cln, a second connection line Cl2, and a third connection line Cl3. The node connection line Cln connects the first capacitor electrode Ce1 and the first electrode of the third transistor T3 in the corresponding sub-pixel together. The second connection line Cl2 connects a corresponding one of the plurality of second reset signal lines Vint2 and the first electrode of the sixth transistor T6 in the corresponding sub-pixel together. The third connection line Cl3 connects a corresponding one of the plurality of first reset signal lines Vint1 and the first electrode of the first transistor T1 in the corresponding sub-pixel together. In some embodiments, the first signal line layer also includes a relay electrode RE in a corresponding one of the plurality of sub-pixels sp. The relay electrode connects the first electrode of the fifth transistor T5 in the corresponding one of the plurality of sub-pixels sp to the anode contact pad in the corresponding one of the plurality of sub-pixels sp. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of voltage supply lines Vdd, a plurality of data lines DL, node connection lines Cln, second connection lines Cl2, and third connection lines Cl3 are in the same layer. Optionally, the signal line layer has a thickness in the range of 600nm to 700nm, for example, 650nm.

[0060] In the context of the present disclosure, for example, Figure 3A In FIG. 1 , the area enclosed by a dotted line and indicated as “sp” indicates an approximate area corresponding to each sub-pixel in the array substrate. The area enclosed by a dotted line and indicated as “sp” does not necessarily indicate a repeated unit of a plurality of pixel driving circuits.

[0061] Figure 3F 1 is a diagram showing the structure of multiple voltage supply lines in an array substrate according to some embodiments of the present disclosure. In some embodiments, the array substrate includes a display area DA and a peripheral area PA. Multiple voltage supply lines Vdd are at least partially in the display area DA. Multiple voltage supply lines Vdd are connected to a connecting bar CB in the peripheral area PA. The connecting bar CB is in turn connected to a circuit connection part ICP, which is then connected to, for example, an integrated circuit.

[0062] Figure 4C is along Figure 3A Cross-sectional view of line C-C' in FIG. Figure 2A , Figure 3A , Figure 3E and Figure 4CIn some embodiments, the second connection line Cl2 connects a corresponding one of the plurality of second reset signal lines Vint2 to the first electrode S6 of the sixth transistor T6 in the corresponding sub-pixel. A corresponding one of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the first electrode S6 of the sixth transistor T6 in the corresponding sub-pixel through the second connection line Cl2. Optionally, the second connection line Cl2 is connected to a corresponding one of the plurality of second reset signal lines Vint2 through a fifth through hole v5 extending through the interlayer dielectric layer ILD. Optionally, the second connection line Cl2 is connected to the first electrode S6 of the sixth transistor T6 in the corresponding sub-pixel through a sixth through hole v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0063] Figure 4D is along Figure 3A The cross-sectional view of the line D-D' in FIG. Figure 2A , Figure 3A , Figure 3E and Figure 4D In some embodiments, the third connection line Cl3 connects a corresponding one of the plurality of first reset signal lines Vint1 to the first electrode S1 of the first transistor T1 in the corresponding sub-pixel. The corresponding one of the plurality of first reset signal lines Vint1 is configured to provide a reset signal to the first electrode S1 of the first transistor T1 in the corresponding sub-pixel through the third connection line Cl3. Optionally, the third connection line Cl3 is connected to the corresponding one of the plurality of first reset signal lines Vint1 through a seventh through hole v7 extending through the interlayer dielectric layer ILD. Optionally, the third connection line Cl3 is connected to the first electrode S6 of the sixth transistor T6 in the corresponding sub-pixel through an eighth through hole v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0064] Reference Figure 2A , Figure 3A , Figure 3C , Figure 3D and Figure 4AIn some embodiments, except for the hole area H, the orthographic projection of the second capacitor electrode Ce2 on the base substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS and leaves a margin, and a part of the second capacitor electrode Ce2 does not exist in the hole area H. In some embodiments, the signal line layer includes a node connection line Cln, which is located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is in the same layer as the plurality of voltage supply lines Vdd and the plurality of data lines DL. Optionally, the array substrate also includes a first through hole v1 in the hole area H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first through hole v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate also includes a first through hole v1 and a second through hole v2. The first through hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second through hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first through hole v1, and is connected to the semiconductor material layer SML through the second through hole v2. Optionally, the node connection line Cln is connected to the first electrode S3 of the third transistor, as shown in FIG. Figure 4A shown.

[0065] refer to Figure 2A , Figure 3A , Figure 3D and Figure 4B In some embodiments, the anti-interference block IPB is in the same layer as the second capacitor electrode Ce2. A corresponding one of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB through a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD.

[0066] refer to Figure 2A , Figure 3A , Figure 3D and Figure 4B In some embodiments, the plurality of data lines DL and the plurality of voltage supply lines Vdd are in the same layer. A corresponding one of the plurality of data lines DL is connected to the source S2 of the second transistor through a fourth via v4. Optionally, the fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0067] Figure 5A yes Figure 3A A partial view of a sub-pixel of an array substrate is shown. Figure 5B Shows Figure 5A Some selected parts of Figure 5CThe structure of the anti-interference block in some embodiments of the present disclosure is shown. Figure 3A , Figure 5A , Figure 5B and Figure 5C In some embodiments, the anti-interference block IPB includes a first arm AM1 and a second arm AM2. Figure 4A and Figure 5B As shown, a portion of the node connection line Cln at a position connected to the semiconductor material layer SML through the second via v2 may be represented as an N1 node. Figure 3A , Figure 5A and Figure 5B , along the first direction DR1, a portion of the node connection line Cln at a position connected to the semiconductor material layer SML through the second through hole v2 (e.g., the N1 node) is separated from the first adjacent data line ADL1 by the first arm AM1, and is separated from the second adjacent data line ADL2 by the second arm AM2.

[0068] The inventors of the present disclosure found that, unexpectedly and surprisingly, the crosstalk between the N1 node and the adjacent data line can be significantly reduced by setting the anti-interference block IPB as described in the present disclosure. Table 1 below shows the unexpected and surprising reduction of crosstalk in the array substrate according to the present disclosure compared to the control array substrate.

[0069] Table 1. Reduction of crosstalk between N1 node and adjacent data lines in array substrate.

[0070]

[0071] In Table 1, "N1 node ~ DL" represents the parasitic capacitance between the N1 node and the adjacent data line; "Cst" represents the storage capacitor; "Vdd ~ DL" represents the parasitic capacitance between the corresponding one of the multiple voltage supply lines Vdd and the adjacent data line; "DL ~ N2 node" represents the parasitic capacitance between the N2 node and the adjacent data line. The crosstalk data is measured under the condition of a black data voltage of 6.5V provided to the multiple data lines. As shown in Table 1, although Vdd ~ DL increases with the anti-interference block IPB, the crosstalk (especially the vertical crosstalk) can be significantly reduced, thereby greatly improving the display quality of the display panel having the present array substrate. Optionally, compared with the control array substrate, the vertical crosstalk is reduced by at least 50%, for example, at least 52%, at least 54%, at least 56%, at least 58% or at least 60%. Optionally, the parasitic capacitance between the N1 node and the adjacent data line is reduced by at least 50%, for example, at least 52%, at least 54%, at least 56%, at least 58% or at least 60%. The slightly increased Vdd~DL can be easily compensated by a compensation integrated circuit.

[0072] Reference Figure 3A and Figure 3B In some embodiments, the first electrode S2 of the third transistor T3 and the active layer ACT3 are part of an integral structure in a corresponding one of the plurality of sub-pixels. Figure 3A and Figure 4A In some embodiments, the node connection line Cln is connected to the first electrode S3 of the third transistor T3 through the second through hole v2. Figure 3A , Figure 3B , Figure 4A and FIG. 5A to FIG. 5C In some embodiments, an orthographic projection of the first arm AM1 on the base substrate BS at least partially overlaps with an orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS.

[0073] As used herein, the active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of at least a portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the gate on the base substrate. As used herein, the first electrode refers to a component of a transistor connected to one side of the active layer, and the second electrode refers to a component of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), the active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, the orthographic projection of the first portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the first gate on the base substrate, and the orthographic projection of the second portion of the semiconductor material layer on the base substrate overlaps with the orthographic projection of the second gate on the base substrate. In the case of a dual-gate transistor, the first electrode refers to a piece of the transistor connected to the first portion away from the third portion, and the second electrode refers to a component of the transistor connected to the second portion away from the third portion.

[0074] Figure 2C is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2C , Figure 3A , Figure 3B and Figure 3C In some embodiments, the third transistor T3 is a “dual gate” transistor and the first transistor T1 is a “dual gate” transistor. Figure 5D is an enlarged view of a region of an array substrate having a first transistor and a third transistor according to some embodiments of the present disclosure. Figure 5DIn some embodiments, the active layer ACT1 of the first transistor T1 passes through a corresponding one of the plurality of first reset control signal lines rst1 twice (alternatively, a corresponding one of the plurality of first reset control signal lines rst1 passes through the active layer ACT1 of the first transistor T1 twice). Similarly, in some embodiments, the active layer ACT3 of the third transistor T3 passes through a corresponding one of the plurality of gate lines GL twice (alternatively, a corresponding one of the plurality of gate lines GL passes through the active layer ACT3 of the third transistor T3 twice). Figure 5E is another enlarged view of a region of an array substrate having a third transistor in some embodiments according to the present disclosure. Figure 5E In some embodiments, a corresponding one of the plurality of gate lines GL includes a main body MB extending along the first direction DR1 and a protrusion GP protruding from the main body MB along the second direction DR2. Figure 5E As shown, the active layer ACT3 of the third transistor T3 passes through the body MB once and passes through the protrusion GP once. The active layer ACT3 of the third transistor T3 includes a first portion passing through the protrusion GP, ​​a second portion passing through the body MB, and a third portion connecting the first portion and the second portion, and the third portion does not pass through any portion of a corresponding one of the plurality of gate lines GL. Figure 5E As shown, the orthographic projection of the first arm AM1 on the base substrate at least partially overlaps with the orthographic projection of the third portion of the active layer ACT3 of the third transistor T3 on the base substrate. Optionally, the third portion has an L-like shape.

[0075] refer to Figure 3A , Figure 3B , Figure 4A and FIG. 5A to FIG. 5C In some embodiments, the orthographic projection of the second arm AM2 on the base substrate BS at least partially overlaps with the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd on the base substrate BS. Optionally, the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd on the base substrate BS substantially covers the orthographic projection of the second arm AM2 on the base substrate BS. As used herein, the term "substantially covers" means that one orthographic projection is covered by another orthographic projection by at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%.

[0076] Fig. 5F Detailed structure of the anti-interference block in some embodiments of the present disclosure is shown. Figure 3A , Figure 4B , FIG. 5A to FIG. 5EIn some embodiments, the anti-interference block IPB further comprises a handle H. A corresponding one of the plurality of voltage supply lines Vdd is connected to the handle H through a third through hole v3. Optionally, the first arm AM1 comprises an L-shaped portion LP and a first end portion TP1. Optionally, the second arm AM2 comprises a base BP, a second end portion TP2, and a connection portion CP connecting the base BP and the second end portion TP2. Optionally, the base BP connects the L-shaped portion LP and the handle H.

[0077] Optionally, the handle H has a substantially rectangular shape. Optionally, the base BP has a substantially rectangular shape. Optionally, the L-shaped portion has an L-like shape. Optionally, the first terminal portion TP1 has a rectangular-like shape.

[0078] Optionally, the orthographic projection of the first end portion TP1 on the base substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS, while the orthographic projection of the L-shaped portion LP does not overlap with the orthographic projection of the active layer ACT3 of the third transistor T3 on the base substrate BS.

[0079] Figure 5G FIG. 2 shows a partial structure of a corresponding one of a plurality of voltage supply lines according to some embodiments of the present disclosure. Figure 5G In some embodiments, a corresponding one of the plurality of voltage supply lines Vdd includes a first parallel portion PA1, a second parallel portion PA2, and an inclined portion INP, wherein the inclined portion INP connects the first parallel portion PA1 and the second parallel portion PA2 along an inclined direction IDR. The first parallel portion PA1 and the second parallel portion PA2 extend along directions substantially parallel to the second direction DR2, respectively. The inclined portion INP extends along an inclination angle α relative to the second direction DR2. The connecting portion INP extends along a direction substantially parallel to the inclined direction IDR. Fig. 5F In some embodiments, the handle H and the base BP are arranged along a direction substantially parallel to the second direction DR2. As used herein, the term "substantially parallel" means that the angle is in the range of 0 to about 45 degrees, such as 0 to about 5 degrees, 0 to about 10 degrees, 0 to about 15 degrees, 0 to about 20 degrees, 0 to about 25 degrees, 0 to about 30 degrees.

[0080] Optionally, each of the first parallel portion PA1, the second parallel portion PA2 and the inclined portion INP is substantially straight. As used herein, the term "substantially straight" means straight, or with minimal deviation from straight, such as within 1%, within 2%, within 5%, within 7%, within 10%, within 12%, or within 15%.

[0081] Reference FIG. 5A to FIG. 5GIn some embodiments, the orthographic projection of the inclined portion INP on the base substrate BS substantially covers the orthographic projection of the connecting portion CP on the base substrate BS. Optionally, the orthographic projection of the first parallel portion PA1 on the base substrate BS at least partially overlaps with the orthographic projection of the handle H on the base substrate BS. Optionally, the orthographic projection of the second parallel portion PA2 on the base substrate BS substantially covers the orthographic projection of the second terminal portion TP2 on the base substrate BS.

[0082] Reference Figure 2A , Figure 3A and Figure 3B In some embodiments, the second electrode D1 of the first transistor T1 and the first electrode S3 of the third transistor T3 are part of the integral structure of a corresponding sub-pixel sp in the plurality of sub-pixels sp. The second electrode D1 of the first transistor T1 is directly connected to the first electrode S3 of the third transistor T3. Figure 4A In some embodiments, the node connection line Cln is connected to the first electrode S3 of the third transistor T3 through the second through hole v2. Figure 3A , Figure 4A , FIG. 5A to FIG. 5G In some embodiments, the orthographic projection of the second electrode D1 of the first transistor T1 on the base substrate BS at least partially overlaps with the orthographic projection of the handle H on the base substrate BS, at least partially overlaps with the orthographic projection of the first parallel portion PA1 on the base substrate BS, and at least partially overlaps with the orthographic projection of the base BP on the base substrate BS.

[0083] refer to Figure 5D In some embodiments, the orthographic projection of the anti-interference block IPB on the base substrate BS covers at least 30% (for example, at least 35%, 45%, 50%, 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85% or at least 90%) of the orthographic projection of the second electrode D1 of the first transistor T1 on the base substrate BS.

[0084] Reference Figure 3A , Figure 4A , FIG. 5A to FIG. 5G In some embodiments, the portion of the node connection line Cln at the position connected to the semiconductor material layer SML through the second via v2 (eg Figure 5BThe orthographic projection of the anti-interference block IPB on the base substrate BS is substantially surrounded by a combination of an orthographic projection of the anti-interference block IPB on the base substrate BS and an orthographic projection of a corresponding one of the plurality of gate lines GL on the base substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the base substrate BS is surrounded by a combination of an orthographic projection of the first adjacent data line ADL1 on the base substrate BS, an orthographic projection of the second adjacent data line ADL2 on the base substrate BS, an orthographic projection of a corresponding one of the plurality of first reset control signal lines rst1 on the base substrate BS, and an orthographic projection of a corresponding one of the plurality of gate lines GL on the base substrate BS. As used herein, the term "substantially surrounding" means that at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, and 100%) of the periphery of the area is surrounded.

[0085] refer to Figure 5B , the virtual line VL passes through a portion of the node connection line Cln at a position connected to the semiconductor material layer through the second through hole (eg Figure 5B The N1 node shown in the figure is substantially parallel to the first direction DR1 and also passes through the anti-interference block IPB, the first adjacent data line ADL1 and the second adjacent data line ADL2. Figures 5B to 5G In some embodiments, the virtual line VL passes through the active layer ACT3 of the third transistor T3, the anti-interference block IPB, the first adjacent data line ADL1, and the second adjacent data line ADL2. Optionally, the virtual line VL passes through the first end portion TP1, the second end portion TP2, the first adjacent data line ADL1, and the second adjacent data line ADL2.

[0086] Figure 5H The structural relationship between the anti-interference block and surrounding components in some embodiments according to the present disclosure is shown. Figure 5H A portion of the node connection line Cln along the virtual line VL at a location connected to the semiconductor material layer through the second through hole (eg Figure 5B A first shortest distance d1 is defined between the node N1 shown in FIG. 4 and a first center line ml1 of the first adjacent data line ADL1 along the second direction DR2. Figure 5H Also shown is a portion of the node connection line Cln along the virtual line VL at a location where it is connected to the semiconductor material layer through the second through hole (eg Figure 5B A second shortest distance d2 is defined between the node N1 shown in FIG. 1 and an edge of the second parallel portion PA2 on a side close to the second adjacent data line ADL2. Figure 5H A third shortest distance d3 between a second center line ml2 of the second adjacent data line ADL2 in the second direction DR2 and a third center line ml3 of the handle H in the second direction DR2 is also shown.

[0087] Optionally, the first shortest distance d1 is in the range of 10.0 μm to 20.0 μm, for example, 10.0 μm to 12.5 μm, 12.5 μm to 15.0 μm, 15.0 μm to 17.5 μm, or 17.5 μm to 20.0 μm. Optionally, the first shortest distance d1 is in the range of 14.5 μm to 16.5 μm, for example, 14.5 μm to 15.0 μm, 15.0 μm to 15.5 μm, 15.5 μm to 16.0 μm, or 16.0 μm to 16.5 μm. Optionally, the second shortest distance d2 is in the range of 8.0 μm to 18.0 μm, for example, 8.0 μm to 10.5 μm, 10.5 μm to 13.0 μm, 13.0 μm to 15.5 μm, or 15.5 μm to 18.0 μm. Optionally, the second shortest distance d2 is in the range of 12.5 μm to 14.5 μm, for example, 12.5 μm to 13.0 μm, 13.0 μm to 13.5 μm, 13.5 μm to 14.0 μm, or 14.0 μm to 14.5 μm. Optionally, the third shortest distance d3 is in the range of 11.0 μm to 22.0 μm, for example, 11.0 μm to 14.0 μm, 14.0 μm to 17.0 μm, 17.0 μm to 20.0 μm, or 20.0 μm to 22.0 μm. Optionally, the third shortest distance d3 is in the range of 16.0 μm to 18.0 μm, for example, 16.0 μm to 16.5 μm, 16.5 μm to 17.0 μm, 17.0 μm to 17.5 μm, or 17.5 μm to 18.0 μm. Optionally, the first shortest distance d1 is 15.53 μm, the second shortest distance d2 is 13.65 μm, and the third shortest distance d3 is 16.87 μm.

[0088] Optionally, a ratio between the first shortest distance, the second shortest distance and the third shortest distance is in the range of (14.5 to 16.5):(13.5 to 14.5):(16.0 to 18.0).

[0089] Fig.5I is along Figure 5A The cross-sectional view of the line E-E' in FIG. Fig.5I , along the first direction, a portion of the node connection line Cln at a position connected to the semiconductor material layer SML through the second through hole v2 is spaced apart from the first adjacent data line ADL1 by the first arm AM1, and is spaced apart from the second adjacent data line ADL2 by the second arm AM2.

[0090] In another aspect, the present disclosure provides a display panel, comprising an array substrate described herein or manufactured by a method described herein and an opposing substrate facing the array substrate. Optionally, the display panel is an organic light emitting diode display panel. Optionally, the display panel is a micro light emitting diode display panel.

[0091] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the method as described herein, and one or more integrated circuits connected to the array substrate.

[0092] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of gate lines, which extend in a first direction respectively; forming a plurality of data lines, which extend in a second direction respectively; forming a plurality of voltage supply lines, which extend in the second direction respectively; and forming a pixel driving circuit. Optionally, forming the pixel driving circuit includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor and forming a storage capacitor. Optionally, forming a storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and forming an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, the method includes: forming a semiconductor material layer on a base substrate; forming a node connection line, which is in the same layer as a corresponding one of the plurality of voltage supply lines, the node connection line is connected to the first capacitor electrode through a first through hole, and is connected to the semiconductor material layer through a second through hole; and forming an anti-interference block, which is in the same layer as the second capacitor electrode, and a corresponding one of the plurality of voltage supply lines is connected to the anti-interference block through a third through hole, and the anti-interference block includes a first arm and a second arm. Optionally, along the first direction, a portion of the node connection line at a position connected to the semiconductor material layer through the second through hole is spaced apart from a first adjacent data line by the first arm, and spaced apart from a second adjacent data line by the second arm.

[0093] In some embodiments, the first electrode and the active layer of the third transistor are formed as part of an integral structure in a corresponding one of the plurality of sub-pixels. Optionally, the node connection line is formed to be connected to the first electrode of the third transistor through the second through hole. Optionally, the orthographic projection of the first arm on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate. Optionally, the orthographic projection of the second arm on the base substrate at least partially overlaps with the orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate. Optionally, the orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate substantially covers the orthographic projection of the second arm on the base substrate.

[0094] In some embodiments, forming the anti-interference block further comprises forming a handle. Optionally, a corresponding one of the plurality of voltage supply lines is formed to be connected to the handle through the third through hole. Optionally, forming the first arm comprises forming an L-shaped portion and forming a first end portion. Optionally, forming the second arm comprises forming a base, forming a second end portion, and forming a connecting portion connecting the base and the second end portion. Optionally, the base is formed to connect the L-shaped portion and the handle.

[0095] In some embodiments, the first electrode and the active layer of the third transistor are formed as part of an integral structure in a corresponding one of the plurality of sub-pixels. Optionally, the node connection line is formed to be connected to the first electrode of the third transistor through the second through hole. Optionally, the orthographic projection of the first end portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the base substrate.

[0096] In some embodiments, each of the plurality of voltage supply lines is formed to include a first parallel portion, a second parallel portion, and an inclined portion, the inclined portion connecting the first parallel portion and the second parallel portion along an inclined direction. Optionally, the first parallel portion and the second parallel portion are formed to extend in directions substantially parallel to the second direction, respectively. Optionally, the inclined portion is formed to extend along an inclined angle relative to the second direction. Optionally, the handle and the base are formed to be arranged in a direction substantially parallel to the second direction. Optionally, the connecting portion is formed to extend in a direction substantially parallel to the inclined direction.

[0097] In some embodiments, the orthographic projection of the inclined portion on the base substrate substantially covers the orthographic projection of the connecting portion on the base substrate. Optionally, the orthographic projection of the first parallel portion on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate. Optionally, the orthographic projection of the second parallel portion on the base substrate substantially covers the orthographic projection of the second end portion on the base substrate.

[0098] In some embodiments, the second electrode of the first transistor and the first electrode of the third transistor are formed as part of an integral structure in a corresponding one of a plurality of sub-pixels, and the second electrode of the first transistor is directly connected to the first electrode of the third transistor. Optionally, the node connection line is formed to be connected to the first electrode of the third transistor through the second through hole. Optionally, the orthographic projection of the second electrode of the first transistor on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate, at least partially overlaps with the orthographic projection of the first parallel portion on the base substrate, and at least partially overlaps with the orthographic projection of the base on the base substrate. Optionally, the orthographic projection of the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole on the base substrate is substantially surrounded by a combination of the orthographic projection of the anti-interference block on the base substrate and the orthographic projection of a corresponding one of the plurality of gate lines on the base substrate.

[0099] In some embodiments, the method further includes forming a plurality of first reset control signal lines. Optionally, a portion of a corresponding one of the plurality of first reset control signal lines is used as the gate of the first transistor. Optionally, the second electrode of the first transistor and the first electrode of the third transistor are formed as part of an integral structure in a corresponding one of a plurality of sub-pixels, and the second electrode of the first transistor is directly connected to the first electrode of the third transistor. Optionally, the node connection line is formed to be connected to the first electrode of the third transistor through the second through hole. Optionally, a portion of a corresponding one of the plurality of gate lines is used as the gate of the third transistor. Optionally, the positive projection of the first adjacent data line on the base substrate, the positive projection of the second adjacent data line on the base substrate, the positive projection of the corresponding one of the plurality of first reset control signal lines on the base substrate, and the positive projection of the corresponding one of the plurality of gate lines on the base substrate surround the positive projection of the anti-interference block on the base substrate.

[0100] In some embodiments, the virtual line passes through the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole, and is substantially parallel to the first direction, and the virtual line also passes through the anti-interference block, the first adjacent data line, and the second adjacent data line. Optionally, the virtual line passes through the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole, and is substantially parallel to the first direction, and the virtual line also passes through the active layer of the third transistor, the anti-interference block, the first adjacent data line, and the second adjacent data line. Optionally, the virtual line passes through the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole, and is substantially parallel to the first direction, and the virtual line also passes through the first end portion, the second end portion, the first adjacent data line, and the second adjacent data line.

[0101] In some embodiments, the first shortest distance along the virtual line between the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole and the first center line of the first adjacent data line along the second direction is in the range of 14.5 μm to 16.5 μm. Optionally, the second shortest distance along the virtual line between the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole and the edge of the second parallel portion on one side close to the second adjacent data line is in the range of 12.5 μm to 14.5 μm. Optionally, the third shortest distance between the second center line of the second adjacent data line along the second direction and the third center line of the handle along the second direction is in the range of 16.0 μm to 18.0 μm. Optionally, the ratio between the first shortest distance, the second shortest distance and the third shortest distance is in the range of (14.5 to 16.5): (13.5 to 14.5): (16.0 to 18.0).

[0102] In some embodiments, the method further includes forming a gate insulating layer on a side of the semiconductor material layer away from the base substrate, the first capacitor electrode is located on the side of the gate insulating layer away from the base substrate; and forming an interlayer dielectric layer on a side of the second capacitor electrode away from the insulating layer, the node connection line and the plurality of voltage supply lines are located on the side of the interlayer dielectric layer away from the second capacitor electrode. Optionally, the first through hole is formed in a hole region that does not include a portion of the second capacitor electrode, the first through hole extending through the interlayer dielectric layer and the insulating layer, wherein, except for the hole region, the orthographic projection of the second capacitor electrode on the base substrate completely covers the orthographic projection of the first capacitor electrode on the base substrate and leaves a margin. Optionally, the second through hole extends through the interlayer dielectric layer, the insulating layer and the gate insulating layer.

[0103] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture buffer layers and barrier layers (between the semiconductor material layer and the base substrate), for example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of materials suitable for manufacturing buffer layers and / or barrier layers include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. Optionally, the thickness of the buffer layer is in the range of 400nm to 800nm, for example, 600nm. Optionally, the thickness of the barrier layer is in the range of 80nm to 150nm, for example, 110nm.

[0104] Various suitable semiconductor materials and various suitable manufacturing methods can be used to manufacture the semiconductor material layer. For example, the semiconductor material can be deposited on the substrate by magnetron sputtering, vapor deposition (e.g., plasma enhanced chemical vapor deposition) or vacuum deposition. Examples of suitable metal oxide semiconductor materials include, but are not limited to, polycrystalline silicon, amorphous silicon and various metal oxides, such as indium gallium tin oxide, indium gallium zinc oxide, zinc oxide, gallium oxide, indium oxide. In one example, the semiconductor material layer includes polycrystalline silicon. Optionally, the thickness of the semiconductor material layer is in the range of about 45nm to about 55nm, for example 50nm.

[0105] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the gate insulating layer, the insulating layer, the interlayer dielectric layer or the planarization layer. For example, the insulating material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of materials suitable for manufacturing the gate insulating layer, the insulating layer, the interlayer dielectric layer or the planarization layer include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx) or a combination thereof. Optionally, the gate insulating layer has a thickness in the range of 100nm to 140nm, for example, 120nm. Optionally, the insulating layer has a thickness in the range of 100nm to 160nm, for example, 130nm. Optionally, the interlayer dielectric layer has a thickness in the range of 450nm to 550nm, for example, 500nm. Optionally, the planarization layer has a thickness in the range of 1200nm to 1800nm, for example, 1500nm.

[0106] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: A plurality of grid lines extending along a first direction respectively; A plurality of data lines extending along the second direction respectively; a plurality of voltage supply lines extending respectively along the second direction; as well as Pixel driving circuit; Wherein, the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a third transistor and a storage capacitor; and the storage capacitor comprising a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding one of the plurality of voltage supply lines, and an insulating layer between the first capacitor electrode and the second capacitor electrode; Wherein, the array substrate comprises: a layer of semiconductor material on a base substrate; a node connection line in the same layer as a corresponding one of the plurality of voltage supply lines, the node connection line being connected to the first capacitor electrode through a first via and to the semiconductor material layer through a second via; and an anti-interference block in the same layer as the second capacitor electrode, a corresponding one of the plurality of voltage supply lines being connected to the anti-interference block through a third through hole, the anti-interference block comprising a first arm and a second arm; Wherein, along the first direction, a portion of the node connection line at a position connected to the semiconductor material layer through the second through hole is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.

2. The array substrate according to claim 1, wherein: The first electrode of the third transistor and the second electrode of the first transistor are part of an integral structure in a corresponding one of a plurality of sub-pixels; The node connection line is connected to the first electrode of the third transistor through the second through hole; as well as An orthographic projection of the first arm on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate.

3. The array substrate according to claim 1, wherein: An orthographic projection of the second arm on the base substrate at least partially overlaps with an orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: An orthographic projection of a corresponding one of the plurality of voltage supply lines on the base substrate substantially covers at least 30% of an orthographic projection of the second arm on the base substrate.

5. The array substrate according to any one of claims 1 to 3, wherein: The anti-tamper block also includes a handle; a respective one of the plurality of voltage supply lines connected to the handle through the third through hole; The first arm includes an L-shaped portion and a first end portion; and The second arm includes a base portion, a second end portion, and a connecting portion connecting the base portion and the second end portion; Wherein, the base connects the L-shaped portion and the handle.

6. The array substrate according to claim 5, wherein: The first electrode and the active layer of the third transistor are part of an integral structure in a corresponding one of the plurality of sub-pixels; The node connection line is connected to the first electrode of the third transistor or the second electrode of the first transistor through the second through hole; as well as An orthographic projection of the first end portion on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor on the base substrate.

7. The array substrate according to claim 5, wherein: Each of the plurality of voltage supply lines comprises a first parallel portion, a second parallel portion, and an inclined portion, wherein the inclined portion connects the first parallel portion and the second parallel portion along an inclined direction; The first parallel portion and the second parallel portion extend in directions substantially parallel to the second direction respectively; the inclined portion extends along an inclined angle relative to the second direction; The handle and the base are arranged along a direction substantially parallel to the second direction; as well as The connecting portion extends in a direction substantially parallel to the inclined direction.

8. The array substrate according to claim 7, wherein: The orthographic projection of the inclined portion on the base substrate substantially covers the orthographic projection of the connecting portion on the base substrate; The orthographic projection of the first parallel portion on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate; as well as An orthographic projection of the second parallel portion on the base substrate substantially covers an orthographic projection of the second end portion on the base substrate.

9. The array substrate according to claim 7, wherein: The second electrode of the first transistor and the first electrode of the third transistor are part of an integral structure in a corresponding one of the plurality of sub-pixels, and the second electrode of the first transistor is directly connected to the first electrode of the third transistor; The node connection line is connected to the first electrode of the third transistor through the second through hole; as well as The orthographic projection of the second electrode of the first transistor on the base substrate at least partially overlaps with the orthographic projection of the handle on the base substrate, at least partially overlaps with the orthographic projection of the first parallel portion on the base substrate, and at least partially overlaps with the orthographic projection of the base on the base substrate.

10. The array substrate according to claim 9, wherein: An orthographic projection of the anti-interference block on the base substrate covers at least 30% of an orthographic projection of the second electrode of the first transistor on the base substrate.

11. The array substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the portion of the node connection line at the position connected to the semiconductor material layer through the second through hole on the base substrate is substantially surrounded by a combination of the orthographic projection of the anti-interference block on the base substrate and the orthographic projection of a corresponding one of the multiple gate lines on the base substrate.

12. The array substrate according to any one of claims 1 to 3, further comprising a plurality of first reset control signal lines; a portion of a corresponding one of the plurality of first reset control signal lines serving as a gate of the first transistor; The second electrode of the first transistor and the first electrode of the third transistor are part of an integral structure in a corresponding one of the plurality of sub-pixels, and the second electrode of the first transistor is directly connected to the first electrode of the third transistor; The node connection line is connected to the first electrode of the third transistor through the second through hole; a portion of a corresponding one of the plurality of gate lines serving as a gate of the third transistor; as well as A combination of the orthographic projection of the first adjacent data line on the base substrate, the orthographic projection of the second adjacent data line on the base substrate, the orthographic projection of a corresponding one of the plurality of first reset control signal lines on the base substrate, and the orthographic projection of a corresponding one of the plurality of gate lines on the base substrate surrounds the orthographic projection of the anti-interference block on the base substrate.

13. The array substrate according to claim 7, wherein: A virtual line passes through the portion of the node connection line at the location connected to the semiconductor material layer through the second through hole and is substantially parallel to the first direction, and the virtual line also passes through the first end portion, the second end portion, the first adjacent data line and the second adjacent data line.

14. The array substrate according to claim 13, wherein: A first shortest distance along the virtual line between the portion of the node connection line at a location connected to the semiconductor material layer through the second via and a first center line of the first adjacent data line along the second direction ranges from 10.0 μm to 20.0 μm.

15. The array substrate according to claim 14, wherein: A second shortest distance along the virtual line between the portion of the node connection line at the position connected to the semiconductor material layer through the second via and an edge of the second parallel portion on a side close to the second adjacent data line ranges from 8.0 μm to 18.0 μm.

16. The array substrate according to claim 15, wherein: A third shortest distance between a second center line of the second adjacent data line along the second direction and a third center line of the stem along the second direction is in a range of 11.0 μm to 22.0 μm.

17. The array substrate according to claim 16, wherein: A ratio among the first shortest distance, the second shortest distance, and the third shortest distance is in the range of (14.5 to 16.5):(13.5 to 14.5):(16.0 to 18.0).

18. The array substrate according to any one of claims 1 to 3, wherein: The second adjacent data line is configured to provide a data signal to a corresponding sub-pixel; and The first adjacent data line is configured to provide a data signal to an adjacent sub-pixel directly adjacent to the corresponding sub-pixel.

19. A display device comprising the array substrate according to any one of claims 1 to 18 and an integrated circuit connected to the array substrate.

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