Comparator circuit

Abstract

A comparator circuit includes an input stage having a set of differential current paths and a pair of differential input transistors (N1, N2; P7, P8) connected to a pair of input terminals (INN, INP). An output stage includes an output current path between first and second power supply terminals (VDD, VSS), an output transistor (P4) connected in the output current path and having a control terminal coupled to the set of differential current paths, and a comparator output (OUT) connected to the output current path. An auxiliary stage includes an auxiliary current path between the power supply terminals (VDD, VSS), an auxiliary current source, a first auxiliary transistor (P3) connected in the auxiliary current path and having a control terminal connected to a control terminal of the output transistor (P4), and a voltage follower having a second auxiliary transistor (P5) and a third auxiliary transistor (P6). The second auxiliary transistor (P5) controls the voltage follower and the third auxiliary transistor (P6) couples the control terminal of the output transistor (P4) to at least one of the set of differential current paths.

Description

Technical Field

[0001] This disclosure relates to comparator circuits, sensor front-ends having such comparator circuits, and ramp analog-to-digital converters. This disclosure also relates to electronic devices including such comparator circuits.

[0002] This application claims priority to European Patent Application 20174457.0, the disclosure of which is incorporated herein by reference. Background Technology

[0003] Comparator circuits are widely used in electronic applications. It is generally desirable for the comparator's output to follow changes in its input with almost no delay. However, in traditional comparator circuits, the speed of the comparator is traded against the energy consumption and / or space required for circuit implementation. Summary of the Invention

[0004] The goal is to provide an improved comparator concept that can quickly switch the comparator output with very low current consumption.

[0005] This objective is achieved through the subject matter of the independent claims. Embodiments and developments of the improved concept are defined in the dependent claims.

[0006] A comparator circuit based on the improved comparator concept may include an input stage having a set of differential current paths and a pair of differential input transistors coupled to these differential current paths. Furthermore, the comparator circuit has an output stage and an output transistor, the output stage having an output current path between power supply terminals, the output transistor being connected in the output current path and having a control terminal connected to the input stage.

[0007] The improved comparator concept is based on the idea of ​​providing an auxiliary stage that controls the potential at the control terminal of the output transistor, ensuring that the potential at the control terminal of the output transistor does not fully saturate even when the comparator is tilted, for example due to a large differential at the input. However, it allows for a rapid transition to another output state if the input conditions are reversed. This is achieved, for example, by a first auxiliary transistor in an auxiliary current path whose control terminal is connected to the control terminal of the output transistor. A voltage follower with a second and third auxiliary transistor having their control terminals connected together supports control by having the second auxiliary transistor connected in the auxiliary current path while the third auxiliary transistor connects the control terminal of the output transistor to at least one current path in this set of differential current paths.

[0008] The current obtained through the auxiliary current path and the third auxiliary transistor causes a controlled voltage drop at the control terminal of the output transistor, preventing full saturation, and allowing the output transistor, and thus the comparator output, to switch immediately once the sensed input crosses the comparator's threshold voltage. Therefore, the auxiliary stage regulates the comparator's internal node, which in conventional solutions needs to recover from saturation to a precise level close to the comparator's switching point.

[0009] For example, an embodiment of a comparator circuit according to the improved comparator concept includes an input stage comprising a set of differential current paths and a pair of differential input transistors coupled to the set of differential current paths, and having control terminals connected to a pair of input terminals of the comparator circuit. The output stage includes an output current path between a first power supply terminal and a second power supply terminal, an output transistor connected in the output current path and having a control terminal connected to one of the current paths in the set of differential current paths, and a comparator output connected to the output current path.

[0010] The auxiliary stage includes an auxiliary current path between a first power supply terminal and a second power supply terminal, an auxiliary current source connected in the auxiliary current path, a first auxiliary transistor connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor, and a voltage follower consisting of a second auxiliary transistor and a third auxiliary transistor having control terminals connected together. The second auxiliary transistor is connected in the auxiliary current path and controls the voltage follower. The third auxiliary transistor couples the control terminal of the output transistor to at least one current path in this set of differential current paths.

[0011] The auxiliary current source in the auxiliary stage forces a specific current to flow through the auxiliary current path, and thus through the first and second auxiliary transistors. Due to the voltage follower configuration between the second and third auxiliary transistors, a certain current is also implied through the third auxiliary transistor, i.e., from the control terminal of the output transistor, the first auxiliary transistor, to the input stage of the comparator. Since these currents are determined by the control voltages of the three auxiliary transistors, a certain potential at the control terminal of the first auxiliary transistor connected to the output transistor is regulated in this way.

[0012] Specifically, this adjustment brings the potential at the control terminals of the first auxiliary transistor and the output transistor closer to the switching point of the output transistor, while moving away from the saturation potential. Therefore, if the input conditions change towards equilibrium or transition, the output transistor can switch more quickly.

[0013] For example, the first, second, and third auxiliary transistors are designed to be sized such that, at the operating point of the auxiliary stage, the voltage difference between the source and control terminals of the first auxiliary transistor is greater than zero and lower than the threshold voltage difference of the output transistor. The threshold voltage difference can be defined as the threshold at which the comparator switches between two output states in its balanced state, i.e., when the voltage difference between the comparator's inputs is zero. Depending on the transistor type, the voltage difference between the source and control terminals of the first auxiliary transistor can be an absolute voltage difference.

[0014] This dimensional determination can be achieved in several ways. For example, the auxiliary transistors can be designed such that the current density of the first auxiliary transistor is lower than that of the output transistor. Furthermore, it is possible for the current density of the second auxiliary transistor to be lower than that of the third auxiliary transistor. Combinations of both are also possible.

[0015] In another type of sizing, the threshold voltage of the first auxiliary transistor is lower than the threshold voltage of the output transistor, and / or the threshold voltage of the second auxiliary transistor is lower than the threshold voltage of the third auxiliary transistor.

[0016] In these configurations, it can be assumed that the source terminals of the first auxiliary transistor and the output transistor are at the same or similar potentials, such as one of the power supply terminals. It should also be noted that the aforementioned regulation of the potential at the control terminal of the output transistor is also achieved by reusing the current provided and returned to the input stage from the differential current path. Furthermore, this regulation is only effective when the comparator is tilted and does not require the full performance of the differential input pair. This makes the improved comparator concept power-efficient. Once the two input voltages approach each other, i.e., when the comparator should switch, the regulation automatically shuts off due to the changes at the control terminals of the output transistor and the first auxiliary transistor caused by the input stage.

[0017] In some implementations of comparator circuits, the set of differential current paths in the input stage includes a current mirror with a pair of differential transistors. One of the current paths in this set, connected to the control terminal of the output transistor, is controlled by the current mirror. This means that, for example, the potential transferred from the input stage to the output transistor is not actively controlled in the corresponding circuit, but is controlled only by the current mirror, which is controlled from the other current path of the differential current path. This makes it easier to control the corresponding nodes.

[0018] In some implementations, the set of differential current paths in the input stage includes a pair of differential input transistors and a current mirror with a pair of differential transistors. The input stage includes an input current source that shares a common connection with the set of differential current paths in the input stage. A third auxiliary transistor is connected between the control terminal of the output transistor and the common connection with the input current source. Also in such a configuration, one current path of the set of differential current paths connected to the control terminal of the output transistor can be controlled by the current mirror. Specifically, feedback of the current from the control terminal of the output transistor to the common connection of the set of differential current paths via the third auxiliary transistor enables efficient reuse of the current supplied from the input stage (specifically the current mirror) to the output stage.

[0019] In another implementation, the input stage is implemented as a folded cascode amplifier. The pair of differential input transistors is coupled between a common current source and a set of different current paths. This set of differential current paths is coupled between the first and second power supply terminals and includes current mirrors with different transistor pairs. This configuration also allows for efficient reuse of the current supplied from the control terminals of the output transistors.

[0020] Various other modifications are possible for the implementation of the input stage. However, the auxiliary stage can still provide efficient regulation of the potential at the control terminals of the output transistors, while saving power through current reuse.

[0021] The comparator circuit described above may be particularly useful when it is necessary to compare a changing voltage with a fixed or changing reference voltage. Specifically, the comparator can be used to detect whether the sensed voltage exceeds the reference voltage with a fast response time.

[0022] For example, the comparator circuit according to one of the above embodiments can be used in the sensor front end of a photodiode, which includes an integrator for integrating the photocurrent from the photodiode. In this configuration, the comparator circuit has a first embodiment with a pair of input terminals connected to the output of the integrator, and a second embodiment with a pair of input terminals connected to a reference voltage source. Therefore, the crossover between the integrated photocurrent and the reference voltage can be detected in a fast manner.

[0023] In another implementation, a comparator circuit based on a modified comparator concept can be used in a ramp analog-to-digital converter (ADC). For example, the first terminal of the input pair is connected to the output of a ramp signal generator, the second terminal of the input pair is connected to a sample-and-hold element that samples the input signal provided at the input terminal, and the comparator output is coupled to a counter circuit to provide a digital output value corresponding to the input signal.

[0024] For example, various implementations of comparator circuits, sensor front-ends, and ramp ADCs can be used in a wide range of fixed or portable electronic devices. Examples of fixed electronic devices are medical imaging equipment, such as X-ray machines or computed tomography (CT) machines. Examples of portable electronic devices are smartphones, wearable devices such as smartwatches, or biosensors, portable sensor devices, etc., for example, for optical sensor applications. Therefore, the improved comparator concept also encompasses such electronic devices. Attached Figure Description

[0025] The improved comparator concept will now be described in more detail with the aid of the accompanying drawings. In all the drawings, elements with the same or similar functions have the same reference numerals. Therefore, it is unnecessary to repeat their description in the following drawings.

[0026] In the attached diagram:

[0027] Figure 1 An example implementation of the comparator circuit is shown;

[0028] Figure 2 Another example implementation of the comparator circuit is shown;

[0029] Figure 3 Another example implementation of the comparator circuit is shown;

[0030] Figure 4 An example implementation of a photodiode sensor front end is shown; and

[0031] Figure 5 An example implementation of a ramp analog-to-digital converter is shown. Detailed Implementation

[0032] Figure 1 A first example implementation of a comparator circuit based on the improved comparator concept is shown. In this example implementation, the comparator circuit consists of three stages: an input stage, an output stage, and an auxiliary stage. All stages are connected between a first power supply terminal VDD and a second power supply terminal VSS. For example, the first power supply terminal VDD provides a positive supply voltage, and the second power supply terminal VSS provides a negative supply voltage or ground potential.

[0033] The input stage includes a set of differential current paths and a pair of differential input transistors N1 and N2 coupled within these paths. Specifically, the controlled portion of each input transistor N1 and N2, for example, a source-drain connection, is connected in each differential current path. The control or gate terminals of the input transistors N1 and N2 are connected to a pair of input terminals INN and INP of the comparator circuit, respectively. In this example implementation, the input transistors N1 and N2 have a common connection to an input current source coupled to a second power supply terminal VSS. Specifically, the source terminals of the input transistors N1 and N2 are connected to this input current source.

[0034] This set of differential current paths in the input stage also includes a current mirror with differential transistor pairs P1 and P2, from which transistor P1 controls the current mirror. Therefore, the current IB1 flowing through transistors P1 and N1 controls the current flowing through transistor P2. The current flowing through transistor P2 is divided into a current IB2 flowing through transistor N2 and a current IB4 flowing to the output stage.

[0035] The output stage includes an output current path between the first power supply terminal VDD and the second power supply terminal VSS, and an output transistor P4 connected in the output current path and having a control terminal or gate terminal connected to the drain terminal of transistor P2 in the input stage. The output stage also includes an output current source with drive current IB7. The comparator output OUT is coupled to a node in the output current path between the output transistor P4 and the output current source.

[0036] According to the improved comparator concept, the comparator circuit also includes an auxiliary stage (framed in dashed box). The auxiliary stage includes an auxiliary current path between the first power supply terminal VDD and the second power supply terminal VSS. In this auxiliary current path, a first auxiliary transistor P3 is connected, with its control terminal or gate terminal connected to the control terminal of the output transistor P4. The source terminals of both the first auxiliary transistor P3 and the output transistor P4 are connected to the first power supply terminal VDD. The auxiliary stage also includes a voltage follower formed by transistors P5 and P6, with transistor P5 connected to the auxiliary current path and controlling the voltage follower. For this purpose, transistor P5 is diode-connected, i.e., its control terminal is connected to its drain terminal. To perform the voltage follower function, the control terminal of transistor P6 is connected to the control terminal of transistor P5. The controlled portion of transistor P6 is connected between the control terminal of the output transistor P4 and the common connection between the input transistors N1, N2 and the input current source. The auxiliary current path also includes a current source for driving current IB5, one end of which is connected to the second power supply terminal VSS and the other end to the drain terminal of transistor P5. Current IB6 flows through a third auxiliary transistor P6.

[0037] During the operation of the comparator circuit, the input terminal INN, for example, is the negative input or inverting input of the comparator, to which a reference voltage that defines the comparator's threshold voltage can be provided. Therefore, when the input voltage at the positive input or non-inverting input INP is higher than the reference voltage, the comparator's output OUT will be high, corresponding to, for example, the potential at the first power supply terminal VDD; otherwise, it will be low, corresponding to the potential at the second power supply terminal VSS.

[0038] Assuming the comparator circuit operates without an auxiliary stage, when the potential at input INP is lower than the potential at input INN, the output of the differential pair, i.e., the connection to the output stage with potential VDIFFOUTN, will typically (without applying the improved comparator concept) be the same as or close to the high rail defined by the first power supply terminal VDD. If the voltage at input INP rises rapidly to the potential at input INN, node VDIFFOUTN needs to stabilize back to its operating point, which is approximately one threshold voltage lower than the power supply voltage at the first power supply terminal VDD or the gate-source voltage of output transistor P4. Without the improved comparator concept, this recovery phase occurs in a slewing manner, reducing the comparator's speed.

[0039] The improved comparator concept limits the offset of node VDIFFOUTN through a regulation loop formed by auxiliary transistors P3, P5, and P6, thus preventing node VDIFFOUTN from reaching the high rail. Therefore, node VDIFFOUTN stabilizes back to its operating point from a voltage level slightly above the final operating point, rather than recovering from the potential of the high rail, resulting in faster stabilization.

[0040] For example, this is achieved by determining the dimensions of the first, second, and third auxiliary transistors P3, P5, and P6 such that, at the operating point of the auxiliary stage, the voltage difference between the source and control terminals of the first auxiliary transistor P3 is greater than zero and lower than the threshold voltage difference of the output transistor P4. This threshold voltage difference of the output transistor P4 can be defined as the voltage difference when the output transistor P4 switches from a non-conducting state to a conducting state, corresponding to the switching from a low level to a high level at the comparator output OUT. For example, this can be achieved by setting the threshold voltage of the first auxiliary transistor P3 to be lower than the threshold voltage of the output transistor.

[0041] For example, this setup can be achieved by having the first auxiliary transistor P3 typically matched to the output transistor P4 and acting as a reference transistor for defining the upper limit voltage of node VDIFFOUTN. For example, by selecting a lower current density for transistor P3 relative to transistor P4, the auxiliary transistor P3 will require a smaller gate-source voltage, thereby generating a higher voltage at node VDIFFOUTN than the operating point of output transistor P4 when the differential input voltage at inputs INP, INN is 0V.

[0042] The first auxiliary transistor P3, together with the auxiliary current source drive current IB5, forms a general-purpose amplifier, thus providing gain. As described above, the second and third auxiliary transistors P5 and P6 form the voltage follower or source follower output of the general-purpose amplifier. The source terminal of the third auxiliary transistor P6 is the output of the voltage follower, which adjusts the voltage at node VDIFFOUTN when the voltage at input INP is lower than the voltage at input INN.

[0043] In an alternative implementation, the dimensions of the auxiliary transistors are determined such that the threshold voltage of the second auxiliary transistor P5 is lower than the threshold voltage of the third auxiliary transistor. Alternatively, the determination of the threshold voltage dimensions of transistors P3 and P4 can be combined with the determination of the dimensions of auxiliary transistors P5 and P6.

[0044] Similarly, the current density of the second auxiliary transistor P5 can be designed to be less than the current density of the third auxiliary transistor P6.

[0045] The potential at node VDIFFOUTN is regulated by establishing the dependence between the gate-source voltages of auxiliary transistors P3, P5, and P6 and the currents flowing through them.

[0046] The third auxiliary transistor P6 reduces the current IB6 required to pull down the voltage at node VDIFFOUTN to the tail of the differential input pair N2, N1. This balances the current in the differential pair N1, N2.

[0047] For example, in a tilted scenario where the voltage at the positive input terminal INP is lower than the voltage at the negative input terminal INN, if the auxiliary stage were absent, the entire current IB3 would flow downwards from IB1. However, due to the presence of the auxiliary stage, the current IB6 required to pull down the voltage at node VDIFFOUTN to a defined level is reduced to the current source providing the current IB3. This means that approximately half of the current IB3 will flow downwards from IB1, while the other half is provided by the current IB6. This pre-biases the input stage of the comparator circuit to a configuration close to the switching point, except for the input transistor N2, which continuously senses the voltage at the positive input terminal INP. Once the differential input voltage at input terminals INP and INN becomes 0V, the differential pair N1 and N2 can switch rapidly.

[0048] Once the differential input voltage of the comparator becomes 0V, the auxiliary stage will no longer function, and its regulation will be disabled, allowing the comparator circuit to switch at normal accuracy.

[0049] An auxiliary stage based on the improved comparator concept adds an additional current branch to an existing comparator circuit with input and output stages, as described above. Gain-speed performance allows for at least compensation of the additional current branch, resulting in a power-efficient solution.

[0050] Since slewing prevention is achieved through adjustment, the accuracy and performance stability obtained under process changes and ambient temperature are well controlled.

[0051] This regulation is achieved by sharing the bias current provided by the input current source connected to the pair of differential input transistors. This ensures high energy efficiency and high-speed characteristics without affecting the comparator's accuracy. Specifically, when the comparator is tilted and accuracy is not critical, this is achieved by sharing current with the pair of differential input transistors N1 and N2. No additional current consumption is required to improve speed, except for an extra current branch, i.e., an auxiliary current path.

[0052] The auxiliary stage is power-efficient, fast, and does not affect the comparator's accuracy. Because the auxiliary stage's additional circuitry is relatively small, it is also suitable for multi-channel devices, where area is critical for each module present in each channel.

[0053] Figure 2 An alternative implementation of the comparator circuit based on the improved component concept is shown, which is based on Figure 1 The implementation shown. Therefore, only the implementation shown will be explained. Figure 1 The differences in the implementation methods.

[0054] Instead of using a current mirror in the input stage Figure 2 The input stage of the implementation includes two diode-connected transistors P1 and P2 in each current path of the differential current path of the input stage. Although the current branch with transistor P2 is not controlled by P1, assuming the auxiliary stage is absent, the voltage at node VDIFFOUTN still tends to remain on the high rail. Therefore, without the auxiliary stage, once the voltage at the positive input terminal INP approaches the voltage at the negative input terminal INN, the potential at the control terminal of the output transistor P4 will need to recover from such a voltage, thus causing the comparator output OUT to switch.

[0055] However, due to the existence of the auxiliary level, a combination with... Figure 1 The same effect is described, thus speeding up the switching at the comparator output OUT.

[0056] for Figure 1 and Figure 2 In both implementations, for example for biasing reasons, additional transistor pairs or a single transistor may exist in various current paths; however, this does not affect the general principles described in conjunction with the improved comparator concept. In any case, the voltage at the control terminal of the output transistor P4 is brought to a level close to the switching threshold of the output transistor P4.

[0057] Figure 3 Another example implementation of a comparator circuit based on the improved comparator concept is shown. The output stage and auxiliary stage are similar. Figure 1 and Figure 2 The corresponding implementation is described above. In this implementation, the input stage is implemented as a folded cascode amplifier with a set of differential paths, including current mirrors with transistors P1 and P2, which is similar to... Figure 1 The implementation is as follows. Furthermore, the differential current path includes a pair of bias transistors N3 and N4 controlled by a bias voltage VB. Each path of the differential current path includes a corresponding current source that drives currents IB8 and IB9 and couples the differential current path to a second power supply terminal VSS. The pair of input transistors is formed by transistors P7 and P8, whose input current source, driving current IB3, is connected to the first power supply terminal. The drain terminals of input transistors P7 and P8 are respectively connected to each differential current path. Specifically, transistor P7 is connected to a circuit with transistors P1 and N3, whose current source drives current IB8, and transistor P8 is connected to a circuit including transistors P2, N4, and a current source driving current IB9. Feedback from the auxiliary stage is connected to the common connection of transistors P7 and N3 via transistor P6.

[0058] By utilizing this implementation of the input stage, in the tilted state where no auxiliary stage exists, a result similar to... Figure 1 The implementation follows a similar pattern. Specifically, if the voltage at the positive input terminal INP is lower than the voltage at the negative input terminal INN, the current IB3 provided by the input current source will flow completely or almost completely through the input transistor P8, while little or no current will flow through the input transistor P7. Therefore, the current IB1 through transistor P1 must provide the full current IB8. Consequently, the mirror transistor P2 will also be controlled to an open-circuit state, causing the voltage at node VDIFFOUTN to be at or near the potential of the first power supply terminal VDD. Furthermore, in this state, the control terminal of the output transistor P4 will also be close to the high rail.

[0059] Utilize such as combination Figure 1In the auxiliary stage that operates as described, the potential at the control terminal of the output transistor P4 is adjusted so that the voltage difference between the source terminal and the control terminal of the first auxiliary transistor P3 is greater than 0 and lower than the threshold voltage difference of the output transistor P4. This reduces slewing if the comparator circuit is about to switch.

[0060] Because input transistor P7 does not supply current, current IB8 is the sum of currents IB1 and IB6. Utilizing the feedback from this current IB6 from the auxiliary stage, IB1 is reduced compared to an implementation without an auxiliary stage. Therefore, current IB6 is effectively reused. Further implementations of the input stage and / or variations of the output stage remain possible. In any case, the auxiliary stage reduces the slew rate of the output transistor.

[0061] Comparator circuits based on the improved comparator concept can be used in a variety of applications that require comparators with fast detection capabilities.

[0062] For example, Figure 4 An example implementation of a sensor front-end for a photodiode (PD) is shown. For example, the sensor front-end includes an integrator that can be coupled to the photodiode (PD) for integrating its photocurrent. The output of the integrator is coupled to processing circuitry that can process the integrated signal in the analog or digital domain. Furthermore, the output of the integrator is connected to the non-inverting positive input INP of a comparator implemented according to one of the examples described above. The negative inverting input is connected to a reference voltage source VREF, which can be a constant voltage source or a variable voltage source.

[0063] At the start of the integration period, the integrator output is below the reference voltage. However, once the integrated photocurrent, i.e., the voltage provided by the integrator, exceeds the level of the reference voltage, the comparator circuit CMP can indicate this crossover at the comparator output OUT with almost no delay. For example, this information can be used in the processing circuit PROC.

[0064] Figure 5 This illustrates another application of a comparator circuit in a ramp analog-to-digital converter (ADC). In this application, the first input, specifically the non-inverting input of the comparator CMP, is connected to the output of a ramp signal generator. The second input, the inverting input, is connected to a sample-and-hold element S / H, which samples the input signal VIN provided at the input terminal.

[0065] A ramp signal generator is formed, for example, by an integrator that integrates a constant reference voltage, thereby outputting a linear ramp voltage VINT. The integrator can be reset by a corresponding signal and based on a clock signal CLK.

[0066] At the beginning of each ramp cycle, the ramp signal VINT will be lower than the input voltage VIN at the inverting input INN. Once the ramp signal VINT crosses this level, the comparator output will switch from low to high accordingly. In other words, the output is low until then. The ramp ADC also includes an AND gate with a first input supplied with the clock signal CLK and a second input with an inverted version of the comparator output. Therefore, on each clock edge before crossing the ramp signal VINT, a pulse is supplied to the counter CNTR, which counts the corresponding pulse. Once the ramp signal VINT crosses the input voltage VIN, the AND gate provides no pulse, allowing the counter CNT's count value CV to remain constant. The counter value can be implemented using an N-bit word representing the digital equivalent of the input signal VIN.

[0067] As shown in the signal diagram, the input voltage VIN corresponds to the voltage of the ramp signal VINT after a given time t, which is defined by multiplying the counter value CV by the clock period T of the clock signal CLK, i.e., CV T.

[0068] Although the transistors are shown as p-channel or n-channel in the example implementation, the corresponding transistor types can also be completely changed to the opposite type, along with the switching of the power supply potential and the polarity of the power supply terminals VDD and VSS. Therefore, such alternative implementations are also covered by the scope defined in this disclosure and the claims.

[0069] Various implementations of comparator circuits, sensor front-ends, and ramp ADCs can be used, for example, in a variety of fixed or portable electronic devices, such as fixed electronic devices like medical imaging equipment like X-ray equipment or computed tomography equipment, or portable electronic devices like smartphones, wearable devices like smartwatches, or biosensors, portable sensor devices, etc., for example, in optical sensor applications.

[0070] It should be understood that this disclosure is not limited to the disclosed embodiments and the content specifically shown and described above. Rather, the features listed in the independent dependent claims or specification may be advantageously combined. Furthermore, the scope of this disclosure includes those variations and modifications that will be apparent to those skilled in the art and fall within the spirit of the appended claims. The term "comprising" as used in the claims or specification does not exclude other elements or steps of the corresponding feature or process. Where the terms "a" or "an" are used in conjunction with a feature, it does not exclude the presence of a plurality of such features. Furthermore, any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A comparator circuit, comprising: The input stage includes a set of differential current paths and a pair of differential input transistors (N1, N2); P7, P8), wherein the pair of differential input transistors (N1, N2); P7, P8) are coupled to the set of differential current paths and have control terminals connected to a pair of input terminals (INN, INP) of the comparator circuit; The output stage includes an output current path between a first power supply terminal (VDD) and a second power supply terminal (VSS), an output transistor (P4) connected in the output current path and having a control terminal connected to one of the current paths of the set of differential current paths, and a comparator output (OUT) connected to the output current path. and An auxiliary stage includes an auxiliary current path between the first power supply terminal (VDD) and the second power supply terminal (VSS), an auxiliary current source connected in the auxiliary current path, a first auxiliary transistor (P3) connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor (P4), and a voltage follower with a second auxiliary transistor (P5) and a third auxiliary transistor (P6) having control terminals connected together, wherein the second auxiliary transistor (P5) is connected in the auxiliary current path and controls the voltage follower, and wherein the third auxiliary transistor (P6) couples the control terminal of the output transistor (P4) to at least one current path in the set of differential current paths. The source terminals of the first auxiliary transistor (P3) and the output transistor (P4) are both connected to the first power supply terminal (VDD), the drain terminal of the first auxiliary transistor (P3) is connected to the source terminal of the second auxiliary transistor (P5), and the control terminal of the second auxiliary transistor (P5) is connected to its drain terminal.

2. The comparator circuit of claim 1, wherein the dimensions of the first, second, and third auxiliary transistors (P3, P5, P6) are designed such that at the operating point of the auxiliary stage, the voltage difference between the source terminal and the control terminal of the first auxiliary transistor (P3) is greater than zero and lower than the threshold voltage difference of the output transistor (P4).

3. The comparator circuit according to claim 2, wherein the voltage difference between the source terminal and the control terminal of the first auxiliary transistor (P3) is an absolute voltage difference.

4. The comparator circuit according to claim 2, wherein the current density of the first auxiliary transistor (P3) is lower than the current density of the output transistor (P4), and / or the current density of the second auxiliary transistor (P5) is lower than the current density of the third auxiliary transistor (P6).

5. The comparator circuit according to any one of claims 2-4, wherein the threshold voltage of the first auxiliary transistor (P3) is lower than the threshold voltage of the output transistor (P4), and / or the threshold voltage of the second auxiliary transistor (P5) is lower than the threshold voltage of the third auxiliary transistor (P6).

6. The comparator circuit according to any one of claims 1-4, wherein The input stage includes a set of differential current paths comprising a current mirror with a differential transistor pair (P1, P2); and One of the current paths in the set of differential current paths, connected to the control terminal of the output transistor (P4), is controlled by the current mirror.

7. The comparator circuit according to any one of claims 1-4, wherein The set of differential current paths of the input stage includes the pair of differential input transistors (N1, N2) and a current mirror having a pair of differential transistors (P1, P2). The input stage includes an input current source (IB3) having a common connection with the set of differential current paths of the input stage; and The third auxiliary transistor (P6) is connected between the control terminal of the output transistor (P4) and the common connection having the input current source (IB3).

8. The comparator circuit according to any one of claims 1-4, wherein The input stage has a set of differential current paths comprising a pair of differential input transistors (N1, N2) and a differential transistor pair (P1, P2); The input stage includes an input current source (IB3) having a common connection with a set of differential current paths of the input stage; and The third auxiliary transistor (P6) is connected between the control terminal of the output transistor (P4) and the common connection having the input current source (IB3).

9. The comparator circuit of claim 8, wherein each transistor of the differential transistor pair (P1, P2) is implemented in a diode-connected manner.

10. The comparator circuit according to any one of claims 1-4, wherein, The input stage is implemented as a folded cascode amplifier; The pair of differential input transistors (P7, P8) are coupled between a common current source and the set of differential current paths; and The set of differential current paths is coupled between the first and second power supply terminals (VDD, VSS) and includes a current mirror with a differential transistor pair (P1, P2).

11. A sensor front end for a photodiode, the sensor front end comprising: An integrator is used to integrate the photocurrent from the photodiode; and The comparator circuit according to any one of claims 1-10 has a first terminal (INP) connected to the output of the integrator and a second terminal (INN) connected to a pair of input terminals of a reference voltage source.

12. A ramp analog-to-digital converter (ADC) comprising a comparator circuit according to any one of claims 1 to 10, wherein The first terminal (INP) of the pair of input terminals is connected to the output of the ramp signal generator; The second terminal (INN) of the pair of input terminals is connected to a sample-and-hold element (S / H) that samples the input signal (Vin) provided at the input terminals; and The comparator output (OUT) is coupled to a counter circuit (CNTR) to provide a digital output value corresponding to the input signal.

13. An electronic device comprising one of the following: The comparator circuit according to any one of claims 1 to 10; The sensor front end according to claim 11; The ramp analog-to-digital converter according to claim 12.

14. The electronic device according to claim 13, wherein, The electronic device is implemented as one of the following: Fixed electronic devices; X-ray device; Computed tomography equipment; Portable electronic devices; Smartphones; Wearable devices; Portable sensor devices.

15. The electronic device according to claim 14, wherein, The wearable devices include smartwatches or biosensors.

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