Video data processing apparatus and method, display system

Abstract

Disclosed are a video data processing device and method and a display system, comprising a first acquisition module, a second acquisition module, a storage module and a processing module. The first acquisition module is configured to, in response to a received picture quality adjustment parameter, determine whether the picture quality adjustment parameter meets a preset condition, and when the picture quality adjustment parameter meets the preset condition, send the picture quality adjustment parameter to the storage module. The storage module is configured to cache the picture quality adjustment parameter, and in response to control of a frame synchronization signal, send the picture quality adjustment parameter to the processing module. The second acquisition module is configured to acquire original video data, and in response to a valid data selection signal, send the original video data to the processing module. The transmission time period of the picture quality adjustment parameter and the transmission time period of the original video data have no overlap. The processing module is configured to perform data processing on the original video data according to the picture quality adjustment parameter, and generate target video data.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a video data processing device, a video data processing method, and a display system. Background Technology

[0002] With the continuous development of science and technology, terminal devices such as professional monitors, computers, and smartphones are widely used. To achieve image display effects that meet user requirements, these devices adjust the image according to user-inputted commands. For example, they might adjust the image's color gamut based on the user's color gamut switching command, or adjust the image's colors based on the user's color adjustment command. Summary of the Invention

[0003] This disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a video data processing apparatus and method, and a display system.

[0004] To achieve the above objectives, this disclosure provides a video data processing apparatus, comprising: a first acquisition module, a second acquisition module, a storage module, and a processing module, wherein,

[0005] The first acquisition module is configured to, in response to the received image quality adjustment parameters, determine whether the image quality adjustment parameters meet preset conditions, and when the image quality adjustment parameters meet the preset conditions, send the image quality adjustment parameters to the storage module;

[0006] The storage module is configured to cache the image quality adjustment parameters and, in response to the control of the frame synchronization signal, send the image quality adjustment parameters to the processing module.

[0007] The second acquisition module is configured to acquire raw video data and, in response to a valid data strobe signal, send the raw video data to the processing module; wherein the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the raw video data.

[0008] The processing module is configured to process the original video data according to the image quality adjustment parameters to generate target video data.

[0009] In some embodiments, the first acquisition module includes: a receiving submodule and a verification submodule, wherein...

[0010] The receiving submodule is configured to receive the image quality adjustment parameters sent by the system chip;

[0011] The verification submodule is configured to determine whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the receiving submodule is controlled to send the image quality adjustment parameters to the storage module. When the image quality adjustment parameters do not meet the preset conditions, a data request signal is sent to the system chip so that the system chip resends the image quality adjustment parameters.

[0012] In some embodiments, the image quality adjustment parameters are serial data, which includes, in sequence: a first keyword, at least one valid data, a second keyword, and a check value; wherein the check value is obtained by performing a first operation on the first keyword, the second keyword, and the valid data between them.

[0013] The verification submodule is specifically configured to perform a second operation on the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the verification value in the received image quality adjustment parameters, and compare the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions.

[0014] In some embodiments, the first operation includes an XOR operation, and the second operation includes an XOR operation.

[0015] In some embodiments, the first acquisition module receives the image quality adjustment parameters in a first clock domain;

[0016] The device further includes: a timing generation module, configured to generate the frame synchronization signal and the valid data strobe signal in a second clock domain; wherein, there is a preset time interval between the valid state start time of the frame synchronization signal and the valid state start time of the valid data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain.

[0017] Specifically, the storage module is configured to cache the image quality adjustment parameters and send the image quality adjustment parameters to the processing module in the third clock domain starting from the effective state start time of the frame synchronization signal, wherein the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

[0018] In some embodiments, the storage module includes: a pulse generator and a first memory; wherein,

[0019] The first memory is configured to store the image quality adjustment parameters;

[0020] The pulse generator is configured to generate a pulse signal in the third clock domain. The pulse signal is used to control the first memory to output the image quality adjustment parameters to the processing module. The frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.

[0021] In some embodiments, the pulse generator includes: a first generation unit and a second generation unit, wherein,

[0022] The first generation unit is configured to delay the frame synchronization signal by a first time to obtain a delayed signal; wherein the first time is the single clock pulse width of the third clock domain;

[0023] The second generation unit is configured to invert the delay signal and then perform an AND operation with the frame synchronization signal to obtain the pulse signal.

[0024] In some embodiments, the second acquisition module includes: a receiver, a write memory controller, and a read memory controller;

[0025] The receiver is configured to receive the raw video data in a fourth clock domain;

[0026] The write memory controller is configured to write the original video data into the second memory under the fifth clock domain;

[0027] The read memory controller is configured to read the original video data in the second memory under the fifth clock domain, and send the original video data to the processing module under the second clock domain.

[0028] This disclosure also provides a display system, including: a display module, a system chip, and the aforementioned video data processing device.

[0029] The system chip is configured to output corresponding image quality adjustment parameters in response to an image quality adjustment command;

[0030] The display module is configured to display in response to target video data output by the display driver.

[0031] This disclosure also provides a video data processing method applied to a video data processing device, wherein the video data processing device includes: a first acquisition module, a second acquisition module, a storage module, and a processing module, and the method includes:

[0032] In response to the received image quality adjustment parameters, the first acquisition module determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the first acquisition module sends the image quality adjustment parameters to the storage module.

[0033] The storage module caches the image quality adjustment parameters and, in response to the control of the frame synchronization signal, sends the image quality adjustment parameters to the processing module.

[0034] The second acquisition module acquires the raw video data and, in response to a valid data strobe signal, sends the raw video data to the processing module; wherein the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the raw video data.

[0035] The processing module processes the original video data according to the image quality adjustment parameters to generate target video data.

[0036] In some embodiments, the first acquisition module includes: a receiving submodule and a verification submodule.

[0037] The first acquisition module, in response to the received image quality adjustment parameters, determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the module sends the image quality adjustment parameters to the storage module, specifically including:

[0038] The receiving submodule receives the image quality adjustment parameters sent by the system chip;

[0039] The verification submodule determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, it controls the receiving submodule to output the image quality adjustment parameters to the storage module. When the image quality adjustment parameters do not meet the preset conditions, it sends a data request signal to the system chip so that the system chip resends the image quality adjustment parameters.

[0040] In some embodiments, the image quality adjustment parameters are serial data, which includes, in sequence: a first keyword, at least one valid data, a second keyword, and a check value; wherein the check value is obtained by performing a first operation on the first keyword, the second keyword, and the valid data between them.

[0041] The verification submodule determines whether the image quality adjustment parameters meet preset conditions, specifically including:

[0042] The verification submodule performs a second operation on the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the verification value in the received image quality adjustment parameters, and compares the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions.

[0043] In some embodiments, the first operation includes an XOR operation, and the second operation includes an XOR operation.

[0044] In some embodiments, the first acquisition module receives the image quality adjustment parameters in a first clock domain; the device further includes: a timing generation module;

[0045] The frame synchronization signal and the valid data strobe signal are both generated by the timing generation module in the second clock domain. There is a preset time interval between the effective state start time of the frame synchronization signal and the effective state start time of the valid data strobe signal. The clock frequency of the second clock domain is greater than the clock frequency of the first clock domain.

[0046] The storage module caches the image quality adjustment parameters and sends them to the processing module in the third clock domain starting from the effective state start time of the frame synchronization signal. The clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

[0047] In some embodiments, the storage module includes: a pulse generator and a first memory;

[0048] The storage module caches the image quality adjustment parameters and, starting from the effective state start time of the frame synchronization signal, sends the image quality adjustment parameters to the processing module in the third clock domain, specifically including:

[0049] The first memory stores the image quality adjustment parameters;

[0050] The pulse generator generates a pulse signal in the third clock domain. The pulse signal is used to control the first memory to output the image quality adjustment parameters to the processing module. The frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.

[0051] In some embodiments, the pulse generator generates a pulse signal in a third clock domain, specifically including:

[0052] The pulse generator delays the frame synchronization signal by a first time to obtain a delayed signal; and after inverting the delayed signal, it performs an AND operation with the frame synchronization signal to obtain the pulse signal; wherein, the first time is the single clock pulse width of the third clock domain.

[0053] In some embodiments, the second acquisition module includes: a receiver, a write memory controller, and a read memory controller;

[0054] The receiver receives the raw video data in the fourth clock domain;

[0055] The write memory controller writes the original video data into the second memory under the fifth clock domain;

[0056] The read memory controller reads the raw video data from the second memory under the fifth clock domain, and sends the raw video data to the processing module under the second clock domain. Attached Figure Description

[0057] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0058] Figure 1 This is a schematic diagram of a video data processing apparatus provided in some embodiments of the present disclosure.

[0059] Figure 2 This is a schematic diagram of a video data processing apparatus provided in some other embodiments of this disclosure.

[0060] Figure 3 This is a schematic diagram illustrating the composition of image quality adjustment parameters provided in some embodiments of this disclosure.

[0061] Figure 4 The following are waveform diagrams of some signals provided in some embodiments of this disclosure.

[0062] Figure 5 This is a schematic diagram of a video data processing method provided in some embodiments of this disclosure.

[0063] Figure 6 This is a schematic diagram of an optional approach to step S10 provided in some embodiments of this disclosure.

[0064] Figure 7 This is a schematic diagram of a display system provided in some embodiments of the present disclosure.

[0065] Figure 8 This is a schematic diagram of the display process of a display system provided in some embodiments of this disclosure. Detailed Implementation

[0066] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0067] Unless otherwise defined, the technical or scientific terms used in the embodiments of this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0068] During the use of display devices, color gamut and GAMA adjustments can be performed on the displayed image according to user needs. Taking color gamut adjustment as an example, the terminal device can use 3D LUT (Look Up Table) technology to adjust the color gamut of the image to be adjusted. Specifically, based on the original pixel value of each pixel in the image to be adjusted, the target pixel value of each pixel is obtained according to the data in the lookup table. Then, the adjusted image is displayed based on the target pixel value of each pixel.

[0069] Typically, color gamut adjustment parameters (i.e., data in the 3D LUT) are transmitted in heterogeneous systems. Specifically, these heterogeneous systems include a system-on-a-chip (SoC) and an FPGA (Field-Programmable Gate Array). When the SoC receives a user's color gamut adjustment command, it outputs the color gamut adjustment parameters to the FPGA via SPI (Serial Peripheral Interface). However, the color gamut adjustment parameters are large, requiring several frames for transmission, and are dynamically updated. This can lead to inconsistencies in the display of different areas within the same frame, where pixels are adjusted based on the original color gamut adjustment parameters while pixels in other areas are adjusted based on the updated parameters.

[0070] Figure 1 This is a schematic diagram of a video data processing apparatus provided in some embodiments of the present disclosure. Optionally, the video data processing apparatus 100 may be integrated into an FPGA. Figure 1As shown, the video data processing device 100 includes: a first acquisition module 110, a second acquisition module 120, a storage module 130, and a processing module 140.

[0071] The first acquisition module 110 is configured to, in response to the received image quality adjustment parameters, determine whether the image quality adjustment parameters meet preset conditions, and when the image quality adjustment parameters meet the preset conditions, send the image quality adjustment parameters to the storage module 130.

[0072] The image quality adjustment parameters can be sent by the system chip to the video processing device. For example, the system chip generates image quality adjustment parameters when it receives an image quality adjustment command input by the user. Image quality adjustment commands can be color gamut adjustment commands, Gamma adjustment commands, etc. Image quality adjustment parameters can be: parameters corresponding to Gamma adjustment commands and parameters corresponding to color gamut adjustment commands. Taking a color gamut adjustment command as an example, this command can further include: a first color gamut adjustment command to adjust the image color gamut to a first color gamut, a second color gamut adjustment command to adjust the image color gamut to a second color gamut, a third color gamut adjustment command to adjust the image color gamut to a third color gamut, etc. The color gamut adjustment parameters output by the system chip can also be different for different color gamut adjustment commands.

[0073] The first acquisition module 110 can receive image quality adjustment parameters sent by the system chip via the SPI interface. The SPI interface can transmit image quality adjustment parameters in a first clock domain (i.e., the SPI clock domain). The first clock domain is used to generate a first reference signal, which is a clock signal. The SPI interface responds to the rising edge (or falling edge, or high level state, or low level state) of the first reference signal to perform data transmission. Therefore, the data transmission rate in the first clock domain is related to the clock frequency of the first reference signal.

[0074] Storage module 130 is configured to store image quality adjustment parameters and, in response to the control of the frame synchronization signal, sends the image quality adjustment parameters to processing module 140. The frame synchronization signal can be generated in the local clock domain, and its period is the display period of each frame in the video. Furthermore, "in response to the control of the frame synchronization signal, sending the image quality adjustment parameters to processing module 140" means that the image quality adjustment parameters are sent to processing module 140 starting from the beginning of the frame synchronization signal's active state, or starting from the end of the frame synchronization signal's active state, or starting from a point between the beginning and end of the active state of the frame synchronization signal, until the image quality adjustment parameters have been completely sent. For example, the active state is a high-level state.

[0075] The second acquisition module 120 is configured to acquire raw video data and, in response to a valid data strobe signal, transmit the raw video data to the processing module 140. The raw video data can be sent from a video source to the video data processing device 100. There is a preset time interval between the start time of the valid state of the valid data strobe signal and the start time of the valid state of the frame synchronization signal. This preset time interval is the frame blanking phase of each frame's display cycle. The transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the raw video data.

[0076] In some embodiments, the image quality adjustment parameters can be transmitted to the processing module 140 in the local clock domain, or the image quality adjustment parameters can be transmitted to the processing module 140 in the high-speed clock domain with a higher clock frequency.

[0077] Processing module 140 is configured to process the raw video data according to image quality adjustment parameters to generate target video data. This target video data can be sent to the display module via sending module 160 for display. Sending module 160 can use the V-BY-ONE standard for data transmission.

[0078] It should be noted that the processing module 140 receives the image quality adjustment parameters and the original video data at different times. When the processing module 140 receives the image quality adjustment parameters, it can store them and use them to process subsequently received original video data. During certain time periods, the processing module 140 may not receive the image quality adjustment parameters, but only the original video data including multiple frames. In this case, the processing module 140 can use the currently stored image quality adjustment parameters to process the original video data.

[0079] In some examples, the image quality adjustment parameters are the parameters required when using 3D-LUT for color gamut adjustment. The processing module 140 can specifically perform three-dimensional interpolation processing on the original video data according to the image quality adjustment parameters.

[0080] In this embodiment, after the image quality adjustment parameters output by the system chip are sent to the video data processing device 100, the storage module 130 first caches the received image quality adjustment parameters, and then, under the control of the frame synchronization signal, sends the image quality adjustment parameters to the processing module 140. The second acquisition module 120 sends the original video data to the processing module 140 under the control of the valid data strobe signal, and the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the original video data. This ensures that when the processing module 140 processes the same frame of video image, it does so based on the same image quality adjustment parameters, thereby ensuring that the display effect of different areas in the same frame of video image is consistent.

[0081] Figure 2 This is a schematic diagram of a video data processing apparatus provided in some other embodiments of this disclosure, such as... Figure 2 As shown, the first acquisition module 110 includes a receiving submodule 112 and a verification submodule 113.

[0082] The receiving submodule 112 is configured to receive image quality adjustment parameters sent by the system chip.

[0083] Optionally, the image quality adjustment parameters are serial data. Figure 3 A diagram illustrating the components of image quality adjustment parameters, as shown below. Figure 3 As shown, the image quality adjustment parameters are arranged in the following order: the first keyword HEAD, at least one valid data DATA0~DATAn, the second keyword END, and the checksum CRC. The checksum CRC is generated by the system chip and is obtained by performing a first operation on the first keyword HEAD, the second keyword END, and the valid data DATA0~DATAn between them.

[0084] Specifically, the receiving submodule 112 may include: a first detection unit 112a and a second detection unit 112b. The first detection unit 112a is used to detect a first keyword in the serial data, and the second detection unit 112b is used to detect a second keyword in the serial data. After the receiving submodule 112 detects the first keyword and the second keyword, it can further determine the valid data between the first keyword and the second keyword, as well as the check code after the second keyword.

[0085] For example, to distinguish the first key, the second key, and the valid data in the serial data, the overall bit width of the image quality adjustment parameters can be set to 32 bits; the bit width of the valid data can be 30 bits, with the high two bits of the valid data padded with 0s; the high two bits of the first key and the high two bits of the second key can be selected from "01", "10", and "11", respectively. For example, the first key is a 32-bit hexadecimal number: FFFF_FFFF_FFFF_FFFF; the second key is a 32-bit hexadecimal number: 7FFF_FFFF_FFFF_FFFF.

[0086] For example, the first operation includes the XOR operation.

[0087] That is, the keyword CRC = HEAD^DATA0^DATA1……^DATAn^END.

[0088] The verification submodule 113 is configured to determine whether the image quality adjustment parameters meet the preset conditions. When the image quality adjustment parameters meet the preset conditions, the receiving submodule 112 is controlled to output the image quality adjustment parameters to the storage module 130. When the image quality adjustment parameters do not meet the preset conditions, a data request signal is sent to the system chip 300 so that the system chip 300 resends the image quality adjustment parameters.

[0089] Optionally, the verification submodule 113 is specifically configured to perform a second operation on the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the verification value in the received image quality adjustment parameters, and compare the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions, that is, it is determined that a transmission error has occurred in the image quality adjustment parameters during transmission. At this time, a data request signal is sent to the system chip 300 to request the system chip 300 to resend the image quality adjustment data.

[0090] The second operation includes an XOR operation. The result of the second operation is denoted as CRC'.

[0091] CRC'=HEAD^DATA0^DATA1......^DATAn^END^CRC

[0092] When the first operation is an XOR operation, then CRC' = CRC^CRC = 0 if the image quality adjustment parameters are transmitted accurately; therefore, in some embodiments, when both the first and second operations are XOR operations, the target value can be set to 0.

[0093] In some embodiments, such as Figure 2As shown, the video data processing device 100 also includes a timing generation module 150, which is configured to generate a frame synchronization signal and a valid data strobe signal in a second clock domain (i.e., the local clock domain mentioned above). There is a preset time interval between the start time of the valid state of the frame synchronization signal and the start time of the valid state of the valid data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain. For example, the start time of the valid state of the frame synchronization signal can be the rising edge of the frame synchronization signal, and the preset time interval between the start time of the valid state of the frame synchronization signal and the start time of the valid state of the valid data strobe signal is the frame blanking phase in one frame image display cycle. The second clock domain is used to generate a second reference signal, which is a clock signal. The timing generation module 150 can generate the frame synchronization signal and the valid data strobe signal based on the second reference signal; the sending module 160 can also send the target video data to the display module based on the second reference signal. For example, the second reference signal is generated by the local crystal oscillator. For example, when the local crystal oscillator generates the rising edge (or falling edge) of the m-th second reference signal, the frame synchronization signal is at the rising edge; when the local crystal oscillator generates the rising edge (or falling edge) of the n-th second reference signal, the frame synchronization signal is at the falling edge, m > n, and m and n are both integers.

[0094] The timing of the signals output by the timing generation module 150 is shown in Table 1 below. Here, 1VCLK represents the time of one clock in the second clock domain; 1Line represents the time to display one line.

[0095] Table 1

[0096]

[0097]

[0098] The storage module 130, starting from the effective state start time of the frame synchronization signal, sends the image quality adjustment parameters to the processing module 140 under the third clock domain. The third clock domain is used to generate a third reference signal, which is a clock signal. Under the third clock domain, the storage module 130 can perform data transmission in response to the rising edge (or falling edge, or high level state, or low level state) of the third reference signal. Therefore, the data transmission rate under the third clock domain is related to the clock frequency of the third reference signal. The clock frequency of the third clock domain is greater than the clock frequency of the second clock domain. For example, the clock frequency of the third clock domain is twice that of the second clock domain. Sending the image quality adjustment parameters under the third clock domain ensures that the image quality adjustment parameters are transmitted completely during the frame blanking phase.

[0099] The effective start time of the frame synchronization signal can be the rising edge. However, since the storage module 130 cannot directly detect the signal edge in actual circuit design, in practical applications, a pulse signal can be generated based on the frame synchronization signal in the third clock domain, and the image quality adjustment parameters can be sent under the control of this pulse signal. Specifically, the storage module 130 includes a pulse generator 132 and a first memory 131, which can be RAM (random access memory). The pulse generator 132 is configured to generate a pulse signal in the third clock domain, and the pulse signal is used to control the first memory 131 to output the image quality adjustment parameters to the processing module 140. Figure 4 Here are waveform diagrams of some signals provided in some embodiments of this disclosure, such as... Figure 4 As shown, DE is the valid data strobe signal. The frequency of the pulse signal SOF is the same as the frequency of the frame synchronization signal VS, and the rising edge of the pulse signal SOF is the same as the start time of the valid state of the frame synchronization signal VS; the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

[0100] Optionally, the pulse generator 132 includes a first generation unit and a second generation unit. The first generation unit is configured to delay the frame synchronization signal VS by a first time T1 to obtain a delayed signal VS_DLY (e.g., ...). Figure 4 (as shown); where the first time T1 is the single clock pulse width of the third clock domain. The second generation unit is configured to invert the delay signal VS_DLY and then perform an AND operation with the frame synchronization signal VS to obtain the pulse signal SOF.

[0101] It should be noted that both the frame synchronization signal VS and the delay signal VS_DLY are signals that switch between high and low levels; inverting the signals interchanges their high and low states. Performing a bitwise AND operation on the two signals yields a pulse signal. During periods when both signals are high, the pulse signal SOF is high; otherwise, SOF is low.

[0102] In some embodiments, the second acquisition module 120 includes a receiver 121, a write memory controller 122, and a read memory controller 123.

[0103] The receiver 121 is configured to receive raw video data in the fourth clock domain. The receiver 121 receives raw video data through the SDI (serial digital interface) and converts the received serial data into parallel video data.

[0104] The fourth clock domain is the clock domain of the video source. The fourth clock domain is used to generate the fourth reference signal, which is a clock signal. The video source responds to the rising edge (or falling edge, or high level state, or low level state) of the fourth reference signal to transmit data. Therefore, the data transmission rate in the fourth clock domain is related to the clock frequency of the fourth reference signal.

[0105] The write memory controller 122 is configured to write raw video data to the second memory 200 under the fifth clock domain. For example, the second memory 200 is a DDR (Double Data Rate) memory, and the fifth clock domain is the read / write clock domain of the DDR.

[0106] The memory controller 123 is configured to read the original video data in the memory under the fifth clock domain when the valid data strobe signal reaches the valid state, and send the original video data to the processing module 140 under the second clock domain.

[0107] The fifth clock domain is used to generate a fifth reference signal, which is a clock signal. The write memory controller 122 writes data to the second memory in response to the rising edge (or falling edge, or high level, or low level) of the fifth reference signal; the read memory controller 123 reads data in response to the rising edge (or falling edge, or high level, or low level) of the fifth reference signal. Therefore, the data read rate and data write rate in the fifth clock domain are related to the clock frequency of the fifth reference signal.

[0108] Since the original video data from the video source is transmitted to the receiver 121 under the fourth clock domain, while the original video data received by the processing module 140 is transmitted under the second clock domain, the original video data needs to be transmitted across clock domains during the transmission process from the video source to the processing module 140. This cross-clock domain transmission can be achieved through the settings of the read memory controller 123 and the write memory controller 122. Additionally, the video data processing device 100 may also include a switching module configured to retrieve pre-stored preset image data from the second memory 200 or other locations and output it to the processing module 140 when the receiver 121 does not receive original video data, or to directly send it to the display module via the sending module 160. This ensures that even when the video data processing device 100 does not receive video data, the display module can still display a preset image to indicate to the user that no video data is currently input.

[0109] Figure 5 This is a schematic diagram of a video data processing method provided in some embodiments of this disclosure, which is applied to the aforementioned video data processing apparatus 100. (In conjunction with...) Figure 2and Figure 5 As shown, the video data processing method includes:

[0110] S10, the first acquisition module 110, in response to the received image quality adjustment parameters, determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the image quality adjustment parameters are sent to the storage module 130. In some embodiments, the image quality adjustment parameters are sent from the system chip to the first acquisition module 110, and the first acquisition module 110 transmits the parameters to the first acquisition module 110 under a first clock domain. For example, the system chip sends the image quality adjustment parameters to the first acquisition module 110 through an SPI interface, where the first clock domain is the SPI clock domain.

[0111] S20, storage module 130 caches the image quality adjustment parameters and, in response to the control of the frame synchronization signal, sends the image quality adjustment parameters to processing module 140.

[0112] S30, the second acquisition module 120 acquires the original video data and, in response to the valid data strobe signal, transmits the original video data to the processing module 140; wherein the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the original video data. In some embodiments, the frame synchronization signal and the valid data strobe signal are generated by the timing generation module 150 in the second clock domain; wherein there is a preset time interval between the valid state start time of the frame synchronization signal and the valid state start time of the valid data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain.

[0113] S40 and processing module 140 process the original video data according to the image quality adjustment parameters to generate target video data.

[0114] It should be noted that the process of step S30 is independent of the processes of steps S10 to S20.

[0115] Figure 6 This is a schematic diagram illustrating an optional approach to step S10 provided in some embodiments of this disclosure, such as... Figure 6 As shown, in some embodiments, step S10 specifically includes:

[0116] S11, Receiver submodule 112 receives the image quality adjustment parameters sent by the system chip.

[0117] S12, the verification submodule 113 determines whether the image quality adjustment parameters meet the preset conditions. When the image quality adjustment parameters meet the preset conditions, the control receiving submodule 112 outputs the image quality adjustment parameters to the storage module 130. When the image quality adjustment parameters do not meet the preset conditions, a data request signal is sent to the system chip 300 so that the system chip 300 resends the image quality adjustment parameters.

[0118] The image quality adjustment parameters are serial data, which includes, in sequence: a first keyword, at least one valid data, a second keyword, and a check value. The check value is obtained by performing a first operation on the first keyword, the second keyword, and the valid data between them. In this case, step S12 specifically includes: the verification submodule 113 performs a second operation on the first keyword, the second keyword, the valid data between the first and second keywords, and the check value in the received image quality adjustment parameters, and compares the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions.

[0119] Both the first and second operations can be XOR operations.

[0120] Specifically, step S20 includes: S20a, starting from the effective state start time of the frame synchronization signal, the storage module 130 sends the image quality adjustment parameters to the processing module 140 in the third clock domain, wherein the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

[0121] As described above, the storage module 130 specifically includes a pulse generator 132 and a first memory 131. In this case, step S20a specifically includes: the first memory 131 storing image quality adjustment parameters; the pulse generator 132 generating a pulse signal in the third clock domain, the pulse signal being used to control the first memory 131 to output the image quality adjustment parameters to the processing module 140; wherein, the frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge time of the pulse signal is the same as the effective state start time of the frame synchronization signal; the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

[0122] Specifically, the pulse generator 132 generates a pulse signal in the third clock domain, which includes: delaying the frame synchronization signal by a first time to obtain a delayed signal; and inverting the delayed signal and performing an AND operation with the frame synchronization signal to obtain the pulse signal; wherein the first time is the single clock pulse width of the third clock domain.

[0123] In some embodiments, step S30 specifically includes: receiver 121 receiving raw video data in a fourth clock domain; write memory controller 122 writing the raw video data into second memory 200 in a fifth clock domain; read memory controller 123 reading the raw video data in the memory in the fifth clock domain and sending the raw video data to processing module 140 in the second clock domain.

[0124] The process of data processing using the video data processing device 100 is described above and will not be repeated here.

[0125] Figure 7 This is a schematic diagram of a display system provided in some embodiments of this disclosure. The display system can be a monitor system, computer, smartphone, or other terminal device. Figure 7 As shown, the display system includes: a display module 400, a system chip 300, and the aforementioned video data processing device 100.

[0126] The system chip 300 is configured to output corresponding image quality adjustment parameters in response to image quality adjustment commands.

[0127] The display module 400 is configured to display target video data output by the video data processing device 100. The display module 400 includes a display panel and a driving circuit, the driving circuit being configured to provide a driving signal to the display panel based on the target video data to control the display panel to perform the display.

[0128] Figure 8 This is a schematic diagram of the display process of the display system provided in some embodiments of this disclosure, such as... Figure 8 As shown, the display process includes:

[0129] When the system chip 300 receives the image quality adjustment instruction, it performs step S1a: the system chip 300 sends the image quality adjustment parameters to the video data processing device 100.

[0130] S1b: After receiving the image quality adjustment parameters, the first acquisition module 110 of the video data processing device 100 determines whether the image quality adjustment parameters meet the preset conditions. If they do, step S1c is performed; otherwise, a data request instruction is sent to the system chip 300, thereby executing step S1a again.

[0131] S1c: Output the image quality adjustment parameters to the storage module 130 so that the storage module 130 can cache the image quality adjustment parameters.

[0132] S1d When the frame synchronization signal begins to reach an effective state, the storage module 130 sends the cached image quality adjustment parameters to the processing module 140.

[0133] S1e, the processing module 140 updates the parameters stored internally based on the received image quality adjustment parameters.

[0134] In addition, the video source sends raw video data to the video data processing device 100, thereby causing the video data processing module 140 to execute steps S2a to S3.

[0135] S2a, the write memory controller 122 of the video data processing module 140 writes the received raw video data to the second memory.

[0136] S2b, the memory controller 123 of the video data processing module 140 reads the raw video data from the second memory.

[0137] S2c and memory controller 123 respond to the valid data strobe signal and send the raw video data to processing module 140.

[0138] S3. The processing module 140 processes the original video data using the currently stored image quality adjustment parameters to obtain the target video data.

[0139] S4. The display module displays the target video data.

[0140] When the system chip receives a quality adjustment instruction, the "currently stored quality adjustment parameters" in step S3 are the quality adjustment parameters issued by the system chip according to the quality adjustment instruction. When the system chip does not receive a quality adjustment instruction, the processing module 140 keeps its stored quality adjustment parameters unchanged. At this time, the video source can still send the original video data. At this time, the processing module 140 can process the data according to the unupdated quality adjustment parameters.

[0141] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A video data processing apparatus, comprising: The system comprises a first acquisition module, a second acquisition module, a storage module, and a processing module, wherein... The first acquisition module is configured to, in response to the received image quality adjustment parameters, determine whether the image quality adjustment parameters meet preset conditions, and when the image quality adjustment parameters meet the preset conditions, send the image quality adjustment parameters to the storage module; The storage module is configured to cache the image quality adjustment parameters and, in response to the control of the frame synchronization signal, send the image quality adjustment parameters to the processing module. The second acquisition module is configured to acquire raw video data and, in response to a valid data strobe signal, send the raw video data to the processing module; wherein the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the raw video data. The processing module is configured to process the original video data according to the image quality adjustment parameters to generate target video data.

2. The apparatus according to claim 1, wherein, The first acquisition module includes: a receiving submodule and a verification submodule, wherein, The receiving submodule is configured to receive the image quality adjustment parameters sent by the system chip; The verification submodule is configured to determine whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the receiving submodule is controlled to send the image quality adjustment parameters to the storage module. When the image quality adjustment parameters do not meet the preset conditions, a data request signal is sent to the system chip so that the system chip resends the image quality adjustment parameters.

3. The apparatus according to claim 2, wherein, The image quality adjustment parameters are serial data, which includes, in sequence: a first keyword, at least one valid data, a second keyword, and a check value; wherein, the check value is obtained by performing a first operation on the first keyword, the second keyword, and the valid data between them. The verification submodule is specifically configured to perform a second operation on the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the verification value in the received image quality adjustment parameters, and compare the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions.

4. The apparatus according to claim 3, wherein, The first operation includes an XOR operation, and the second operation includes an XOR operation.

5. The apparatus according to any one of claims 1 to 4, wherein, The first acquisition module receives the image quality adjustment parameters in the first clock domain; The device further includes: a timing generation module, configured to generate the frame synchronization signal and the valid data strobe signal in a second clock domain; wherein, there is a preset time interval between the valid state start time of the frame synchronization signal and the valid state start time of the valid data strobe signal, and the clock frequency of the second clock domain is greater than the clock frequency of the first clock domain. Specifically, the storage module is configured to cache the image quality adjustment parameters and send the image quality adjustment parameters to the processing module in the third clock domain starting from the effective state start time of the frame synchronization signal, wherein the clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

6. The apparatus according to claim 5, wherein, The storage module includes: a pulse generator and a first memory; wherein... The first memory is configured to store the image quality adjustment parameters; The pulse generator is configured to generate a pulse signal in the third clock domain. The pulse signal is used to control the first memory to output the image quality adjustment parameters to the processing module. The frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.

7. The apparatus according to claim 6, wherein, The pulse generator includes: a first generation unit and a second generation unit, wherein... The first generation unit is configured to delay the frame synchronization signal by a first time to obtain a delayed signal; wherein the first time is the single clock pulse width of the third clock domain; The second generation unit is configured to invert the delay signal and then perform an AND operation with the frame synchronization signal to obtain the pulse signal.

8. The apparatus according to claim 5, wherein, The second acquisition module includes: a receiver, a write memory controller, and a read memory controller; The receiver is configured to receive the raw video data in a fourth clock domain; The write memory controller is configured to write the original video data into the second memory under the fifth clock domain; The read memory controller is configured to read the original video data in the second memory under the fifth clock domain, and send the original video data to the processing module under the second clock domain.

9. A display system, comprising: The display module, the system chip, and the video data processing apparatus according to any one of claims 1 to 8 The system chip is configured to output corresponding image quality adjustment parameters in response to an image quality adjustment command; The display module is configured to display in response to the target video data output by the video data processing device.

10. A video data processing method applied to a video data processing device, wherein, The video data processing device includes: a first acquisition module, a second acquisition module, a storage module, and a processing module; the method includes: In response to the received image quality adjustment parameters, the first acquisition module determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the first acquisition module sends the image quality adjustment parameters to the storage module. The storage module caches the image quality adjustment parameters and, in response to the control of the frame synchronization signal, sends the image quality adjustment parameters to the processing module. The second acquisition module acquires the raw video data and, in response to a valid data strobe signal, sends the raw video data to the processing module; wherein the transmission time period of the image quality adjustment parameters does not overlap with the transmission time period of the raw video data. The processing module processes the original video data according to the image quality adjustment parameters to generate target video data.

11. The method according to claim 10, wherein, The first acquisition module includes: a receiving submodule and a verification submodule. The first acquisition module, in response to the received image quality adjustment parameters, determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, the module sends the image quality adjustment parameters to the storage module, specifically including: The receiving submodule receives the image quality adjustment parameters sent by the system chip; The verification submodule determines whether the image quality adjustment parameters meet preset conditions. When the image quality adjustment parameters meet the preset conditions, it controls the receiving submodule to output the image quality adjustment parameters to the storage module. When the image quality adjustment parameters do not meet the preset conditions, it sends a data request signal to the system chip so that the system chip resends the image quality adjustment parameters.

12. The method according to claim 11, wherein, The image quality adjustment parameters are serial data, which includes, in sequence: a first keyword, at least one valid data, a second keyword, and a check value; wherein, the check value is obtained by performing a first operation on the first keyword, the second keyword, and the valid data between them. The verification submodule determines whether the image quality adjustment parameters meet preset conditions, specifically including: The verification submodule performs a second operation on the first keyword, the second keyword, the valid data between the first keyword and the second keyword, and the verification value in the received image quality adjustment parameters, and compares the result of the second operation with the target value. When the result of the second operation is equal to the target value, it is determined that the image quality adjustment parameters meet the preset conditions; otherwise, it is determined that the image quality adjustment parameters do not meet the preset conditions.

13. The method according to claim 12, wherein, The first operation includes an XOR operation, and the second operation includes an XOR operation.

14. The method according to any one of claims 10 to 13, wherein, The first acquisition module receives the image quality adjustment parameters in the first clock domain; the device further includes: a timing generation module; The frame synchronization signal and the valid data strobe signal are both generated by the timing generation module in the second clock domain. There is a preset time interval between the effective state start time of the frame synchronization signal and the effective state start time of the valid data strobe signal. The clock frequency of the second clock domain is greater than the clock frequency of the first clock domain. The storage module caches the image quality adjustment parameters and sends them to the processing module in the third clock domain starting from the effective state start time of the frame synchronization signal. The clock frequency of the third clock domain is greater than the clock frequency of the second clock domain.

15. The method according to claim 14, wherein, The storage module includes: a pulse generator and a first memory; The storage module caches the image quality adjustment parameters and, starting from the effective state start time of the frame synchronization signal, sends the image quality adjustment parameters to the processing module in the third clock domain, specifically including: The first memory stores the image quality adjustment parameters; The pulse generator generates a pulse signal in the third clock domain. The pulse signal is used to control the first memory to output the image quality adjustment parameters to the processing module. The frequency of the pulse signal is the same as the frequency of the frame synchronization signal, and the rising edge of the pulse signal is the same as the start time of the effective state of the frame synchronization signal.

16. The method according to claim 15, wherein, The pulse generator generates pulse signals in the third clock domain, specifically including: The pulse generator delays the frame synchronization signal by a first time to obtain a delayed signal; and after inverting the delayed signal, it performs an AND operation with the frame synchronization signal to obtain the pulse signal; wherein, the first time is the single clock pulse width of the third clock domain.

17. The method according to claim 14, wherein, The second acquisition module includes: a receiver, a write memory controller, and a read memory controller; The receiver receives the raw video data in the fourth clock domain; The write memory controller writes the original video data into the second memory under the fifth clock domain; The read memory controller reads the raw video data from the second memory under the fifth clock domain, and sends the raw video data to the processing module under the second clock domain.

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