LDO circuit with low noise and high PSRR

Abstract

The application relates to a low-noise high-PSRR LDO circuit and belongs to the technical field of analog integrated circuits; the low-noise high-PSRR LDO circuit comprises a band-gap reference circuit, an error amplifier EA, a filter circuit, a buffer stage BUF, a PSRR enhancement circuit, MOS tubes MP1 and MP2, resistors Ra and Rb, a capacitor CL, a resistor RL and a resistor Resr; an RC low-pass filter structure composed of active resistors formed by the MOS tubes and a capacitor is adopted to filter out the output noise power of the band-gap reference and the error amplifier. The error amplifier, the output buffer stage and the power stage jointly form a three-stage operational amplifier structure to ensure the stability of the output voltage. Meanwhile, the PSRR enhancement circuit is adopted to ensure that the LDO has a good power supply rejection ratio. The low-noise high-PSRR LDO circuit introduces the filter circuit and the PSRR enhancement circuit, filters out the output noise of the band-gap reference and the error amplifier, and enhances the PSRR of the LDO.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog integrated circuits, and relates to a low-noise high-PSRR LDO circuit. BACKGROUND

[0002] With the rapid development of science and technology, mobile portable devices have become indispensable in people's lives. In order to ensure the stable operation of electronic devices, a high-reliability stable power supply is also essential. At present, most mobile portable applications and high-precision sensitive systems need low-noise high-power-supply-rejection-ratio voltage stabilizers as on-chip power supplies. As an important member of power management chips, LDO can be applied to radio frequency circuits and AD / DA converters and other circuits with high requirements for power supply noise due to its small size, high stability, low noise and low cost. Therefore, the low-noise high-PSRR LDO circuit has become the focus of researchers.

[0003] The noise in the traditional LDO circuit mainly comes from the bandgap reference circuit and the error amplifier circuit, and the bandgap reference is the main noise source. The power supply ripple of the LDO has multiple paths from the input coupling to the output end. The first path is coupled from the bandgap reference circuit and the error amplifier to the output end. The second path is from the buffer stage to the output. The third path is coupled from the input through the power adjustment tube to the output end.

[0004] On the one hand, in the design of the LDO circuit, the common methods to improve the noise include introducing a filter circuit at the output end of the bandgap reference, connecting a unit gain buffer after the current source reference, increasing the area of the input pair tube and the current source, and reducing the resistance value of the feedback resistance network. Among them, a capacitor is introduced at the output end of the bandgap reference circuit to form an RC low-pass filter with the output resistance and the capacitor of the reference, but a relatively large resistance is needed, which will consume the chip area. Although the unit gain buffer reduces the thermal noise of the bandgap reference, it consumes a large amount of static current. Increasing the area of the input pair tube and the current source can reduce the flicker noise generated by the error amplifier, but it will consume static current and chip area. Reducing the resistance value of the feedback resistance network can reduce the thermal noise generated by the resistance, but it will increase the overall static current of the voltage stabilizer.

[0005] In a second aspect, common methods for improving PSRR include cascading LDO to preprocess the power supply, introducing a filter circuit between the power supply and the output terminal, and using an NMOS tube as the adjusting tube. The cascading LDO preprocessing method can optimize the PSRR of the circuit, but increases the complexity and design cost of the circuit, consumes more power and chip area, and increases the pressure difference of the LDO. The filter circuit introduced between the power supply and the circuit reduces the influence of the power supply ripple on the output terminal of the LDO circuit and improves the PSRR, but a large area of resistance and capacitance is required to obtain a good cutoff frequency, which increases the cost. The use of an NMOS tube as an adjusting tube makes the power supply voltage ripple not affect the gate-source voltage of the adjusting tube, thereby achieving good PSRR performance, but it results in a larger pressure difference and more power consumption of the LDO. SUMMARY

[0006] The technical problem solved by the present application is to overcome the shortcomings of the prior art and provide an LDO circuit with low noise and high PSRR, which effectively improves the noise and PSRR of the LDO without consuming excessive chip area and ensuring the pressure difference.

[0007] The technical solution of the present application is:

[0008] An LDO circuit with low noise and high PSRR includes a bandgap reference circuit, an error amplifier EA, a filter circuit, a buffer stage BUF, a PSRR enhancement circuit, MOS tubes MP1 and MP2, resistors Ra and Rb, a capacitor CL, a resistor RL, and a resistor Resr.

[0009] The output terminal VREF of the bandgap reference circuit module is connected to one input terminal of the error amplifier EA. The other input terminal of the error amplifier EA is connected to the negative terminal of the resistor Ra and the positive terminal of the resistor Rb. The output terminal of the error amplifier EA is connected to the filter circuit. The power supply terminal of the error amplifier EA, the power supply terminal of the buffer stage BUF, the power supply terminal of the PSRR enhancement circuit, and the source electrode of the MOS tube MP1 are all connected to the input Vin. The output of the filter circuit is connected to the gate electrode of the MOS tube MP1 and the PSRR enhancement circuit after passing through the BUF. The bias of the PSRR enhancement circuit is provided by the bandgap reference circuit. The gate electrode of the MOS tube MP1 is connected to the gate electrode of the MOS tube MP2. The source electrode of the MOS tube MP2 is connected to the error amplifier. The drain electrodes of the MOS tube MP1 and the MOS tube MP2 are both connected to the output terminal Vout. The positive terminals of the resistor Ra, the capacitor CL, and the resistor RL are all connected to the output terminal Vout. The negative terminal of the capacitor CL is connected to the positive terminal of the resistor Resr. The negative terminals of the resistor Rb, the resistor Resr, and the resistor RL are all connected to the ground.

[0010] In the low-noise high-PSRR LDO circuit, the output noise of the bandgap reference and the error amplifier EA is filtered out through the filter circuit and the PSRR enhancement circuit, while avoiding transmission of small signal ripple of the power supply to the output end, so as to realize high PSRR of the LDO; and the MOS tube MP2 is used to realize overcurrent protection.

[0011] In the low-noise high-PSRR LDO circuit, the bandgap reference circuit comprises the triodes Q1-Q13, the capacitors C1-C2, the resistors R1-R9, the MOS tubes M1-M8, a Schmitt trigger and an inverter;

[0012] Wherein, the base of the triode Q1, Q2 and the emitter of the triode Q10 and the positive end of the resistor R3 are connected, the emitter of the triode Q1 and the positive end of the resistor R1 are connected, the emitter of the triode Q2 and the negative end of the resistor R1 and the positive end of the resistor R2 are connected, the negative end of the resistor R3 and the output end VREF of the bandgap reference circuit, the positive end of the resistor R4 are connected, the negative end of the resistor R4 and the negative end of the resistor R2 are connected with the ground; the collector of the triode Q1 and the collector, base of the triode Q3 and the base of the triode Q4 are connected, the collector of the triode Q2 and the collector of the triode Q4, the base of the triode Q9, the positive end of the capacitor C1 are connected, the negative end of the capacitor C1 is connected with the ground, the base of the triode Q10 and the emitter of the triode Q3, the emitter of the triode Q4, the emitter of the triode Q9, the collector of the triode Q11 are connected, the power supply and the collector of the triode Q10, the positive end of the capacitor C2, the emitter of the triode Q11, the drain end of the MOS tube M1, the emitter of the triode Q12, the source end and the drain end of the MOS tube M2, the source end of the MOS tube M3, the source end of the MOS tube M4, the source end of the MOS tube M5 are connected, the negative end of the capacitor C2 and the base, the collector of the triode Q11, the base and the collector of the triode Q12, the collector of the triode Q6, the gate end of the MOS tube M2 are connected, the collector of the triode Q9 and the collector and the base of the triode Q5, the base of the triode Q6, the negative end of the resistor R5, the gate end of the MOS tube M1 are connected, the positive end of the resistor R5 and the source end of the MOS tube M1 are connected, the emitter of the triode Q5 and the collector of the triode Q7, the base of the triode Q8 are connected, the emitter of the triode Q6 and the collector of the triode Q8, the base of the triode Q7 are connected, the emitter of the triode Q8 and the positive end of the resistor R6 are connected, the emitter of the triode Q7 and the negative end of the resistor R6 are connected with the ground, the gate end of the MOS tube M3 and the drain end of the MOS tube M3, the drain end of the MOS tube M6, the gate end of the MOS tube M4, the gate end of the MOS tube M5 are connected, the source end of the MOS tube M6 and the positive end of the resistor R7 are connected, the gate end of the MOS tube M6 and the negative end of the resistor R7, the drain end of the MOS tube M7 are connected, the source end of the MOS tube M7 is connected with the ground, the drain end of the MOS tube M4 and the positive end of the resistor R8, the base of the triode Q13 are connected, the negative end of the resistor R8 and the positive end of the resistor R9, the drain end of the MOS tube M8 are connected, the drain end of the MOS tube M5 and the collector of the triode Q13, the input end of the Schmidt trigger are connected, the emitter of the triode Q13 and the source end of the MOS tube M8, the negative end of the resistor R9 are connected and connected with the ground, the gate end of the MOS tube M8 and the output of the Schmidt trigger, the input of the inverter are connected.

[0013] In the above low noise high PSRR LDO circuit, the error amplifier EA includes triodes Q14-Q17, resistors R10-R11 and MOS tubes M9-M36;

[0014] MOS transistor M10 gate end connected with band gap reference voltage, MOS transistor M9 gate end connected with feedback voltage, MOS transistor M11 drain end connected with MOS transistor M9 source end, MOS transistor M10 source end, MOS transistor M9 drain end connected with MOS transistor M20 source end, MOS transistor M21 drain end, MOS transistor M10 drain end connected with MOS transistor M18 source end, MOS transistor M19 drain end, MOS transistor M20 drain end connected with MOS transistor M32 drain end, MOS transistor M34 gate end, MOS transistor M18 drain end connected with MOS transistor M33 drain end, MOS transistor M35 gate end, MOS transistor M32 gate end connected with MOS transistor M31 gate end, MOS transistor M33 gate end, MOS transistor M34 source end, MOS transistor M16 drain end, MOS transistor M16 source end connected with MOS transistor M17 drain end, MOS transistor M35 source end connected with MOS transistor M14 drain end, transistor Q16 emitter, transistor Q17 emitter and error amplifier output end, MOS transistor M14 source end connected with MOS transistor M15 drain end, transistor Q16 base connected with MOS transistor M30 gate end, MOS transistor M26 drain end, transistor Q15 collector, transistor Q17 base connected with MOS transistor M12 drain end, MOS transistor M36 drain end, MOS transistor M36 source end connected with MOS transistor M22 drain end, MOS transistor M22 source end connected with MOS transistor M23 drain end, MOS transistor M11 gate end connected with MOS transistor M12 gate end, MOS transistor M13 gate end, MOS transistor M13 drain end connected with MOS transistor M24 drain end, MOS transistor M24 source end connected with MOS transistor M25 drain end, MOS transistor M31 drain end connected with MOS transistor M30 drain end, MOS transistor M26 source end connected with MOS transistor M27 drain end, transistor Q15 base connected with transistor Q14 base, transistor Q14 collector, MOS transistor M28 drain end, MOS transistor M28 source end connected with MOS transistor M29 drain end, transistor Q15 emitter connected with resistor R11 negative end, transistor Q14 emitter connected with resistor R10 negative end, MOS transistor M14 gate end connected with MOS transistor M16 gate end, MOS transistor M18 gate end, MOS transistor M20 gate end, MOS transistor M22 gate end, MOS transistor M24 gate end, MOS transistor M26 gate end, MOS transistor M28 gate end constitute current mirror structure, MOS transistor M15 gate end connected with MOS transistor M17 gate end, MOS transistor M19 gate end, MOS transistor M21 gate end, MOS transistor M23 gate end, MOS transistor M25 gate end, MOS transistor M27 gate end, MOS transistor M29 gate end constitute current mirror structure,The source end of the MOS transistor M15 is connected to the ground together with the source end of the MOS transistor M17, the source end of the MOS transistor M19, the source end of the MOS transistor M21, the source end of the MOS transistor M23, the source end of the MOS transistor M25, the source end of the MOS transistor M27, and the source end of the MOS transistor M29; the positive end of the resistor R10 is connected to the positive end of the resistor R11, the source end of the MOS transistor M31, the source end of the MOS transistor M13, the source end of the MOS transistor M12, the source end of the MOS transistor M11, the source end of the MOS transistor M32, the source end of the MOS transistor M33, the drain end of the MOS transistor M34, the drain end of the MOS transistor M35, the collector of the triode Q16, and the collector of the triode Q17.

[0015] In the low-noise high-PSRR LDO circuit, the error amplifier circuit adopts a folded common-source and common-gate operational amplifier structure, which ensures the LDO loop gain and obtains a larger output voltage swing; the PMOS transistors M9 and M10 constitute an input pair, the MOS transistors M11, M12 and M13 provide appropriate bias for the input pair, and compare the reference voltage VREF and the feedback voltage VFB; the bias transistor M36 works in the saturation region to adjust the starting voltage point of the LDO circuit; the NMOS transistors M14-M29 constitute a current mirror to provide bias for the overall structure of the error amplifier, and the width-length ratios of the transistors are all inverse ratios to reduce the static current of the error amplifier and the power consumption of the LDO; the bipolar transistors Q14 and Q15 and the resistors R10 and R11 constitute an overcurrent monitoring circuit to provide overcurrent protection for the LDO and prevent the circuit from being damaged due to excessively high load current.

[0016] In the low-noise high-PSRR LDO circuit, the filter circuit includes the capacitor C3 and the MOS transistors M37-M39.

[0017] The source end of the MOS transistor M37 is connected to the input signal end and the source end of the MOS transistor M38, the gate end of the MOS transistor M37 is connected to the gate end of the MOS transistor M38, the drain end of the MOS transistor M38 and the drain end of the MOS transistor M39, the drain end of the MOS transistor M37 is connected to the output signal end and the positive end of the capacitor C3, and the gate end of the MOS transistor M39 is connected to the negative end of the capacitor C3 and the source end of the MOS transistor M39 is connected to the ground.

[0018] In the low-noise high-PSRR LDO circuit, the filter circuit uses the MOS transistors M37 and M38 to constitute an equivalent active resistor, and C3 is a filter capacitor; M39 provides a small bias current of 1nA for the drain end of M38, so that the gate-source voltage of M38 is equal, and the gate-source voltage of M37 is consistent with that of M38; the size of M38 is much larger than that of M37, so that M37 works in the linear region and is equivalent to a large resistor, which together with the filter capacitor constitutes a low-pass filter to filter out the high-frequency noise of the LDO.

[0019] In the low-noise high-PSRR LDO circuit, the PSRR enhancement circuit comprises MOS tubes M40-M42.

[0020] The drain of the MOS tube M40 is connected with the gate of the power adjusting tube, the gate of the MOS tube M40 is connected with the gate of the MOS tube M41, the drain of the MOS tube M41, and the drain of the MOS tube M42, the gate of the MOS tube M42 is biased by the bandgap reference, the source of the MOS tube M40 and the source of the MOS tube M41 are connected with the input power supply end, and the source of the MOS tube M42 is connected with the ground.

[0021] In the low-noise high-PSRR LDO circuit, the PSRR enhancement circuit introduces the common-gate MOS tube M40 relative to the power supply on the basis of improving the output driving capability of the buffer stage BUF, transmits the signal to the gate of the adjusting tube MP1, copies the power supply ripple to adaptively inject the gate of the power adjusting tube by adjusting the width-length ratio of the M40 and the buffer stage, reduces the influence of the power supply ripple on the gate-source voltage of the adjusting tube, and improves the PSRR of the LDO in the middle and high frequency bands.

[0022] In the low-noise high-PSRR LDO circuit, the working temperature range of the LDO circuit is -40-85 DEG C, and the working range of the power supply voltage is 2.5-5V; under the normal working condition of the LDO circuit, the bandgap reference circuit module provides the accurate zero-temperature drift reference voltage required by the error amplifier EA; due to the virtual short and virtual open characteristics of the operational amplifier, the voltage division of the resistors Ra and Rb in the feedback resistor network is equal to the reference voltage of the reference, and after filtering the noise of the bandgap reference circuit and the error amplifier EA, the filtered voltage is connected with the gate of the power adjusting tube, thereby forming a negative feedback loop and ensuring that the output end Vout stably outputs a 1.5V voltage.

[0023] Compared with the prior art, the present application has the following beneficial effects:

[0024] (1) The bandgap reference circuit of the present application is used to generate the zero-temperature drift reference voltage required by the LDO, has lower noise, and provides bias for the PSRR enhancement circuit;

[0025] (2) The error amplifier of the present application is used to compare the feedback voltage and the reference voltage, and the difference is output to the RC low-pass filter circuit in the next stage to filter the noise of the bandgap reference and the error amplifier, and then the second-stage buffer structure is used to further adjust the gate voltage of the power adjusting tube, so that a good gain is obtained while the LDO output voltage is stabilized;

[0026] (3) The PSRR enhancement circuit of the present application copies the power supply ripple to the gate of the power adjusting tube, thereby reducing the influence of the power supply ripple on the gate-source voltage of the power adjusting tube and improving the PSRR of the LDO;

[0027] (4) The LDO circuit structure of the present application introduces an RC filter circuit at the back end of the error amplifier, effectively reducing the noise of the bandgap reference circuit and the error amplifier, and using MOS devices to form the resistance of the filter circuit, obtaining a high resistance value while reducing the chip layout area;

[0028] (5) The LDO circuit of the present application introduces a PSRR enhancement circuit between the gate and source of the power adjustment tube, improving the PSRR of the LDO;

[0029] (6) The error amplifier, buffer stage and power stage circuit of the present application form a feedback loop, which stabilizes the output voltage by adjusting the gate voltage of the power adjustment tube, and monitors the load current through the sampling tube. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic diagram of the bandgap reference circuit of the present application;

[0031] Figure 2 is a schematic diagram of the bandgap reference circuit of the present application;

[0032] Figure 3 is a schematic diagram of the error amplifier EA of the present application;

[0033] Figure 4 is a schematic diagram of the filter circuit of the present application;

[0034] Figure 5 is a schematic diagram of the PSRR enhancement circuit of the present application;

[0035] Figure 6 is a circuit noise performance curve of the present application;

[0036] Figure 7 is a circuit PSRR performance curve of the present application. DETAILED DESCRIPTION

[0037] The present application will be further described below in conjunction with examples.

[0038] In view of the problem of unsatisfactory PSRR of the LDO circuit, a PSRR enhancement circuit is introduced at the gate of the power adjustment tube, which copies the power supply ripple to the gate of the power adjustment tube, thereby reducing the influence of the gate-source voltage of the adjustment tube on the power supply ripple. Therefore, the power supply ripple will not be coupled to the output through the path of the adjustment tube, thereby improving the PSRR of the LDO in the medium and high frequency bands.

[0039] The low-noise high-PSRR LDO circuit, as shown in Figure 1 specifically includes a bandgap reference circuit, an error amplifier EA, a filter circuit, a buffer stage BUF, a PSRR enhancement circuit, a MOS tube MP1, a MOS tube MP2, a resistor Ra, a resistor Rb, a capacitor CL, a resistor RL and a resistor Resr.

[0040] The output end VREF of the bandgap reference circuit module is connected to one of the input ends of the error amplifier EA; the other input end of the error amplifier EA is connected to the negative end of the resistor Ra and the positive end of the resistor Rb; the output end of the error amplifier EA is connected to the filter circuit; the power supply end of the error amplifier EA, the power supply end of the buffer stage BUF, the power supply end of the PSRR enhancement circuit and the source of the MOS tube MP1 are all connected to the input Vin; the output of the filter circuit is connected to the gate of the MOS tube MP1 and the PSRR enhancement circuit after passing through the BUF; the bias of the PSRR enhancement circuit is provided by the bandgap reference circuit; the gate of the MOS tube MP1 is connected to the gate of the MOS tube MP2; the source of the MOS tube MP2 is connected to the error amplifier; the drain of the MOS tube MP1 and the drain of the MOS tube MP2 are both connected to the output end Vout; the positive end of the resistor Ra, the positive end of the capacitor CL and the positive end of the resistor RL are all connected to the output end Vout; the negative end of the capacitor CL is connected to the positive end of the resistor Resr, and the negative end of the resistor Rb, the negative end of the resistor Resr and the negative end of the resistor RL are all connected to the ground.

[0041] Through the filter circuit and the PSRR enhancement circuit, the output noise of the bandgap reference and the error amplifier EA is filtered out, at the same time, the small signal ripple of the power supply is avoided from being transmitted to the output end, so as to realize high PSRR of the LDO; the overcurrent protection is realized through the MOS tube MP2.

[0042] As shown in Figure 2 , the bandgap reference circuit comprises the triodes Q1-Q13, the capacitors C1-C2, the resistors R1-R9, the MOS tubes M1-M8, a Schmidt trigger and an inverter;

[0043] The base of the triode Q1 and Q2 is connected with the emitter of the triode Q10 and the positive terminal of the resistor R3, the emitter of the triode Q1 is connected with the positive terminal of the resistor R1, the emitter of the triode Q2 is connected with the negative terminal of the resistor R1 and the positive terminal of the resistor R2, the negative terminal of the resistor R3 is connected with the output terminal VREF of the bandgap reference circuit and the positive terminal of the resistor R4, the negative terminal of the resistor R4 and the negative terminal of the resistor R2 are connected with the ground; the collector of the triode Q1 is connected with the collector and base of the triode Q3 and the base of the triode Q4, the collector of the triode Q2 is connected with the collector of the triode Q4, the base of the triode Q9 and the positive terminal of the capacitor C1, the negative terminal of the capacitor C1 is connected with the ground, the base of the triode Q10 is connected with the emitter of the triode Q3, the emitter of the triode Q4, the emitter of the triode Q9 and the collector of the triode Q11, the power supply is connected with the collector of the triode Q10, the positive terminal of the capacitor C2, the emitter of the triode Q11, the drain of the MOS transistor M1, the emitter of the triode Q12, the source and drain of the MOS transistor M2, the source of the MOS transistor M3, the source of the MOS transistor M4 and the source of the MOS transistor M5, the negative terminal of the capacitor C2 is connected with the base of the triode Q11, the base and collector of the triode Q12, the collector of the triode Q6 and the gate of the MOS transistor M2, the collector of the triode Q9 is connected with the collector and base of the triode Q5, the base of the triode Q6, the negative terminal of the resistor R5 and the gate of the MOS transistor M1, the positive terminal of the resistor R5 is connected with the source of the MOS transistor M1, the emitter of the triode Q5 is connected with the collector of the triode Q7 and the base of the triode Q8, the emitter of the triode Q6 is connected with the collector of the triode Q8 and the base of the triode Q7, the emitter of the triode Q8 is connected with the positive terminal of the resistor R6, the emitter of the triode Q7 and the negative terminal of the resistor R6 are connected with the ground, the gate of the MOS transistor M3 is connected with the drain of the MOS transistor M3, the drain of the MOS transistor M6, the gate of the MOS transistor M4 and the gate of the MOS transistor M5, the source of the MOS transistor M6 is connected with the positive terminal of the resistor R7, the gate of the MOS transistor M6 is connected with the negative terminal of the resistor R7 and the drain of the MOS transistor M7, the source of the MOS transistor M7 is connected with the ground, the drain of the MOS transistor M4 is connected with the positive terminal of the resistor R8 and the base of the triode Q13, the negative terminal of the resistor R8 is connected with the positive terminal of the resistor R9 and the drain of the MOS transistor M8, the drain of the MOS transistor M5 is connected with the collector of the triode Q13 and the input of the Schmitt trigger, the emitter of the triode Q13 is connected with the source of the MOS transistor M8 and the negative terminal of the resistor R9 and is connected with the ground, the gate of the MOS transistor M8 is connected with the output of the Schmitt trigger and the input of the inverter.

[0044] As shown in Figure 3 , the error amplifier EA includes triodes Q14-Q17, resistors R10-R11 and MOS transistors M9-M36;

[0045] MOS transistor M10 gate end connected with band gap reference voltage, MOS transistor M9 gate end connected with feedback voltage, MOS transistor M11 drain end connected with MOS transistor M9 source end, MOS transistor M10 source end, MOS transistor M9 drain end connected with MOS transistor M20 source end, MOS transistor M21 drain end, MOS transistor M10 drain end connected with MOS transistor M18 source end, MOS transistor M19 drain end, MOS transistor M20 drain end connected with MOS transistor M32 drain end, MOS transistor M34 gate end, MOS transistor M18 drain end connected with MOS transistor M33 drain end, MOS transistor M35 gate end, MOS transistor M32 gate end connected with MOS transistor M31 gate end, MOS transistor M33 gate end, MOS transistor M34 source end, MOS transistor M16 drain end, MOS transistor M16 source end connected with MOS transistor M17 drain end, MOS transistor M35 source end connected with MOS transistor M14 drain end, transistor Q16 emitter, transistor Q17 emitter and error amplifier output end, MOS transistor M14 source end connected with MOS transistor M15 drain end, transistor Q16 base connected with MOS transistor M30 gate end, MOS transistor M26 drain end, transistor Q15 collector, transistor Q17 base connected with MOS transistor M12 drain end, MOS transistor M36 drain end, MOS transistor M36 source end connected with MOS transistor M22 drain end, MOS transistor M22 source end connected with MOS transistor M23 drain end, MOS transistor M11 gate end connected with MOS transistor M12 gate end, MOS transistor M13 gate end, MOS transistor M13 drain end connected with MOS transistor M24 drain end, MOS transistor M24 source end connected with MOS transistor M25 drain end, MOS transistor M31 drain end connected with MOS transistor M30 drain end, MOS transistor M26 source end connected with MOS transistor M27 drain end, transistor Q15 base connected with transistor Q14 base, transistor Q14 collector, MOS transistor M28 drain end, MOS transistor M28 source end connected with MOS transistor M29 drain end, transistor Q15 emitter connected with resistor R11 negative end, transistor Q14 emitter connected with resistor R10 negative end, MOS transistor M14 gate end connected with MOS transistor M16 gate end, MOS transistor M18 gate end, MOS transistor M20 gate end, MOS transistor M22 gate end, MOS transistor M24 gate end, MOS transistor M26 gate end, MOS transistor M28 gate end constitute current mirror structure, MOS transistor M15 gate end connected with MOS transistor M17 gate end, MOS transistor M19 gate end, MOS transistor M21 gate end, MOS transistor M23 gate end, MOS transistor M25 gate end, MOS transistor M27 gate end, MOS transistor M29 gate end constitute current mirror structure,The source end of the MOS transistor M15 is connected to the ground together with the source end of the MOS transistor M17, the source end of the MOS transistor M19, the source end of the MOS transistor M21, the source end of the MOS transistor M23, the source end of the MOS transistor M25, the source end of the MOS transistor M27, and the source end of the MOS transistor M29; the positive end of the resistor R10 is connected to the positive end of the resistor R11, the source end of the MOS transistor M31, the source end of the MOS transistor M13, the source end of the MOS transistor M12, the source end of the MOS transistor M11, the source end of the MOS transistor M32, the source end of the MOS transistor M33, the drain end of the MOS transistor M34, the drain end of the MOS transistor M35, the collector of the triode Q16, and the collector of the triode Q17.

[0046] The error amplifier circuit adopts a folded common-source and common-gate operational amplifier structure, ensures the LDO loop gain, and obtains a large output voltage swing; the PMOS transistors M9 and M10 constitute an input pair, the MOS transistors M11, M12 and M13 provide appropriate bias for the input pair, and compare the reference voltage VREF and the feedback voltage VFB; the bias transistor M36 works in the saturation region to adjust the starting voltage point of the LDO circuit; the NMOS transistors M14-M29 constitute a current mirror to provide bias for the overall structure of the error amplifier, and the width-length ratios of the transistors are all inverse ratios to reduce the static current of the error amplifier and the power consumption of the LDO; the bipolar transistors Q14 and Q15 and the resistors R10 and R11 constitute an overcurrent monitoring circuit to provide overcurrent protection for the LDO and prevent the circuit from being damaged due to excessively high load current.

[0047] As shown in Figure 4 The filter circuit includes the capacitor C3 and the MOS transistors M37-M39; the source end of the MOS transistor M37 is connected to the input signal end and the source end of the MOS transistor M38, the gate end of the MOS transistor M37 is connected to the gate end of the MOS transistor M38, the drain end of the MOS transistor M38 and the drain end of the MOS transistor M39, the drain end of the MOS transistor M37 is connected to the output signal end and the positive end of the capacitor C3, and the gate end of the MOS transistor M39 is connected to the negative end of the capacitor C3 and the source end of the MOS transistor M39 is connected to the ground.

[0048] The filter circuit uses the MOS transistors M37 and M38 to constitute an equivalent active resistor, and the C3 is a filter capacitor; the MOS transistor M39 provides a small bias current of 1nA for the drain end of the MOS transistor M38, so that the gate-source voltage of the MOS transistor M38 is equal to that of the MOS transistor M37, and the gate-source voltage of the MOS transistor M37 is consistent with that of the MOS transistor M38; the size of the MOS transistor M38 is much larger than that of the MOS transistor M37, so that the MOS transistor M37 works in the linear region and is equivalent to a large resistor, and together with the filter capacitor, constitutes a low-pass filter to filter out the high-frequency noise of the LDO.

[0049] As shown in Figure 5As shown, the PSRR enhancement circuit includes MOSFETs M40-M42; wherein, the drain of MOSFET M40 is connected to the gate of the power regulation transistor, the gate of MOSFET M40 is connected to the gate of MOSFET M41, the drain of MOSFET M41, and the drain of MOSFET M42, the gate of MOSFET M42 is biased by a bandgap reference, the source of MOSFET M40 and the source of MOSFET M41 are connected to the input power supply, and the source of MOSFET M42 is connected to ground.

[0050] The PSRR enhancement circuit, based on the improved output drive capability of the buffer stage BUF, introduces a common-gate MOSFET M40 relative to the power supply to transmit the signal to the gate of the regulating transistor MP1. By adjusting the width-to-length ratio of M40 and the buffer stage, the power supply ripple is replicated and adaptively injected into the gate of the power regulating transistor, reducing the influence of power supply ripple on the gate-source voltage of the regulating transistor and improving the PSRR of the LDO in the mid-to-high frequency range.

[0051] The LDO circuit operates in a temperature range of -40 to 85°C and a power supply voltage range of 2.5 to 5V. Under normal operating conditions, the bandgap reference circuit module provides the precise zero-temperature drift reference voltage required by the error amplifier EA. Due to the virtual short and virtual open characteristics of the op-amp, the voltage division of resistors Ra and Rb in the feedback resistor network is equal to the reference voltage. After the noise from the bandgap reference circuit and the error amplifier circuit EA is filtered out by the filter circuit, it is connected to the gate of the power adjustment transistor to form a negative feedback loop, ensuring that the output Vout outputs a stable 1.5V voltage.

[0052] In use, the low-noise, high-PSRR LDO circuit proposed in this invention outputs a noise voltage as follows: Figure 6 As shown, the noise level is 0.3732 μV / √Hz at 1 kHz, and as low as 30.7 μVRMS in the 10 Hz–100 kHz frequency range. PSRR is as follows... Figure 7 As shown, the linear regulation is up to 83.8dB@1kHz, up to 80.2dB@10kHz, and up to 42dB@100kHz. When the LDO's load capacitance is designed to be 4.7μF and the load resistance to be 3Ω, the LDO loop can operate stably, and the load current can reach 500mA. At room temperature (25℃), the proposed LDO circuit has a linear regulation of 0.2% / V.

[0053] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A low noise high PSRR LDO circuit, characterized in that: The bandgap reference circuit, an error amplifier EA, a filter circuit, a buffer stage BUF, a PSRR enhancement circuit, a MOS transistor MP1, a MOS transistor MP2, a resistor Ra, a resistor Rb, a capacitor CL, a resistor RL and a resistor Resr are included. The output end VREF of the bandgap reference circuit module is connected to one input end of the error amplifier EA; the other input end of the error amplifier EA is connected to the negative end of the resistor Ra and the positive end of the resistor Rb; the output end of the error amplifier EA is connected to the filter circuit; the power supply end of the error amplifier EA, the power supply end of the buffer stage BUF, the power supply end of the PSRR enhancement circuit and the source of the MOS transistor MP1 are all connected to the input Vin; the output of the filter circuit is connected to the gate of the MOS transistor MP1 and the PSRR enhancement circuit after passing through the BUF; the bias of the PSRR enhancement circuit is provided by the bandgap reference circuit; the gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2; the source of the MOS transistor MP2 is connected to the error amplifier; the drain of the MOS transistor MP1 and the drain of the MOS transistor MP2 are both connected to the output end Vout; the positive end of the resistor Ra, the positive end of the capacitor CL and the positive end of the resistor RL are all connected to the output end Vout; the negative end of the capacitor CL is connected to the positive end of the resistor Resr, and the negative end of the resistor Rb, the negative end of the resistor Resr and the negative end of the resistor RL are all connected to the ground; The bandgap reference circuit includes transistors Q1-Q13, capacitors C1-C2, resistors R1-R9, MOS transistors M1-M8, a Schmitt trigger and an inverter. The base of the triode Q1 and Q2 is connected with the emitter of the triode Q10 and the positive end of the resistor R3, the emitter of the triode Q1 is connected with the positive end of the resistor R1, the emitter of the triode Q2 is connected with the negative end of the resistor R1 and the positive end of the resistor R2, the negative end of the resistor R3 is connected with the output end VREF of the bandgap reference circuit and the positive end of the resistor R4, the negative end of the resistor R4 and the negative end of the resistor R2 are connected with the ground; the collector of the triode Q1 is connected with the collector and base of the triode Q3 and the base of the triode Q4, the collector of the triode Q2 is connected with the collector of the triode Q4, the base of the triode Q9 and the positive end of the capacitor C1, the negative end of the capacitor C1 is connected with the ground, the base of the triode Q10 is connected with the emitter of the triode Q3, the emitter of the triode Q4, the emitter of the triode Q9 and the collector of the triode Q11, the power supply is connected with the collector of the triode Q10, the positive end of the capacitor C2, the emitter of the triode Q11, the drain end of the MOS transistor M1, the emitter of the triode Q12, the source end and the drain end of the MOS transistor M2, the source end of the MOS transistor M3, the source end of the MOS transistor M4 and the source end of the MOS transistor M5, the negative end of the capacitor C2 is connected with the base of the triode Q11, the base and the collector of the triode Q12, the collector of the triode Q6 and the gate end of the MOS transistor M2, the collector of the triode Q9 is connected with the collector and the base of the triode Q5, the base of the triode Q6, the negative end of the resistor R5 and the gate end of the MOS transistor M1, the positive end of the resistor R5 is connected with the source end of the MOS transistor M1, the emitter of the triode Q5 is connected with the collector of the triode Q7 and the base of the triode Q8, the emitter of the triode Q6 is connected with the collector of the triode Q8 and the base of the triode Q7, the emitter of the triode Q8 is connected with the positive end of the resistor R6, the emitter of the triode Q7 and the negative end of the resistor R6 are connected with the ground, the gate end of the MOS transistor M3 is connected with the drain end of the MOS transistor M3, the drain end of the MOS transistor M6, the gate end of the MOS transistor M4 and the gate end of the MOS transistor M5, the source end of the MOS transistor M6 is connected with the positive end of the resistor R7, the gate end of the MOS transistor M6 is connected with the negative end of the resistor R7 and the drain end of the MOS transistor M7, the source end of the MOS transistor M7 is connected with the ground, the drain end of the MOS transistor M4 is connected with the positive end of the resistor R8 and the base of the triode Q13, the negative end of the resistor R8 is connected with the positive end of the resistor R9 and the drain end of the MOS transistor M8, the drain end of the MOS transistor M5 is connected with the collector of the triode Q13 and the input end of the Schmidt trigger, the emitter of the triode Q13 is connected with the source end of the MOS transistor M8 and the negative end of the resistor R9 and is connected with the ground, the gate end of the MOS transistor M8 is connected with the output of the Schmidt trigger and the input of the inverter.

2. The low noise high PSRR LDO circuit of claim 1, wherein: The output noise of the bandgap reference and the error amplifier EA is filtered out through the filter circuit and the PSRR enhancement circuit, at the same time, the small signal ripple of the power supply is avoided to be transmitted to the output end, so that the high PSRR of the LDO is realized; the overcurrent protection is realized through the MOS transistor MP2.

3. The low noise high PSRR LDO circuit of claim 1, wherein: The error amplifier EA comprises triodes Q14-Q17, resistors R10-R11 and MOS tubes M9-M36; MOS transistor M10 gate end connected with band gap reference voltage, MOS transistor M9 gate end connected with feedback voltage, MOS transistor M11 drain end connected with MOS transistor M9 source end, MOS transistor M10 source end, MOS transistor M9 drain end connected with MOS transistor M20 source end, MOS transistor M21 drain end, MOS transistor M10 drain end connected with MOS transistor M18 source end, MOS transistor M19 drain end, MOS transistor M20 drain end connected with MOS transistor M32 drain end, MOS transistor M34 gate end, MOS transistor M18 drain end connected with MOS transistor M33 drain end, MOS transistor M35 gate end, MOS transistor M32 gate end connected with MOS transistor M31 gate end, MOS transistor M33 gate end, MOS transistor M34 source end, MOS transistor M16 drain end, MOS transistor M16 source end connected with MOS transistor M17 drain end, MOS transistor M35 source end connected with MOS transistor M14 drain end, transistor Q16 emitter, transistor Q17 emitter and error amplifier output end, MOS transistor M14 source end connected with MOS transistor M15 drain end, transistor Q16 base connected with MOS transistor M30 gate end, MOS transistor M26 drain end, transistor Q15 collector, transistor Q17 base connected with MOS transistor M12 drain end, MOS transistor M36 drain end, MOS transistor M36 source end connected with MOS transistor M22 drain end, MOS transistor M22 source end connected with MOS transistor M23 drain end, MOS transistor M11 gate end connected with MOS transistor M12 gate end, MOS transistor M13 gate end, MOS transistor M13 drain end connected with MOS transistor M24 drain end, MOS transistor M24 source end connected with MOS transistor M25 drain end, MOS transistor M31 drain end connected with MOS transistor M30 drain end, MOS transistor M26 source end connected with MOS transistor M27 drain end, transistor Q15 base connected with transistor Q14 base, transistor Q14 collector, MOS transistor M28 drain end, MOS transistor M28 source end connected with MOS transistor M29 drain end, transistor Q15 emitter connected with resistor R11 negative end, transistor Q14 emitter connected with resistor R10 negative end, MOS transistor M14 gate end connected with MOS transistor M16 gate end, MOS transistor M18 gate end, MOS transistor M20 gate end, MOS transistor M22 gate end, MOS transistor M24 gate end, MOS transistor M26 gate end, MOS transistor M28 gate end constitute current mirror structure, MOS transistor M15 gate end connected with MOS transistor M17 gate end, MOS transistor M19 gate end, MOS transistor M21 gate end, MOS transistor M23 gate end, MOS transistor M25 gate end, MOS transistor M27 gate end, MOS transistor M29 gate end constitute current mirror structure,The source terminal of the MOS transistor M15 is connected to the ground together with the source terminal of the MOS transistor M17, the source terminal of the MOS transistor M19, the source terminal of the MOS transistor M21, the source terminal of the MOS transistor M23, the source terminal of the MOS transistor M25, the source terminal of the MOS transistor M27, and the source terminal of the MOS transistor M29. The positive terminal of the resistor R10 is connected to the positive terminal of the resistor R11, the source terminal of the MOS transistor M31, the source terminal of the MOS transistor M13, the source terminal of the MOS transistor M12, the source terminal of the MOS transistor M11, the source terminal of the MOS transistor M32, the source terminal of the MOS transistor M33, the drain terminal of the MOS transistor M34, the drain terminal of the MOS transistor M35, the collector terminal of the triode Q16, and the collector terminal of the triode Q17.

4. The low noise high PSRR LDO circuit of claim 3, wherein: The error amplifier circuit adopts a folded common-source and common-gate operational amplifier structure, guarantees the LDO loop gain, and obtains a larger output voltage swing; the PMOS tubes M9 and M10 are used to form an input pair tube, the MOS tubes M11, M12 and M13 provide a suitable bias for the input pair tube, and the reference voltage VREF and the feedback voltage VFB are compared; the bias tube M36 is used to work in a saturation region, and the starting voltage point of the LDO circuit is adjusted; the NMOS tubes M14-M29 are used to form a current mirror, and provide a bias for the overall structure of the error amplifier; the width-length ratios of the tubes are all inverse ratios, so that the static current of the error amplifier is reduced, and the power consumption of the LDO is reduced; the triodes Q14 and Q15 and the resistors R10 and R11 are used to form an overcurrent monitoring circuit, and provide overcurrent protection for the LDO, so as to prevent the circuit from being damaged due to an excessively high load current.

5. The low noise high PSRR LDO circuit of claim 4, wherein: The filter circuit comprises a capacitor C3 and MOS tubes M37-M39; The source end of the MOS tube M37 is connected with an input signal end and the source end of the MOS tube M38, the gate end of the MOS tube M37 is connected with the gate end of the MOS tube M38, the drain end of the MOS tube M38 and the drain end of the MOS tube M39, the drain end of the MOS tube M37 is connected with an output signal end and the positive end of the capacitor C3, and the gate end of the MOS tube M39 is connected with the negative end of the capacitor C3 and the source end of the MOS tube M39 is connected to the ground.

6. The low noise high PSRR LDO circuit of claim 5, wherein: The filter circuit uses the MOS tubes M37 and M38 to form an equivalent active resistor, and the C3 is a filter capacitor; the MOS tube M39 provides a small bias current of 1nA for the drain end of the MOS tube M38, so that the gate-source voltage of the MOS tube M38 is equal, and the gate-source voltage of the MOS tube M37 is consistent with that of the MOS tube M38; the size of the MOS tube M38 is much larger than that of the MOS tube M37, so that the MOS tube M37 works in a linear region and is equivalent to a large resistor, and together with the filter capacitor, forms a low-pass filter to filter the high-frequency noise of the LDO.

7. The low noise high PSRR LDO circuit of claim 6, wherein: The PSRR enhancement circuit comprises MOS tubes M40-M42; The drain end of the MOS tube M40 is connected with the gate end of a power adjusting tube, the gate end of the MOS tube M40 is connected with the gate end of the MOS tube M41, the drain end of the MOS tube M41 and the drain end of the MOS tube M42, the gate end of the MOS tube M42 is biased by a bandgap reference, the source end of the MOS tube M40 and the source end of the MOS tube M41 are connected with an input power supply end, and the source end of the MOS tube M42 is connected with the ground.

8. The low noise high PSRR LDO circuit of claim 7, wherein: On the basis of improving the output driving capability of the buffer stage BUF, the PSRR enhancement circuit introduces the common-gate MOS tube M40 relative to the power supply, transmits a signal to the gate end of the adjusting tube MP1, adjusts the width-length ratios of the M40 and the buffer stage, copies the power supply ripple, makes the power supply ripple adaptively injected into the gate end of the adjusting tube, reduces the influence of the power supply ripple on the gate-source voltage of the adjusting tube, and improves the PSRR of the LDO in the medium and high frequency bands.

9. The low noise high PSRR LDO circuit of claim 8, wherein: The working temperature range of the LDO circuit is -40-85 DEG C, and the power supply voltage working range is 2.5-5V; under the normal working condition of the LDO circuit, the band gap reference circuit module provides the accurate zero temperature drift reference voltage required by the error amplifier EA; due to the virtual short and virtual open characteristics of the operational amplifier, the voltage division of the resistors Ra and Rb in the feedback resistor network is equal to the reference voltage of the reference, after filtering the noise of the band gap reference circuit and the error amplifier circuit EA, connected with the gate of the power regulating tube, a negative feedback loop is formed, and the output end Vout is stably output 1.5V voltage.

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