Storage device and method of operating the same

Abstract

According to an embodiment of the disclosure, a storage device can include a memory device and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command can include: a basic header segment, generally included in a command transmitted between the external host and the memory controller, and including information indicating that the read command is a command for requesting data stored in the memory device; a transaction-specific field including information indicating that the read command is a read command for at least two or more logical addresses; and an additional header segment including information about the at least two or more logical addresses.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0091834, filed on July 13, 2021, and Korean Patent Application No. 10-2022-0035416, filed on March 22, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically, to a storage device and a method of operating the same. Background Technology

[0004] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device is a device that stores data only when power is supplied and loses the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are devices that do not lose data even when power is off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] Embodiments of this disclosure provide a storage device and a method thereof capable of performing read operations on multiple logical addresses.

[0008] According to embodiments of the present disclosure, a storage device may include: a memory device; and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include: a basic header field, typically included in a command transmitted between the external host and the memory controller, and including information indicating that the read command is a command for requesting data stored in the memory device; a transaction-specific field, including information indicating that the read command is a read command for at least two or more logical addresses; and an additional header field, including information about at least two or more logical addresses.

[0009] According to embodiments of this disclosure, a method of operating a storage device, the storage device including a memory device and a memory controller controlling the memory device, the method may include: receiving a read command from an external host and performing a read operation based on information about at least two or more logical addresses, the read command including: a basic header segment, typically included in a command transmitted between the external host and the memory controller and including information indicating a read command for requesting data stored in the memory device; a transaction-specific field including information indicating that the read command is a read command for at least two or more logical addresses; and an additional header segment including information about at least two or more logical addresses.

[0010] According to embodiments of this disclosure, a memory controller controls a memory device. The memory controller may include: a mapped data storage device configured to store mapping information between logical addresses and physical addresses of data stored in the memory device; a read request processor configured to receive a read request from an external host and obtain physical addresses corresponding to at least one or more logical addresses included in the read request; and a read operation controller configured to provide a read command to the memory device for the physical addresses corresponding to the at least one or more logical addresses, wherein the read request may include: a basic header segment, typically included in a request transmitted and received between the external host and the memory controller and including information indicating that the read request is for requesting data stored in the memory device; a transaction-specific field including information indicating that the read request is for at least two or more logical addresses; and an additional header segment including information about the at least two or more logical addresses.

[0011] According to an embodiment of the present disclosure, a method of operating a controller may include: identifying a received message as a read command associated with a logical address group based on a first field of the received message; and controlling a memory device to read data from memory cells that are discontinuously arranged in the memory device and indicated by the respective logical address groups, based on the logical address groups defined in a second field of the message.

[0012] According to embodiments of the present disclosure, a method of operating a host may include: providing a message to a memory system for the memory system to operate in response to the message; and receiving data read from memory cells arranged discontinuously within the memory system as a response to the message, wherein the message includes: a first field indicating that the message is a read command associated with a logical address group; and a second field defining a logical address group indicating the respective memory cells.

[0013] This technology provides a storage device and its operation method capable of performing read operations on multiple logical addresses. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0015] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0016] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram illustrating the structure of a storage block within a storage block.

[0017] Figure 4 This is a diagram illustrating a data communication unit between a host and a memory controller according to an embodiment of the present disclosure.

[0018] Figure 5 This is a diagram illustrating the structure of the basic header segment of a Protocol Unit (PIU) included in a command according to an embodiment of the present disclosure.

[0019] Figure 6 This is a diagram illustrating a command PIU included in a command according to an embodiment of the present disclosure.

[0020] Figure 7 This is a diagram illustrating the structure of the read (6) command descriptor block according to an embodiment of the present disclosure.

[0021] Figure 8 This is a diagram illustrating the structure of the read (10) command descriptor block according to an embodiment of the present disclosure.

[0022] Figure 9 This is a diagram illustrating the structure of the read (16) command descriptor block according to an embodiment of the present disclosure.

[0023] Figure 10 This is a diagram illustrating additional header segments according to embodiments of the present disclosure.

[0024] Figure 11 This is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0025] Figure 12 This is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0026] Figure 13 This is a flowchart illustrating a multi-read operation of a storage device according to an embodiment of the present disclosure.

[0027] Figure 14 This is a flowchart illustrating a normal read operation of a storage device according to an embodiment of the present disclosure.

[0028] Figure 15 This is a diagram illustrating the data provision order of a storage device according to an embodiment of the present disclosure.

[0029] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0030] Figure 17 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0031] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0032] Figure 19 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0033] The specific structural or functional descriptions illustrating embodiments based on the concepts disclosed in this specification are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0034] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 Storage device 50 may include memory device 100 and memory controller 200. Storage device 50 may be a device for storing data under the control of a host 400 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. Optionally, storage device 50 may be a device for storing data under the control of a host 400 that stores high-capacity data in one location (such as a server or data center).

[0036] Storage device 50 can be manufactured as one of various types of storage devices depending on the host interface used as a method of communicating with host 400. For example, storage device 50 can be configured as any of the following types of storage devices: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC and micro MMC, secure digital cards in the form of SD, mini SD and micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-e or PCIe) card-type storage devices, compact flash memory (CF) cards, smart media cards and memory sticks.

[0037] The storage device 50 can be manufactured in any of a variety of packages. For example, the storage device 50 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0038] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0039] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0040] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0041] In embodiments, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a fourth-generation low-power Double Data Rate (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this disclosure, for ease of description, the memory device 100 is referred to as NAND flash memory.

[0042] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access a region in the memory cell array selected by the address. Memory device 100 can perform operations instructed by commands on the region selected by the address. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data stored in the region selected by the address.

[0043] The memory controller 200 can control all operations of the storage device 50.

[0044] When power is supplied to storage device 50, memory controller 200 can run firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can run firmware such as flash translation layer (FTL) to control communication between host 400 and storage device 100.

[0045] In an embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 400 and can convert the LBAs into physical block addresses (PBAs), which indicate the addresses of the memory cells in the memory device 100 where the data will be stored.

[0046] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations according to requests from the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, PBA, and data. During a reading operation, the memory controller 200 can provide the memory device 100 with reading commands and PBA. During an erasing operation, the memory controller 200 can provide the memory device 100 with erasing commands and PBA.

[0047] In this disclosure, the information transmitted and received between the host 400 and the memory controller 200 may be referred to as a request or a command.

[0048] In addition, in this disclosure, the information provided to the memory device 100 by the memory controller 200 may be referred to as a command.

[0049] In this embodiment, the memory controller 200 can independently generate commands, addresses, and data regardless of requests from the host 400, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing programming operations, read operations, and erase operations accompanied by wear leveling, read recycling, garbage collection, etc.

[0050] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling operations on at least two memory devices 100 to overlap.

[0051] The host 400 can communicate with the storage device 50 using at least one of the following communication standards and interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0052] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0053] Reference Figure 2The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0054] Memory cell array 110 includes multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi are connected to address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi are connected to input / output circuitry 140 via column lines CL. In an embodiment, row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, column lines CL may include bit lines.

[0055] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells in the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0056] In this embodiment, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. The peripheral circuitry can drive the memory cell array 110 under the control of control logic 150. The peripheral circuitry can drive the memory cell array 110 to perform programming, reading, and erasing operations.

[0057] Voltage generator 120 is configured to generate multiple operating voltages using an external power supply voltage supplied to memory device 100. Voltage generator 120 operates in response to control of control logic 150.

[0058] In this embodiment, the voltage generator 120 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as the operating voltage of the memory device 100.

[0059] In this embodiment, voltage generator 120 can use an external power supply voltage or an internal power supply voltage to generate multiple operating voltages. Voltage generator 120 can be configured to generate various voltages required in memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0060] Voltage generator 120 may include multiple pumping capacitors that receive an internal power supply voltage to generate multiple operating voltages having various voltage levels, and may generate multiple operating voltages by selectively activating the multiple pumping capacitors in response to control of control logic 150.

[0061] The generated operating voltages can be supplied to the memory cell array 110 through the address decoder 130.

[0062] Address decoder 130 is connected to memory cell array 110 via row line RL. Address decoder 130 is configured to operate in response to control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 selects at least one memory block from BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 can connect input / output circuitry 140 and memory cell array 110 to each other based on the decoded column address.

[0063] For example, address decoder 130 may include components such as row decoder, column decoder, and address buffer.

[0064] Input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to memory cell array 110 via bit lines. During programming operations, data can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0065] During a read operation, the data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0066] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuitry 140. Control logic 150 can operate in response to commands (CMD) transmitted from external devices. Control logic 150 can generate control signals to control peripheral circuitry in response to commands (CMD) and addresses (ADDR).

[0067] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram illustrating the structure of a storage block within a storage block.

[0068] Storage block BLKi is Figure 2 Storage blocks BLK1 to BLKi are storage blocks BLKi.

[0069] Reference Figure 3 Multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs individually, and the source line SL can be connected together to string STs. Since string STs can be configured to be identical to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

[0070] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one or more of the source selection transistor SST and the drain selection transistor DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

[0071] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different string STs can be connected to the source select line SSL, the gates of the drain select transistor DSTs can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different string STs connected to the same word line can be referred to as a page PG. Therefore, the memory block BLKi can include the same number of physical pages PG as word lines WL1 to WL16.

[0072] A memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0073] A memory cell can store two or more data bits. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0074] Figure 4 This is a diagram illustrating a data communication unit between a host and a memory controller according to an embodiment of the present disclosure.

[0075] Reference Figure 4 The host 400 and the memory controller 200 can communicate using data packets called Protocol Information Units (PIUs).

[0076] Depending on the operations to be performed by the host 400 and the memory controller 200, the PIU may include a command PIU, a response PIU, a data output PIU, a data input PIU, and a prepare-to-transmit PIU.

[0077] The command PIU can be a PIU transmitted when the host 400 sends a command to the storage device 50.

[0078] A response PIU can be a PIU transmitted when the storage device 50 provides a response to a command provided by the host 400.

[0079] The data output PIU can be a PIU transmitted when the host 400 provides data to the storage device 50.

[0080] The data input PIU can be a PIU transmitted when the storage device 50 provides data to the host 400.

[0081] A PIU ready for transmission can be transmitted when storage device 50 notifies storage device 50 that it is ready to receive a data output PIU from host 400. A PIU ready for transmission can be transmitted when storage device 50 has sufficient buffer space to store the data provided by host 400.

[0082] The minimum size of a PIU can be 32 bytes, and the maximum size can be 65,600 bytes. Depending on the type, the format of a PIU can have different sizes.

[0083] A PIU may include a basic header field 61, transaction-specific fields 62, an additional header field 63, and a data field 64.

[0084] The basic header segment 61 can be 12 bytes in size. The basic header segment 61 can typically be included in all PIUs.

[0085] Transaction-specific field 62 can be included in byte addresses 12 to 31 of the PIU. Depending on the type of the PIU, transaction-specific field 62 can include dedicated transaction codes.

[0086] An additional header segment 63 can be defined when the Total EHS Length field of the basic header segment 61 has a non-zero value. The additional header segment 63 can begin at byte address 32 of the PIU. When the basic header segment 61 cannot contain sufficient information, the additional header segment 63 can be a region capable of storing additional data.

[0087] Data segment 64 may be included in a data output PIU or a data input PIU, and may not be included in other PIUs.

[0088] In an embodiment, the additional header segment 63 and data segment 64 may not be included in all protocol PIUs, but may be included only in specific PIUs.

[0089] Figure 5 This is a diagram illustrating the structure of the basic header segment of the PIU included in a command according to an embodiment of the present disclosure.

[0090] Reference Figure 5 The basic header segment 61 may include transaction type, flags, logical unit number (LUN), task label, initiator ID, command set type, query function / taskmanagement function (Query Function, TaskManagement.Function), response, status, total extra header segment length (Total EHS Length), device information, and data segment length.

[0091] Depending on the PIU type, the transaction type can have a unique value. Table 1 below shows examples of transaction types based on the PIU type.

[0092] Table 1

[0093]

[0094] Depending on the transaction type, the flag can be a field with different values. A Logical Unit Number (LUN) can be a field indicating the number of the logical unit among the multiple logical units included in the object to be operated on, from which the corresponding operation is performed.

[0095] Depending on the transaction type, task labels can be fields with different values.

[0096] The initiator ID can be a field that identifies who initiated the request to perform the operation. Therefore, the initiator ID can have different values ​​in cases where the host generates the PIU and the storage device generates the PIU.

[0097] The command set type can be a field included in the command PIU and the response PIU. The command set type can also be a field indicating which interface the command supports, such as whether the command is a SCSI command, a UFS command, or a manufacturer-defined command.

[0098] The query function / task management function can be a field input to the PIU, such as a query request, query response, or task management request.

[0099] The response may contain fields indicating whether the requested operation was executed successfully or failed.

[0100] The status can be a field indicating the SCSI status.

[0101] The Total EHS Length can be a field indicating the size of the extra header segments in 32-bit units. The Total EHS Length can be used when the PIU includes extra header segments. The length of an extra header segment can be 4 bytes. The value of the Total EHS Length can be obtained by dividing the total number of bytes in the extra header segments by 4. The maximum size of an extra header segment can be 1024 bytes. When no extra header segments are used, the Total EHS Length can be 0.

[0102] Device information may include information that is only used when performing a specific function.

[0103] The data segment length can be a field that indicates the length of the data segment in the PIU. When the PIU does not include a data segment, the data segment length can be 0.

[0104] Figure 6 This is a diagram illustrating a command PIU included in a command according to an embodiment of the present disclosure.

[0105] Reference Figure 5 and Figure 6 Commands (or command PIU) can include basic header fields, transaction-specific fields, and additional header fields.

[0106] Basic header fields are typically included in commands transmitted or received between the host and the memory controller. Additionally, the basic header fields included in a command may include information indicating the command. For example, the basic header fields included in a read command may include information indicating the read command itself. That is, because... Figure 6 The situation corresponds to the command PIU included in the command, therefore the transaction type can be 00 0001b. Furthermore, according to embodiments of this disclosure, since... Figure 6 The command PIU includes an additional header segment, so the total EHS length corresponding to the byte address 8 in the fields included in the basic header segment can have a non-zero value. For example, the total EHS length can be the value obtained by dividing the total number of bytes of logical block address information of the region to be read by 4 during multiple read operations.

[0107] Transaction-specific fields may include multiple Command Descriptor Blocks (CDBs). CDBs can include information about various commands and addresses, depending on their type. CDBs can be based on various communication standards or interfaces such as: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM). In an embodiment, when... Figure 6 The command is the read command, Figure 6 The transaction-specific fields can include reading the CDB.

[0108] Figure 6 The additional header segments included in the command may include information about at least two or more logical addresses provided by host 400.

[0109] In a normal read operation, the host 400 provides the memory controller 200 with information about the starting logical block address and its corresponding transfer length, thereby performing a read operation on the region from the starting logical block address to the logical block address according to the transfer length. A multiple read operation, which involves performing read operations on at least two or more logical addresses, refers to the simultaneous reading of multiple non-contiguous logical addresses. Therefore, during a multiple read operation, the information about at least two or more logical addresses may include multiple starting logical block addresses and information about the transfer length corresponding to each of those starting logical block addresses. The memory controller 200 can simultaneously read multiple non-contiguous logical addresses by receiving such information from the host 400.

[0110] In an embodiment, a single logical address information entry, including information about the starting logical block address and the transmission length corresponding to that starting logical block address, can be 8 bytes in size. Accordingly, in the case of multiple read operations, information about at least two or more logical addresses can be sequentially set in 8-byte increments in an additional header segment, but the size or setting method of the logical address information is not limited thereto.

[0111] Figures 7 to 9 This is a diagram illustrating the reading of a CDB according to an embodiment of the present disclosure. Figures 7 to 9 These can be the read (6) command CDB, the read (10) command CDB, and the read (16) command CDB, respectively.

[0112] Reference Figures 6 to 9 Reading the CDB can be included in the transaction-specific fields of the read command. For example, reading the CDB can include bytes 0 to 9. The columns of the CDB represent each bit in each byte of the CDB. For example, each byte can include bits 0 to 7. Bits 0 to 7 of byte 0 of the CDB represent the opcode. For example, the opcode of the read command could be 08h(read(6) command, Figure 7 ), 28h (read (10) command, Figure 8 ) or 88h (read (16) command, Figure 9 ).

[0113] In the following description, as an example, Figure 8 , Figure 8 This is the read CDB associated with the read (10) command. In the case of the read (10) command, bit 0 of the first byte 1 of the CDB can be omitted (deprecated). Bit 1 of the first byte 1 can indicate FUA_NV. Bit 2 of the first byte 1 can be reserved. Bit 3 of the first byte 1 can indicate Forced Unit Access (FUA). FUA can indicate whether or not the data cache is used. Bit 4 of the first byte 1 indicates Disable Page Out (DPO). DPO can indicate how to set the reservation priority. Bits 5 to 7 of the first byte 1 can be RDPROTECT and can have the value "000b". Bits 2 to 5 of the second to fifth bytes of the read (10) command CDB can indicate the logical address (LA). The logical address LA can include the most significant bit MSB to the least significant bit LSB.

[0114] In the read (10) command CDB, bits 0 through 4 of the sixth byte 6 represent the group number. The group number can represent the context identifier (Context ID) associated with the read request. Bits 5 through 7 of the sixth byte 6 can be reserved.

[0115] The seventh and eighth bytes of the read (10) command CDB, 7 and 8, represent the transfer length. The transfer length can represent the length of the data to be read by the read request.

[0116] The ninth byte 9 of the read (10) command CDB can include control. For example, control can be "00h".

[0117] Reading the CDB may include information indicating that the read command is a read command targeting at least two or more logical addresses. For example, it may include a read mode message indicating whether the read command is a multiple read command requesting to read at least two or more logical addresses or a normal read command requesting to read one logical address. In embodiments, the read mode message may represent each read mode as a predetermined value 0 or 1. Based on the read mode message, the memory controller may perform a normal read operation or a multiple read operation.

[0118] In an embodiment, reading the CDB may include information (read mode message) indicating whether a read command is for at least two or more logical addresses in a reserved field within the read CDB. For example, in the case of a read (10) command, the read mode message may be included in a reserved field located in the second bit 2 of the first byte 1, such as... Figure 8 As shown, but not limited to, the read mode message can be included in the various reserved fields in the read CDB.

[0119] When performing a read operation on at least two or more logical addresses based on a read mode message (multiple read operation), the logical block address information stored in the additional header segment can be used to perform the multiple read operation. When performing a read operation on a single logical address based on a read mode message (normal read operation), the logical block address information stored in the read CDB can be used to perform the normal read operation. The read CDB may include information about the starting logical block address of the region to be read during the normal read operation and the transmission length corresponding to that starting logical block address. However, embodiments are not limited to including only the logical block address information related to the normal read operation in the read CDB, and the logical block address information may be stored in the additional header segment or in other fields of the read command.

[0120] Reference Figure 8 The content described can be modified according to the corresponding format and applied to, for example... Figure 7 and Figure 9 Another type of CDB reading is shown.

[0121] Figure 10 This is a diagram illustrating an example of an additional header segment including information about at least two or more logical addresses, according to an embodiment of this disclosure.

[0122] Reference Figure 10 The additional header field may include information about multiple logical start block addresses (LBAs) and the transmission length corresponding to each of those LBAs. For example, such as Figure 10 As shown, when the additional header segments include LBA#1-TRANSFERLENGTH#1, LBA#2-TRANSFERLENGTH#2, LBA#3-TRANSFER LENGTH#3, and LBA#4-TRANSFERLENGTH#4, the memory controller can simultaneously read data from the following regions: the region corresponding to TRANSFER LENGTH#1, starting from PBA#1 which is the physical block address (PBA) corresponding to LBA#1; the region corresponding to TRANSFER LENGTH#2, starting from PBA#2; the region corresponding to TRANSFER LENGTH#3, starting from PBA#3; and the region corresponding to TRANSFER LENGTH#4, starting from PBA#4.

[0123] Figure 11 This is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0124] Reference Figure 11 The memory controller 200 may include a read request processor 210, a mapped data storage device 220, and a read operation controller 230.

[0125] The memory controller 200 can receive a read request from the host 400 to read data stored in the memory device.

[0126] At this point, a read request may include a basic header field, transaction-specific fields, and additional header fields.

[0127] The basic header segment may be a part of a request typically included in transmissions and receptions between an external host and a memory controller, and may include a Total Extra Header Length (EHSLength) indicating the length of additional header segments. In an embodiment, because the read request includes additional header segments, the Total Extra Header Length may have a non-zero value.

[0128] Transaction-specific fields may include a Read Command Descriptor Block (CDB). The Read CDB may include information indicating whether a read request is for at least two or more logical addresses. For example, a read mode message indicates whether the read request is a multiple read request requesting to read at least two logical addresses or a normal read request requesting to read one logical address. In embodiments, the read mode message may represent each read mode as a predetermined value 0 or 1. Based on the read mode message, the memory controller may perform a normal read operation or a multiple read operation. In embodiments, the read CDB may include information indicating whether a read request is for at least two or more logical addresses (the read mode message) in reserved fields within the read CDB.

[0129] The additional header field may include logical block addresses for multiple read operations. These logical block addresses may include information about multiple starting logical block addresses and the transfer length corresponding to each of those starting logical block addresses.

[0130] The read request processor 210 can receive read requests from an external host and obtain physical addresses corresponding to one or more logical addresses included in the read request from the mapped data storage device 220. Additionally, the read request processor 210 can check whether the read request is for at least two or more logical addresses. In an embodiment, the read request processor 210 can check a read mode message included in the read request. The read mode message, which indicates whether the read request is for at least two or more logical addresses, can be included in a transaction-specific field, and more specifically, in a reserved field within the read CDB included in the transaction-specific field.

[0131] The mapping data storage device 220 may include a logical-to-physical address mapping table that configures the mapping relationship between logical addresses and physical addresses. As a result of the read request processor 210 checking the read mode message, when the read request is for at least two or more logical addresses (multiple read mode), the mapping data storage device 220 may provide the read request processor 210 with mapping data corresponding to the two or more logical addresses included in the additional header segment of the read request. As a result of the read request processor 210 checking the read mode message, when the read request is for a single logical address (normal read mode), the mapping data storage device 220 may provide the read request processor 210 with mapping data corresponding to the single logical address included in the read CDB in the transaction-specific field of the read request. However, the embodiment is not limited to the case where logical block address information for normal read operations is included in the read CDB, and logical block address information may be included in various fields of a read request with additional header segments.

[0132] The read operation controller 230 can control the memory device to perform a read operation according to the instructions of the read request processor 210. The read request processor 210 can provide the read operation controller 230 with mapping data received from the mapped data storage device 220. The read operation controller 230 can control the memory device to perform a read operation on the corresponding address based on the mapping data received from the read request processor 210. More specifically, the read operation controller 230 can provide the memory device with a read command for a physical address corresponding to one or more logical addresses included in the read request.

[0133] Figure 12 This is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0134] Reference Figure 12 In operation S1201, the storage device can receive a read command from an external host requesting to read data stored in the storage device. More specifically, the memory controller in the storage device can receive the read command.

[0135] At this point, the read command can include the basic header field, transaction-specific fields, and additional header fields.

[0136] The basic header segment may be a portion of commands typically included in transmissions and receptions between an external host and a memory controller, and may include a Total Extra Header Length (EHSLength) indicating the length of additional header segments. In an embodiment, since the read command includes additional header segments, the Total Extra Header Length may have a non-zero value.

[0137] Transaction-specific fields may include a Read Command Descriptor Block (CDB). The Read CDB may include information indicating whether a read command is a read command targeting at least two or more logical addresses. For example, a read mode message indicates whether a read command is a multi-read command requesting to read at least two logical addresses or a normal read command requesting to read one logical address. In embodiments, the read mode message may represent each read mode as a predetermined value 0 or 1. Based on the read mode message, the memory controller may perform a normal read operation or a multi-read operation. In embodiments, the read CDB may include information indicating whether a read command is a read command targeting at least two or more logical addresses (the read mode message) in reserved fields within the read CDB.

[0138] The additional header field may include logical block addresses for multiple read operations. These logical block addresses may include information about multiple starting logical block addresses and the transfer length corresponding to each of those starting logical block addresses.

[0139] In operation S1203, the storage device can check the read mode message stored in the CDB.

[0140] In operation S1205, when the read mode message indicates a multiple read mode, that is, when it indicates that the read command is a read command for at least two or more logical addresses, the multiple read operation of operation S1207 can be performed, that is, a read operation for at least two or more logical addresses can be performed.

[0141] In operation S1205, when the read mode indication message is not a multi-read mode, that is, when the read command is not a read command for at least two or more logical addresses, and when the normal read mode is indicated, the normal read operation of operation S1209 can be performed, that is, a read operation for one logical address can be performed.

[0142] In other words, based on the read mode message stored in the CDB, multiple read operations can be performed, or normal read operations can be performed without performing multiple read operations.

[0143] Figure 13 This is a flowchart illustrating multiple read operations of a storage device according to an embodiment of the present disclosure.

[0144] Reference Figure 12 and Figure 13 In operation S1301, the storage device can perform a multiple read operation based on the read mode message stored in the CDB. In this case, in operation S1303, the multiple read operation can be performed using information about at least two or more logical addresses included in the additional header segment of the read command. The information about the at least two or more logical addresses included in the additional header segment can include information about at least two or more starting logical block addresses used for the multiple read operation and the transmission length corresponding to each of the at least two or more starting logical block addresses.

[0145] Figure 14 This is a flowchart illustrating a normal read operation of a storage device according to an embodiment of the present disclosure.

[0146] Reference Figure 12 and Figure 14 In operation S1401, the storage device can perform a normal read operation based on the read mode message stored in the read CDB. In this case, in operation S1403, a transaction-specific field can be used, more specifically, to perform the normal read operation using information about a logical address included in the read CDB. The information about the logical address included in the read CDB can include information about a starting logical block address used for the normal read operation and the transfer length corresponding to that starting logical block address.

[0147] However, the embodiments are not limited to the case where logical block address information for normal read operations is included in the read CDB, and logical block address information may be included in various fields of a read command that includes additional header segments.

[0148] Figure 15 This is a diagram illustrating the data provision order of a storage device according to an embodiment of the present disclosure.

[0149] Reference Figure 1 , Figure 4 and Figure 15 The memory controller in the storage device, which receives a read command from the host requesting to read data stored in the storage device, can perform a read operation to provide the acquired data to the host.

[0150] When performing a read operation targeting at least two or more logical addresses (i.e., a multiple read operation), data from multiple regions with non-contiguous logical addresses can be read and acquired simultaneously. For example, ... Figure 14 As shown, it can simultaneously read DATA#1 of the region corresponding to LBA#1-TRANSFERLENGTH#1, DATA#2 of the region corresponding to LBA#2-TRANSFERLENGTH#2, DATA#3 of the region corresponding to LBA#3-TRANSFERLENGTH#3, and DATA#4 of the region corresponding to LBA#4-TRANSFERLENGTH#4 stored in the additional header segment of the read command.

[0151] At this point, the data obtained through multiple read operations can be provided to the host according to the order of the logical block address information included in the additional header segment. For example, such as Figure 12 As shown, when the physical block address information in the additional header segment of a read command is described in the order of 1) LBA#1-TRANSFER LENGTH#1, 2) LBA#2-TRANSFER LENGTH#2, 3) LBA#3-TRANSFER LENGTH#3, and 4) LBA#4-TRANSFER LENGTH#4, data can also be provided to the host in the order of 1) DATA#1, 2) DATA#2, 3) DATA#3, and 4) DATA#4. However, the data is not limited to a specific order, and data can be provided in the reverse order. Furthermore, data from multiple regions can be provided to the host in various preset orders.

[0152] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0153] Reference Figure 16 The memory controller 1600 may include a processor 1610, RAM 1620, error correction circuitry 1630, host interface 1640, ROM 1650, and flash memory interface 1660.

[0154] The processor 1610 can control all operations of the memory controller 1600.

[0155] RAM 1620 can be used as a buffer memory, cache memory, and operation memory for memory controller 1600.

[0156] ROM 1650 can store various information required to operate memory controller 1600 in firmware form.

[0157] The memory controller 1600 can communicate with external devices (e.g., host 400, application processor, etc.) via host interface 1640.

[0158] The memory controller 1600 can communicate with the memory device 100 via the flash memory interface 1660. The memory controller 1600 can transmit commands (CMD), addresses (ADDR), control signals (CTRL), etc., to the memory device 100 via the flash memory interface 1660, and receive data (DATA). For example, the flash memory interface 1660 may include a NAND interface.

[0159] Figure 17 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0160] Reference Figure 17 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0161] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read operations, programming operations, erase operations, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host computer. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 may be used with reference to... Figure 1 The memory controller 200 described is implemented in the same manner.

[0162] For example, memory controller 2100 may include components such as random access memory (RAM), processor, host interface, memory interface, and error corrector.

[0163] The memory controller 2100 can communicate with an external device via connector 2300. The memory controller 2100 can communicate with the external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with the external device via at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 2300 can be defined by at least one of the aforementioned communication standards.

[0164] For example, memory device 2200 can be configured with various non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0165] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association, PCMCIA), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), and universal flash memory (UFS).

[0166] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0167] Reference Figure 18 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0168] According to embodiments of this disclosure, the SSD controller 3210 can execute reference... Figure 1 The functions of the memory controller 200 are described.

[0169] SSD controller 3210 can control multiple flash storage devices 3221 to 322n in response to signals received from host 3100. For example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0170] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power from host 3100 and use that power to charge the SSD. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. For example, auxiliary power supply 3230 can be located inside SSD 3200 or external to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to SSD 3200.

[0171] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0172] Figure 19 This is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure.

[0173] Reference Figure 19 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0174] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., that control components included in user system 4000. Application processor 4100 can be configured as a system-on-a-chip (SoC).

[0175] Memory module 4200 operates as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and configured as a single semiconductor package.

[0176] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), LTE, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, network module 4300 can be included in application processor 4100.

[0177] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented using non-volatile semiconductor memory elements such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, storage module 4400 can be configured as a removable storage device (removable drive), such as a memory card and external drive of user system 4000.

[0178] For example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be configured with reference to... Figure 1 The memory device 100 described herein operates in the same manner. The memory module 4400 can operate in the same manner as the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0179] User interface 4500 may include interfaces for inputting data or instructions to application processor 4100 or for outputting data to external devices. For example, user interface 4500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0180] Embodiments of this disclosure also provide a storage device and its operation method capable of performing various operations other than the read operations described above on multiple logical addresses. For example, write operations can be performed on multiple logical addresses in the same manner as the multiple read operations described above.

[0181] According to embodiments of this disclosure, a storage device may include a memory device and a memory controller configured to receive write commands from an external host and control the memory device based on the write commands, wherein the write command may include: a basic header field, typically included in commands transmitted and received between the external host and the memory controller, and including information indicating that the write command is a command for requesting data to be stored in the memory device; a transaction-specific field, including information indicating that the write command is a write command for at least two or more logical addresses; and an additional header field, including information about at least two or more logical addresses.

[0182] According to embodiments of this disclosure, a method of operating a storage device includes a memory device and a memory controller for controlling the memory device. The method may include: receiving a write command from an external host by the memory controller and performing a write operation based on information about at least two or more logical addresses. The write command includes: a basic header segment, typically included in commands transmitted and received between the external host and the memory controller, and including information indicating a write command for requesting data to be stored in the memory device; a transaction-specific field, including information indicating that the write command is a write command for at least two or more logical addresses; and an additional header segment, including information about at least two or more logical addresses.

[0183] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the claims. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: Memory devices; as well as The memory controller receives read commands from an external host and controls the memory device according to the read commands. The read command includes: The basic header segment is included in the command transmitted between the external host and the memory controller, and includes information indicating that the read command is a command for requesting data stored in the memory device; Transaction-specific fields include information indicating that the read command is a read command targeting at least two or more logical addresses; as well as An additional header field includes information about the at least two or more logical addresses.

2. The storage device of claim 1, wherein the information regarding the at least two or more logical addresses includes information regarding at least two or more starting logical block addresses and transmission lengths corresponding to the at least two or more starting logical block addresses respectively.

3. The storage device of claim 1, wherein the at least two or more logical addresses are not contiguous with each other.

4. The storage device according to claim 1, wherein the transaction-specific field includes a read command descriptor block, i.e., a read CDB.

5. The storage device of claim 4, wherein reading the CDB includes information indicating that the read command is a read command for the at least two or more logical addresses.

6. The storage device of claim 5, wherein the information indicating that the read command is a read command for the at least two or more logical addresses is included in a reserved field in the read CDB.

7. The storage device according to claim 6, wherein reading the CDB further includes an opcode field, a forced cell access field, and a group number field.

8. The storage device of claim 1, wherein the basic header segment includes a total additional header segment length field indicating the length of the additional header segment.

9. The storage device of claim 8, wherein the total extra header segment length field includes a non-zero value.

10. A method of operating a storage device, the storage device comprising a memory device and a memory controller for controlling the memory device, the method comprising: Receive a read command from an external host, the read command including: The basic header segment is included in the command transmitted between the external host and the memory controller, and includes information indicating a read command for requesting data stored in the memory device. Transaction-specific fields include information indicating that the read command is a read command targeting at least two or more logical addresses, and An additional header field includes information about the at least two or more logical addresses; and The read operation is performed based on information about the at least two or more logical addresses.

11. The method of claim 10, wherein the information regarding the at least two or more logical addresses includes information regarding the at least two or more starting logical block addresses and the transmission lengths corresponding to the at least two or more starting logical block addresses respectively.

12. The method of claim 10, wherein the basic header segment includes a total additional header segment length field indicating the length of the additional header segment.

13. The method of claim 12, wherein the total extra header length field includes non-zero values.

14. The method of claim 10, wherein the at least two or more logical addresses are not contiguous with each other.

15. The method of claim 10, wherein the transaction-specific field includes reading the command descriptor block, i.e., reading the CDB.

16. The method of claim 15, wherein reading the CDB includes information indicating that the read command is a read command for the at least two or more logical addresses.

17. The method of claim 16, wherein the information indicating that the read command is a read command for the at least two or more logical addresses is included in a reserved field in the read CDB.

18. The method of claim 10, further comprising: When the read operation is performed on the at least two or more logical addresses, the data read from the memory device is provided to the external host.

19. The method of claim 18, wherein the read data is provided to the external host according to the order of the logical block address information included in the additional header segment.

20. A memory controller that controls a memory device, the memory controller comprising: A mapping data storage device stores mapping information between the logical addresses and physical addresses of the data stored in the memory device; A read request processor receives a read request from an external host and obtains a physical address corresponding to at least one or more logical addresses included in the read request; as well as The read operation controller provides the memory device with a read command for a physical address corresponding to the at least one or more logical addresses. The read request includes: The basic header segment is included in the request transmitted and received between the external host and the memory controller, and includes information indicating that the read request is for requesting data stored in the memory device; Transaction-specific fields include information indicating that the read request is a read request for at least two or more logical addresses; and An additional header field includes information about the at least two or more logical addresses.

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